Programming languages used in this repository
-
VHDL
42.7 %
-
C
23.13 %
-
Stata
10.97 %
-
SystemVerilog
10.04 %
-
Python
5.21 %
-
Lua
5.18 %
-
Makefile
1.3 %
-
TeX
0.82 %
-
Tcl
0.24 %
-
Shell
0.21 %
-
sed
0.11 %
-
Verilog
0.1 %
Commit statistics for ce0d0232fca1f753606d4d06db95473df99decfd Sep 02 - Mar 18
- Total: 266 commits
- Average per day: 0.2 commits
- Authors: 3
Commits per day of month
Commits per weekday
Commits per day hour (UTC)