Commits · v3.0.4 · Projects / FMC DEL 1ns 4cha

09 Dec, 2020 5 commits
- hdl: use vme64x-core commit compatible with svec_base_wr... · 716e4f6d
  Tomasz Wlostowski authored Dec 09, 2020
  
  716e4f6d
- sw:drv: add link to FMC slot in sysfs · cb215759
  Federico Vaga authored Dec 04, 2020
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Signed-off-by: Federico Vaga <federico.vaga@cern.ch>
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  cb215759
- sw:drv: fix IPMI fru header file · fb99e1c5
  Federico Vaga authored Dec 04, 2020
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Signed-off-by: Federico Vaga <federico.vaga@cern.ch>
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  fb99e1c5
- hdl/testbench: use GN4124 BFM from gn4124-core repo · ddc48d05
  Tomasz Wlostowski authored Dec 09, 2020
  
  ddc48d05
- hdl: updated submodules to be in sync with SVEC/SPEC BSPs · bffde3f5
  Tomasz Wlostowski authored Dec 09, 2020
  
  bffde3f5
04 Dec, 2020 1 commit
- Merge branch 'proposed_master' · b998db99
  Tomasz Wlostowski authored Dec 04, 2020
  
  b998db99
03 Dec, 2020 1 commit
- hdl: fixed version register layout to match specification · 9fe7f7eb
  Tomasz Wlostowski authored Dec 03, 2020
  
  9fe7f7eb
02 Dec, 2020 4 commits
- hdl: correct generation of source ids · 351c88a7
  Tomasz Wlostowski authored Dec 02, 2020
  
  351c88a7
- hdl: updated submodules prior to v3.0.4 release · ca5f16b7
  Tomasz Wlostowski authored Dec 02, 2020
  
  ca5f16b7
- hdl/top: clean up legacy (pre-convention) toplevels · ee778274
  Tomasz Wlostowski authored Dec 02, 2020
  
  ee778274
- hdl: keep IODELAY adjustments in clk_ref clock domain, increase taps register length to 8 bits · 3b69f101
  Tomasz Wlostowski authored Dec 02, 2020
  
  3b69f101
08 Nov, 2020 1 commit
- Merge branch 'tom-spec-convention' into proposed_master · ecd0bb00
  Tomasz Wlostowski authored Nov 08, 2020
  
  ecd0bb00
07 Oct, 2020 3 commits
- Merge branch 'release/v3.0.3' into master · 0ad5fdb0
  Federico Vaga authored Oct 07, 2020
  
  0ad5fdb0
- Update changelog for release · 68bd706f
  Federico Vaga authored Oct 07, 2020
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Signed-off-by: Federico Vaga <federico.vaga@cern.ch>
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  68bd706f
- sw:drv: add parent to hw ZIO device · 7dcab717
  Federico Vaga authored Oct 07, 2020
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Signed-off-by: Federico Vaga <federico.vaga@cern.ch>
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  7dcab717
25 Sep, 2020 7 commits

Merge tag 'v3.0.2' into develop · 8d8efddc

Federico Vaga authored Sep 25, 2020

3.0.2 - 2020-09-25
==================

Added
-----
- bld: cppcheck target for software

Fixed
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- sw: SVEC, load device driver instance only if the mezzanine is present.

8d8efddc

Merge branch 'release/v3.0.2' into master · 8bef31c9
Federico Vaga authored Sep 25, 2020

8bef31c9
update CHANGELOG for release · a6c733f9
Federico Vaga authored Sep 25, 2020
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Signed-off-by: Federico Vaga <federico.vaga@cern.ch>
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a6c733f9
ignore compile_commands.json file · 975afcf0
Federico Vaga authored Sep 25, 2020
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Signed-off-by: Federico Vaga <federico.vaga@cern.ch>
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975afcf0
bld: add cppcheck target · a79ab863
Federico Vaga authored Sep 25, 2020
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Signed-off-by: Federico Vaga <federico.vaga@cern.ch>
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a79ab863
sw:drv: avoid CERN build error with old make targets · 0bb60bb2
Federico Vaga authored Sep 25, 2020
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Signed-off-by: Federico Vaga <federico.vaga@cern.ch>
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0bb60bb2

sw:drv: do not register FD if no mezzanine · aa1f12f1

Federico Vaga authored Sep 25, 2020

If the FMC Delay mezzanine is not present, then there is no reason to
register its instance. Actually, it could be risky because the driver
may do actions that could compromise the FPGA configuration.
Signed-off-by: Federico Vaga <federico.vaga@cern.ch>

aa1f12f1

04 Jun, 2020 4 commits
- doc: one author per line in LaTeX · 9c88f212
  Federico Vaga authored Jun 04, 2020
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Signed-off-by: Federico Vaga <federico.vaga@cern.ch>
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  9c88f212
- add Federico Vaga as author in documentation · f91ab4fb
  Federico Vaga authored Jun 04, 2020
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Signed-off-by: Federico Vaga <federico.vaga@cern.ch>
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  f91ab4fb
- Merge branch 'release/v3.0.1' · ad3211df
  Federico Vaga authored Jun 04, 2020
  
  ad3211df
- update CHANGELOG for release · 8ea54188
  Federico Vaga authored Jun 04, 2020
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Signed-off-by: Federico Vaga <federico.vaga@cern.ch>
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  8ea54188
03 Jun, 2020 3 commits
- port CHANGELOG to BE-CO-HT format · ff801d80
  Federico Vaga authored Jun 03, 2020
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Described here:

https://gitlab.cern.ch/be-co-ht-documents/project-management-guidelinesSigned-off-by: Federico Vaga <federico.vaga@cern.ch>
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  ff801d80
- remove duplicated changelog · d1cde3be
  Federico Vaga authored Jun 03, 2020
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Signed-off-by: Federico Vaga <federico.vaga@cern.ch>
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  d1cde3be
- sw:bld: pass proper version to module info · 411ce3a6
  Federico Vaga authored Jun 03, 2020
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Signed-off-by: Federico Vaga <federico.vaga@cern.ch>
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  411ce3a6
02 Jun, 2020 6 commits
- Updated changelog · ab08b3a5
  Tomasz Wlostowski authored Jun 02, 2020
  
  ab08b3a5
- hdl/syn: updated SVEC ISE project · 85815f82
  Tomasz Wlostowski authored Jun 02, 2020
  
  85815f82
- hdl/top: use work entity instead of component-based instantiation · 8670cf9e
  Tomasz Wlostowski authored Jun 02, 2020
  
  8670cf9e
- hdl/testbench: trivial SVEC testbench · 3a565b1f
  Tomasz Wlostowski authored Jun 02, 2020
  
  3a565b1f
- hdl: extends IODELAY N_TAPS register to 8 bits · 6216cf6a
  Tomasz Wlostowski authored Jun 02, 2020
  
  6216cf6a
- hdl/ip_cores: use release versions of SPEC/SVEC submodules · b362e383
  Tomasz Wlostowski authored Jun 02, 2020
  
  b362e383
28 May, 2020 2 commits
- sw:drv: init IODELAY_ADJ to 0 · 56e65555
  Federico Vaga authored May 28, 2020
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Signed-off-by: Federico Vaga <federico.vaga@cern.ch>
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  56e65555
- sw:drv: add PLL dump in debugfs · a5b2f0e1
  Federico Vaga authored May 28, 2020
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Signed-off-by: Federico Vaga <federico.vaga@cern.ch>
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  a5b2f0e1
27 May, 2020 3 commits
- Merge branch 'feature/build-improve' into develop · 8b817c18
  Federico Vaga authored May 27, 2020
  
  8b817c18
- sw: show calibration tool version · 594ff1de
  Federico Vaga authored May 27, 2020
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Signed-off-by: Federico Vaga <federico.vaga@cern.ch>
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  594ff1de
- sw:bld: clean/install calibration tool · bcafeb8d
  Federico Vaga authored May 27, 2020
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Signed-off-by: Federico Vaga <federico.vaga@cern.ch>
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  bcafeb8d