Commits · dcea8ebe623ce8f7bb6b00c63eef5467eed2f81c · Projects / FMC DEL 1ns 4cha · Open Hardware Repository

04 Apr, 2012 1 commit
- software: extended test procedures, added delay line linearity measurement · dcea8ebe
  Tomasz Wlostowski authored Apr 04, 2012
  
  dcea8ebe
03 Apr, 2012 3 commits
- software: uploaded spec_common.c (SPEC initialization for all test programs) · 6aa82cf3
  Tomasz Wlostowski authored Apr 03, 2012
  
  6aa82cf3
- software: temporary fix to support more than 1 SPEC · 37d297c7
  Tomasz Wlostowski authored Apr 03, 2012
  
  37d297c7
- software: added EEPROM programming tools · 7f7c3541
  Tomasz Wlostowski authored Apr 03, 2012
  
  7f7c3541
29 Feb, 2012 6 commits
- syn/spec/non_wr: binary with fixed pulse generator · 150cffdd
  Tomasz Wlostowski authored Feb 29, 2012
  
  150cffdd
- hdl/fd_main_wishbone_slave: added DBGOUT register for Peltier PWM control · 60d30547
  Tomasz Wlostowski authored Feb 29, 2012
  
  60d30547
- top level: reordered outputs to match the numbers on the front panel · 2359142a
  Tomasz Wlostowski authored Feb 29, 2012
  
  2359142a
- hdl/fd_channel_wb_slave: DCR.PG_ARM bit should be MONOSTABLE · 1c5ffa8d
  Tomasz Wlostowski authored Feb 29, 2012
  
  1c5ffa8d
- hdl: fd_delay_channel_driver.vhd: fixed RCR.CONT bit detection (now the core can… · feae54fb
  Tomasz Wlostowski authored Feb 29, 2012
```
hdl: fd_delay_channel_driver.vhd: fixed RCR.CONT bit detection (now the core can produce continuous waveforms)
```
  feae54fb
- software: added pulse generator mode, temperature calibration program and PPS/10MHz demo program · 8f422f8f
  Tomasz Wlostowski authored Feb 29, 2012
  
  8f422f8f
28 Feb, 2012 1 commit
- V4 PCB design uploaded (minor fixes wrs the V3) · 828b9fab
  Tomasz Wlostowski authored Feb 28, 2012
  
  828b9fab
27 Feb, 2012 4 commits
- syn/spec/non_wr: demo bitstream for V3 · 8c745caf
  Tomasz Wlostowski authored Feb 27, 2012
  
  8c745caf
- software: C library/test program for V3 · f82c33d7
  Tomasz Wlostowski authored Feb 27, 2012
  
  f82c33d7
- software: added onewire master and DS18XXX driver · ef09fc06
  Tomasz Wlostowski authored Feb 27, 2012
  
  ef09fc06
- software: updated register definitions and header for V3 HW · d459367b
  Tomasz Wlostowski authored Feb 27, 2012
  
  d459367b
26 Feb, 2012 9 commits
- syn/top: SPEC non-whiterabbit top level updated for V3 · 9cc135fb
  Tomasz Wlostowski authored Feb 26, 2012
  
  9cc135fb
- hdl: assignment size bug fixed · 6f48bd55
  Tomasz Wlostowski authored Feb 26, 2012
  
  6f48bd55
- platform: uploaded platform-dependend code · 354391a9
  Tomasz Wlostowski authored Feb 26, 2012
  
  354391a9
- hdl: missing signal fix · 9aef0922
  Tomasz Wlostowski authored Feb 26, 2012
  
  9aef0922
- hdl: renamed timing components to avoid conflicts with wr-cores · 5c08b95a
  Tomasz Wlostowski authored Feb 26, 2012
  
  5c08b95a
- hdl: docs for wbgen2 registers · f2a729ec
  Tomasz Wlostowski authored Feb 26, 2012
  
  f2a729ec
- hdl: testing release for V3 hardware · 481fc584
  Tomasz Wlostowski authored Feb 26, 2012
  
  481fc584
- removed fd_ts_normalizer (no longer used) · f4ad16ac
  Tomasz Wlostowski authored Feb 26, 2012
  
  f4ad16ac
- hdl: removed TDC rearm unit (no longer necessary), renamed WB register block · 47b7c000
  Tomasz Wlostowski authored Feb 26, 2012
  
  47b7c000
20 Dec, 2011 2 commits
- software/headers: adapted to V3 HW · b75ccc85
  Tomasz Wlostowski authored Dec 20, 2011
  
  b75ccc85
- hdl: added extra comments · 8e1858c1
  Tomasz Wlostowski authored Dec 20, 2011
  
  8e1858c1
10 Nov, 2011 9 commits
- hdl/syn: bitstream for SPEC WR Demo · 9a1fa649
  Tomasz Wlostowski authored Nov 10, 2011
  
  9a1fa649
- hdl/syn: synthesis files for SPEC WR Demo · 0702773d
  Tomasz Wlostowski authored Nov 10, 2011
  
  0702773d
- hdl/top: uploaded demo of FineDelay synced with WR via WR PTP Core · 5ffd4ff9
  Tomasz Wlostowski authored Nov 10, 2011
  
  5ffd4ff9
- fine_delay_core: added bitbanged I2C master and appropriate control registers · 361a3128
  Tomasz Wlostowski authored Nov 10, 2011
  
  361a3128
- HDL: fd_spi_master: change MOSI status and sample MISO in between SCK edges · c43e9ebc
  Tomasz Wlostowski authored Nov 10, 2011
  
  c43e9ebc
- HDL: fd_spi_dac_arbiter.vhd: fixed missing readouts · 5ba77508
  Tomasz Wlostowski authored Nov 10, 2011
  
  5ba77508
- HDL: fd_rearm_generator.vhd: rearm unit should ignore disabled outputs · 6b580f28
  Tomasz Wlostowski authored Nov 10, 2011
  
  6b580f28
- HDL: fd_delay_channel_driver.vhd: re-arm the TDC if the output is disabled during pulse generation · a176765a
  Tomasz Wlostowski authored Nov 10, 2011
  
  a176765a
- HDL: fd_acam_timestamper: extended read pulses to avoid SI problems · 49bebe17
  Tomasz Wlostowski authored Nov 10, 2011
  
  49bebe17
06 Nov, 2011 3 commits
- software: added PyQT demo application · caaa2d4c
  Tomasz Wlostowski authored Nov 06, 2011
  
  caaa2d4c
- software: updated regisers layout · 0cae1105
  Tomasz Wlostowski authored Nov 06, 2011
  
  0cae1105
- software: fdelay library: remote operation via Ethernet · 79672157
  Tomasz Wlostowski authored Nov 06, 2011
  
  79672157
31 Oct, 2011 2 commits
- Merge branch 'master' of ohwr.org:fmc-projects/fmc-delay-1ns-8cha · 3e17d062
  Tomasz Wlostowski authored Oct 31, 2011
  
  3e17d062
- updated hdlmake manifests · de052457
  Tomasz Wlostowski authored Oct 31, 2011
  
  de052457