The commit also adds possibility of wiring the channel driver 0 and ACAM data valid strobes/state indication
to the front panel LEMO connectors on the SVEC carrier, for the purpose of debugging ACAM/output stage processing latency.

This prevents the WR Core from messing up with the FD DAC settings when an incorrect
WRC firmware is loaded.

hdl/syn/spec: updated the WR core builtin firmware to the 2.1 official release. Enabled synthesis with embedded firmware by default.

rtl: removed alignment of the DCR register to 8 (it was a bug hidden by wrong alignment handling bug in wbgen)

Conflicts:
	hdl/rtl/fd_acam_timestamp_postprocessor.vhd
	hdl/rtl/fd_acam_timestamper.vhd
	hdl/testbench/svec_wr_top/main.sv
	hdl/top/spec/wr/spec_top.vhd
	hdl/top/svec/wr/svec_top.ucf
	hdl/top/svec/wr/svec_top.vhd