FMC DEL 1ns 4cha:ce0d0232fca1f753606d4d06db95473df99decfd commitshttps://ohwr.org/project/fmc-delay-1ns-8cha/commits/ce0d0232fca1f753606d4d06db95473df99decfd2014-03-18T20:07:00Zhttps://ohwr.org/project/fmc-delay-1ns-8cha/commit/ce0d0232fca1f753606d4d06db95473df99decfdhdl/syn: bundled release 2.1 of the WR core for WRC firmware integration2014-03-18T20:07:00ZTomasz Włostowskitomasz.wlostowski@cern.chhttps://ohwr.org/project/fmc-delay-1ns-8cha/commit/41151ff396cacaf3e2faaeb3ff2759af9d7a80dahdl/top/svec/wr/svec_top.ucf: relax inter-clock domain timing2014-03-18T20:05:46ZTomasz Włostowskitomasz.wlostowski@cern.chhttps://ohwr.org/project/fmc-delay-1ns-8cha/commit/39480871158d3f80dcf07ef57b85dd710311586ahdl/top/svec/wr/bicolor_led_ctrl.vhd: eliminate latch2014-03-18T20:05:18ZTomasz Włostowskitomasz.wlostowski@cern.chhttps://ohwr.org/project/fmc-delay-1ns-8cha/commit/556b339f9c6ab8b11f120defcb2d0fe77711708ahdl/ip_cores: add gn4124-core as a submodule2014-03-18T20:04:30ZTomasz Włostowskitomasz.wlostowski@cern.chhttps://ohwr.org/project/fmc-delay-1ns-8cha/commit/70c0e0331fcf94f3067f5f677c01b59eee534b63hdl/syn/svec: updated ISE project to use local ip_cores/ repo checkouts2014-03-17T14:57:28ZTomasz Włostowskitomasz.wlostowski@cern.chhttps://ohwr.org/project/fmc-delay-1ns-8cha/commit/e93ae2978c465668185674a0cb69d42857f6994bhdl/rtl/fd_spi_dac_arbiter.vhd: mask WR Core DAC write signal with TCR.WR_ENA...2014-03-17T14:54:03ZTomasz Włostowskitomasz.wlostowski@cern.ch
This prevents the WR Core from messing up with the FD DAC settings when an incorrect
WRC firmware is loaded.https://ohwr.org/project/fmc-delay-1ns-8cha/commit/d3e6cf13b982c4c7708007e47ab57eade946f9d0hdl: added submodule references for SVEC release bitstream2014-03-13T09:45:05ZTomasz Włostowskitomasz.wlostowski@cern.chhttps://ohwr.org/project/fmc-delay-1ns-8cha/commit/ff0bea1bbff1ca30908062afba28635340160636hdl/top/svec: removed redundant xvme64x_core.vhd2014-03-13T08:55:00ZTomasz Włostowskitomasz.wlostowski@cern.chhttps://ohwr.org/project/fmc-delay-1ns-8cha/commit/8ea34c3dd7d0fe6e272d5bf07fab75d72b999db5hdl/top/svec: fixed WRPC SDB bridge offset (should be relative)2014-01-21T09:11:21ZTomasz Włostowskitomasz.wlostowski@cern.chhttps://ohwr.org/project/fmc-delay-1ns-8cha/commit/bd45952684521ec48302f13a70f74bec9d3c4a73hdl/top/svec: WR support for both mezzanines (migrated to WRPC with multiple ...2014-01-21T09:10:42ZTomasz Włostowskitomasz.wlostowski@cern.chhttps://ohwr.org/project/fmc-delay-1ns-8cha/commit/881f5c68d483200bfff5a7e5fb72cdac0c3a4b5ahdl/top/svec: moved vme64x-core repo to git2014-01-21T09:06:22ZTomasz Włostowskitomasz.wlostowski@cern.chhttps://ohwr.org/project/fmc-delay-1ns-8cha/commit/cec52178a4b9c724ac3ffc3797b4aee52a47e652hdl/syn/spec: updated the WR core builtin firmware to the 2.1 official release.…2014-01-17T14:26:37ZTomasz Włostowskitomasz.wlostowski@cern.chhdl/syn/spec: updated the WR core builtin firmware to the 2.1 official release. Enabled synthesis with embedded firmware by default.
https://ohwr.org/project/fmc-delay-1ns-8cha/commit/c617457b9058f800cc7a42febe244cff4fe5291bhdl/top/spec: added missing constraints on GTP RX clock2014-01-17T14:25:28ZTomasz Włostowskitomasz.wlostowski@cern.chhttps://ohwr.org/project/fmc-delay-1ns-8cha/commit/27f3e721a99f1f1efc680b4836661afbfcf64f86hdl/top/spec: migrate to git version of the Gennum core2014-01-17T14:25:06ZTomasz Włostowskitomasz.wlostowski@cern.chhttps://ohwr.org/project/fmc-delay-1ns-8cha/commit/d78c214c48009a4a65d5e7a18bee79e8f07fff86rtl: removed alignment of the DCR register to 8 (it was a bug hidden by wrong…2013-12-04T16:22:10ZTomasz Włostowskitomasz.wlostowski@cern.chrtl: removed alignment of the DCR register to 8 (it was a bug hidden by wrong alignment handling bug in wbgen)
https://ohwr.org/project/fmc-delay-1ns-8cha/commit/b2a1db4e2d3056d840bc9db60e1e1d19f6a60b37doc: long term test report2013-11-07T13:18:43ZTomasz Włostowskitomasz.wlostowski@cern.chhttps://ohwr.org/project/fmc-delay-1ns-8cha/commit/ddbf6ec04cb2e07eb083ad1a0d6e0ac1f2a41bf1hdl/top/spec/wr/spec_top.vhd: updated to the multi-aux clock WR core2013-09-09T14:38:39ZTomasz Włostowskitomasz.wlostowski@cern.chhttps://ohwr.org/project/fmc-delay-1ns-8cha/commit/605cafb38f60c447fbfa4211cfecd25a02ce4d37rtl/fd_channel_wishbone_slave: FRR register should be in clk_ref domain2013-07-25T09:37:16ZTomasz Włostowskitomasz.wlostowski@cern.chhttps://ohwr.org/project/fmc-delay-1ns-8cha/commit/e8cf78762b0adeee9d296f49759402338d72407edoc/design-notes: fixes after Erik's feedback2013-07-09T17:29:25ZTomasz Włostowskitomasz.wlostowski@cern.chhttps://ohwr.org/project/fmc-delay-1ns-8cha/commit/dc61674fb8980632a250615ed9cada7bdfe3b1cbdoc/design-notes: fixes after Javier's feedback2013-07-04T16:20:06ZTomasz Włostowskitomasz.wlostowski@cern.chhttps://ohwr.org/project/fmc-delay-1ns-8cha/commit/f5f3da02452734a8e699d29eebfb62607a07cf8dhdl/rtl: fix unclear timebase offset signal name2013-07-04T08:46:55ZTomasz Włostowskitomasz.wlostowski@cern.chhttps://ohwr.org/project/fmc-delay-1ns-8cha/commit/4e9db31d8e9ea932d855e759df9b96c0d04be320rtl,doc: fixes in Wishbone registers documentation2013-07-04T08:44:16ZTomasz Włostowskitomasz.wlostowski@cern.chhttps://ohwr.org/project/fmc-delay-1ns-8cha/commit/14302385167810205fc2103e4956da9477ddbea7doc/design-notes: version 1.0 candidate (check for errors)2013-07-03T13:52:43ZTomasz Włostowskitomasz.wlostowski@cern.chhttps://ohwr.org/project/fmc-delay-1ns-8cha/commit/4d14ac356ef2cd622d599d9695b8f8b12f991d90hdl/top/svec: support for SVEC front panel LEDs displaying WR/VME status2013-06-11T11:57:03ZTomasz Włostowskitomasz.wlostowski@cern.chhttps://ohwr.org/project/fmc-delay-1ns-8cha/commit/1f87dc6af07fc409fc63f5676e4b98083e206009top/spec/wr: temporary revert to older WR Core timing interface2013-06-06T08:42:12ZTomasz Włostowskitomasz.wlostowski@cern.chhttps://ohwr.org/project/fmc-delay-1ns-8cha/commit/d7d5c816dec2508a72e7591059277ad00827b6aaMerge branch 'doc-design-notes'2013-05-24T09:25:52ZTomasz Włostowskitomasz.wlostowski@cern.chhttps://ohwr.org/project/fmc-delay-1ns-8cha/commit/d4ed83402f2916b788dc1b4629efcc35a13f068bdoc: wip2013-05-24T09:25:27ZTomasz Włostowskitomasz.wlostowski@cern.chhttps://ohwr.org/project/fmc-delay-1ns-8cha/commit/47fc95990531f302ee218ffe61857ded40b88a70hdl/top/svec: temporarily removed Etherbone (due to non-compatible API changes)2013-05-24T09:17:55ZTomasz Włostowskitomasz.wlostowski@cern.chhttps://ohwr.org/project/fmc-delay-1ns-8cha/commit/c3aabf7772b04ef4f1dbbff091d0636e30336cabhdl/top/svec: revert to master branch of wr-cores (1 WR slot support)2013-05-21T08:58:47ZTomasz Włostowskitomasz.wlostowski@cern.chhttps://ohwr.org/project/fmc-delay-1ns-8cha/commit/90db6efe42cd7a73160368a8742229830cc6c305Merge branch 'gmode'2013-05-17T11:33:59ZTomasz Włostowskitomasz.wlostowski@cern.ch
Conflicts:
hdl/rtl/fd_acam_timestamp_postprocessor.vhd
hdl/rtl/fd_acam_timestamper.vhd
hdl/testbench/svec_wr_top/main.sv
hdl/top/spec/wr/spec_top.vhd
hdl/top/svec/wr/svec_top.ucf
hdl/top/svec/wr/svec_top.vhdhttps://ohwr.org/project/fmc-delay-1ns-8cha/commit/a989eb86ae5b01dae35217911cc0af7f8ae2e107hdl/top/svec: slot order according to the front panel. SDB addresses in…2013-05-17T11:31:05ZTomasz Włostowskitomasz.wlostowski@cern.chhdl/top/svec: slot order according to the front panel. SDB addresses in ascending order. Fixed wrong WR Core SDB bridge address.
https://ohwr.org/project/fmc-delay-1ns-8cha/commit/5a62a8fb4da5e0c3c3b50679d84e21e4784c9252hdl/rtl/fine_delay_pkg: updated SDB version to 3, to allow the driver to…2013-05-17T11:29:25ZTomasz Włostowskitomasz.wlostowski@cern.chhdl/rtl/fine_delay_pkg: updated SDB version to 3, to allow the driver to distinguish between buggy (R-mode) and correct (G-mode) firmwares
https://ohwr.org/project/fmc-delay-1ns-8cha/commit/a5b65f8f153f3f5174b04505c8e3b9b444d47b75testbench/svec_wr_top: wip2013-05-17T11:28:15ZTomasz Włostowskitomasz.wlostowski@cern.chhttps://ohwr.org/project/fmc-delay-1ns-8cha/commit/36d423265413fc18e7cdeaa5059cb41ddaf451afhdl/top/spec: SPEC top level with VIC vector table preinitialization & synthe...2013-04-25T08:09:45ZTomasz Włostowskitomasz.wlostowski@cern.chhttps://ohwr.org/project/fmc-delay-1ns-8cha/commit/258f1b821140c07371bf47e0ca22c1041e54234ahdl/rtl/fine_delay_pkg: increased DDMTD calibration pulse length to improve d...2013-04-25T08:08:35ZTomasz Włostowskitomasz.wlostowski@cern.chhttps://ohwr.org/project/fmc-delay-1ns-8cha/commit/bd0f188439c1267235a76740b893ba8e3981255ehdl/top/svec: top level with SDB synthesis descriptor & VIC vector table prei...2013-04-16T16:18:28ZTomasz Włostowskitomasz.wlostowski@cern.chhttps://ohwr.org/project/fmc-delay-1ns-8cha/commit/dddcbe14556fa5338424b8379f43858716ec533bhdl/top/svec: removed VME core reset output2013-04-16T16:18:28ZTomasz Włostowskitomasz.wlostowski@cern.chhttps://ohwr.org/project/fmc-delay-1ns-8cha/commit/42bbc5eccd79004edb51ed9b040ae07a49981ae0syn/svec: added default release WR Core firmware to the manifest2013-04-16T16:18:28ZTomasz Włostowskitomasz.wlostowski@cern.chhttps://ohwr.org/project/fmc-delay-1ns-8cha/commit/9a910784816e03e66141c5e1bf1ecee36e876b8binclude/vme64x_bfm: some IRQ support (unfinished)2013-04-16T16:18:28ZTomasz Włostowskitomasz.wlostowski@cern.chhttps://ohwr.org/project/fmc-delay-1ns-8cha/commit/fee1b516e47ede9ffe7151748e9008999eb6e328top levels: updated for the newest WR core2013-04-16T16:18:28ZTomasz Włostowskitomasz.wlostowski@cern.ch