FMC DEL 1ns 4cha:94dbf96b46f62edd88c2f152bd81b1a77bd1b7f0 commitshttps://ohwr.org/project/fmc-delay-1ns-8cha/commits/94dbf96b46f62edd88c2f152bd81b1a77bd1b7f02012-04-11T13:50:36Zhttps://ohwr.org/project/fmc-delay-1ns-8cha/commit/94dbf96b46f62edd88c2f152bd81b1a77bd1b7f0hdl/rtl: added root manifest2012-04-11T13:50:36ZTomasz Włostowskitomasz.wlostowski@cern.chhttps://ohwr.org/project/fmc-delay-1ns-8cha/commit/05f1e8ab13f58195fe4889fe737f664b2c5e9bb5hdl/top/spec/non_wr: added PRSNT_L FMC line2012-04-11T13:50:36ZTomasz Włostowskitomasz.wlostowski@cern.chhttps://ohwr.org/project/fmc-delay-1ns-8cha/commit/d638b41fadd099dfe1071e3c4d44cf11489a7826hdl/rtl/fine_delay_core.vhd: VCXO frequency measurement, FMC presence detecti...2012-04-11T13:50:36ZTomasz Włostowskitomasz.wlostowski@cern.chhdl/rtl/fine_delay_core.vhd: VCXO frequency measurement, FMC presence detection, new (generic-configured) WB Interconnect
https://ohwr.org/project/fmc-delay-1ns-8cha/commit/d317b7b930aee13e96668122d4ffc8e32812253ahdl/rtl/fd_acam_timestamper.vhd: disable STOP input during processing of the…2012-04-11T13:50:36ZTomasz Włostowskitomasz.wlostowski@cern.chhdl/rtl/fd_acam_timestamper.vhd: disable STOP input during processing of the pulse to avoid overloading the TDC FIFO when the stop input is driven with a very fast train of pulses
https://ohwr.org/project/fmc-delay-1ns-8cha/commit/d98201c2cd4db9d86ef3b26dd21d10edcb963a7ehdl/rtl: FMC present bit & extra debugging registers added to WB slaves2012-04-11T13:50:36ZTomasz Włostowskitomasz.wlostowski@cern.chhttps://ohwr.org/project/fmc-delay-1ns-8cha/commit/9121896bb4e2bc4a2a8330d23216fff94ce43651removed legacy hdl/sim/fine_delay_regs.v (now split into two separate WB slaves)2012-04-11T13:50:36ZTomasz Włostowskitomasz.wlostowski@cern.chhttps://ohwr.org/project/fmc-delay-1ns-8cha/commit/d7c3720939a6401582dd233acf8bbff4895ba00chdl/sim/timestamp.svh: nanoseconds to counters conversion bugfix2012-04-11T13:50:36ZTomasz Włostowskitomasz.wlostowski@cern.chhttps://ohwr.org/project/fmc-delay-1ns-8cha/commit/c1a51eb0834a5bcdf071306af82bc14273e48419hdl/sim: removed local copy of simdrv_defs header2012-04-11T13:50:36ZTomasz Włostowskitomasz.wlostowski@cern.chhttps://ohwr.org/project/fmc-delay-1ns-8cha/commit/bf7cdce8457b59c6c84cc47a7c7705a8975a37aahdl/sim/acam_model.sv: increased timestamp queue size2012-04-11T13:50:36ZTomasz Włostowskitomasz.wlostowski@cern.chhttps://ohwr.org/project/fmc-delay-1ns-8cha/commit/5e5f2f1f271a7afd585378735b8473e7f7c51e9csoftware: added missing MCP23S17 reg definition2012-04-04T09:43:59ZTomasz Wlostowskitomasz.wlostowski@cern.chhttps://ohwr.org/project/fmc-delay-1ns-8cha/commit/dcea8ebe623ce8f7bb6b00c63eef5467eed2f81csoftware: extended test procedures, added delay line linearity measurement2012-04-04T09:43:22ZTomasz Wlostowskitomasz.wlostowski@cern.chhttps://ohwr.org/project/fmc-delay-1ns-8cha/commit/6aa82cf333e9f6c91aa3e693ff53a08a8ae8bc5esoftware: uploaded spec_common.c (SPEC initialization for all test programs)2012-04-03T15:50:42ZTomasz Wlostowskitomasz.wlostowski@cern.chhttps://ohwr.org/project/fmc-delay-1ns-8cha/commit/37d297c7dd617cfc1edc85cadf2d5e29a7fcf596software: temporary fix to support more than 1 SPEC2012-04-03T15:38:30ZTomasz Wlostowskitomasz.wlostowski@cern.chhttps://ohwr.org/project/fmc-delay-1ns-8cha/commit/7f7c35414160a96753b48bd6f26bef5d27a2e114software: added EEPROM programming tools2012-04-03T14:08:40ZTomasz Wlostowskitomasz.wlostowski@cern.chhttps://ohwr.org/project/fmc-delay-1ns-8cha/commit/150cffddfbb7d9ceec68ed48ce1a5c9aec67885bsyn/spec/non_wr: binary with fixed pulse generator2012-02-29T14:13:10ZTomasz Włostowskitomasz.wlostowski@cern.chhttps://ohwr.org/project/fmc-delay-1ns-8cha/commit/60d30547e18e79c48a96e08c4d8df47cf0962c76hdl/fd_main_wishbone_slave: added DBGOUT register for Peltier PWM control2012-02-29T14:13:10ZTomasz Włostowskitomasz.wlostowski@cern.chhttps://ohwr.org/project/fmc-delay-1ns-8cha/commit/2359142a4c19b02f31e17e24230ec34f9299bb1ftop level: reordered outputs to match the numbers on the front panel2012-02-29T14:13:10ZTomasz Włostowskitomasz.wlostowski@cern.chhttps://ohwr.org/project/fmc-delay-1ns-8cha/commit/1c5ffa8d9462cfaafe4e657ca4a6eed87114e274hdl/fd_channel_wb_slave: DCR.PG_ARM bit should be MONOSTABLE2012-02-29T14:13:09ZTomasz Włostowskitomasz.wlostowski@cern.chhttps://ohwr.org/project/fmc-delay-1ns-8cha/commit/feae54fb60a15bd0306f55043d05db6dc129fa75hdl: fd_delay_channel_driver.vhd: fixed RCR.CONT bit detection (now the core ...2012-02-29T14:13:09ZTomasz Włostowskitomasz.wlostowski@cern.chhdl: fd_delay_channel_driver.vhd: fixed RCR.CONT bit detection (now the core can produce continuous waveforms)
https://ohwr.org/project/fmc-delay-1ns-8cha/commit/8f422f8f73561d17fd4a52217ea7f462c097726fsoftware: added pulse generator mode, temperature calibration program and PPS...2012-02-29T14:06:18ZTomasz Wlostowskitomasz.wlostowski@cern.chhttps://ohwr.org/project/fmc-delay-1ns-8cha/commit/828b9fabc677281698131b05ccff413cd0ea9366V4 PCB design uploaded (minor fixes wrs the V3)2012-02-28T13:03:16ZTomasz Włostowskitomasz.wlostowski@cern.chhttps://ohwr.org/project/fmc-delay-1ns-8cha/commit/8c745caf4748dfa048eb27ae8f5bfeceaf724e46syn/spec/non_wr: demo bitstream for V32012-02-27T17:31:40ZTomasz Włostowskitomasz.wlostowski@cern.chhttps://ohwr.org/project/fmc-delay-1ns-8cha/commit/f82c33d7641ace96507ca51a91d55da78413e51asoftware: C library/test program for V32012-02-27T17:30:19ZTomasz Wlostowskitomasz.wlostowski@cern.chhttps://ohwr.org/project/fmc-delay-1ns-8cha/commit/ef09fc06b37384b8f738645a630844e8207fad8fsoftware: added onewire master and DS18XXX driver2012-02-27T17:30:19ZTomasz Wlostowskitomasz.wlostowski@cern.chhttps://ohwr.org/project/fmc-delay-1ns-8cha/commit/d459367b30e2fc6905500760612c42da74e29515software: updated register definitions and header for V3 HW2012-02-27T17:30:19ZTomasz Wlostowskitomasz.wlostowski@cern.chhttps://ohwr.org/project/fmc-delay-1ns-8cha/commit/9cc135fb339b02355e2ae0c06359279cbf599fdcsyn/top: SPEC non-whiterabbit top level updated for V32012-02-26T22:35:22ZTomasz Włostowskitomasz.wlostowski@cern.chhttps://ohwr.org/project/fmc-delay-1ns-8cha/commit/6f48bd5588bd68b6bf964ff44065035a43d3b16fhdl: assignment size bug fixed2012-02-26T22:34:44ZTomasz Włostowskitomasz.wlostowski@cern.chhttps://ohwr.org/project/fmc-delay-1ns-8cha/commit/354391a939913bfd076a900c754239af2407c7ffplatform: uploaded platform-dependend code2012-02-26T22:06:36ZTomasz Włostowskitomasz.wlostowski@cern.chhttps://ohwr.org/project/fmc-delay-1ns-8cha/commit/9aef0922af4ae642a6f6d6fa1aabbbda53cb6b95hdl: missing signal fix2012-02-26T22:06:02ZTomasz Włostowskitomasz.wlostowski@cern.chhttps://ohwr.org/project/fmc-delay-1ns-8cha/commit/5c08b95ab6cdc4460ccd671b5062226544f603f5hdl: renamed timing components to avoid conflicts with wr-cores2012-02-26T22:05:49ZTomasz Włostowskitomasz.wlostowski@cern.chhttps://ohwr.org/project/fmc-delay-1ns-8cha/commit/f2a729ecd0080fa4903f11bc514aceb38fbbc1f5hdl: docs for wbgen2 registers2012-02-26T21:59:25ZTomasz Włostowskitomasz.wlostowski@cern.chhttps://ohwr.org/project/fmc-delay-1ns-8cha/commit/481fc5847e8471c597c46d268b55cbd66ef6358dhdl: testing release for V3 hardware2012-02-26T21:58:21ZTomasz Włostowskitomasz.wlostowski@cern.chhttps://ohwr.org/project/fmc-delay-1ns-8cha/commit/f4ad16acd393ca4647d26a71b5094f972d5be77eremoved fd_ts_normalizer (no longer used)2012-02-26T21:51:00ZTomasz Włostowskitomasz.wlostowski@cern.chhttps://ohwr.org/project/fmc-delay-1ns-8cha/commit/47b7c00025cc22de1dedc5f544dc1d0daf78fc52hdl: removed TDC rearm unit (no longer necessary), renamed WB register block2012-02-26T21:34:30ZTomasz Włostowskitomasz.wlostowski@cern.chhttps://ohwr.org/project/fmc-delay-1ns-8cha/commit/b75ccc85af596dd0095caea4fea2b20486ad9f14software/headers: adapted to V3 HW2011-12-20T16:08:29ZTomasz Włostowskitomasz.wlostowski@cern.chhttps://ohwr.org/project/fmc-delay-1ns-8cha/commit/8e1858c197efb508884252c76d64b98904ce2ab7hdl: added extra comments2011-12-20T09:26:27ZTomasz Włostowskitomasz.wlostowski@cern.chhttps://ohwr.org/project/fmc-delay-1ns-8cha/commit/9a1fa649e2b68bfd2266a5b5fba753f6aeb476bfhdl/syn: bitstream for SPEC WR Demo2011-11-10T17:43:27ZTomasz Wlostowskitomasz.wlostowski@cern.chhttps://ohwr.org/project/fmc-delay-1ns-8cha/commit/0702773d04976c333339f47801f5dd8247bd806chdl/syn: synthesis files for SPEC WR Demo2011-11-10T17:33:18ZTomasz Wlostowskitomasz.wlostowski@cern.chhttps://ohwr.org/project/fmc-delay-1ns-8cha/commit/5ffd4ff9c4d77148c4621cef50e810bde3d52ab3hdl/top: uploaded demo of FineDelay synced with WR via WR PTP Core2011-11-10T17:32:28ZTomasz Wlostowskitomasz.wlostowski@cern.chhttps://ohwr.org/project/fmc-delay-1ns-8cha/commit/361a312835d18aeb87e99cdebae736ae3a0c77f7fine_delay_core: added bitbanged I2C master and appropriate control registers2011-11-10T17:31:40ZTomasz Wlostowskitomasz.wlostowski@cern.ch