FMC DEL 1ns 4cha:90db6efe42cd7a73160368a8742229830cc6c305 commitshttps://ohwr.org/project/fmc-delay-1ns-8cha/commits/90db6efe42cd7a73160368a8742229830cc6c3052013-05-17T11:33:59Zhttps://ohwr.org/project/fmc-delay-1ns-8cha/commit/90db6efe42cd7a73160368a8742229830cc6c305Merge branch 'gmode'2013-05-17T11:33:59ZTomasz Włostowskitomasz.wlostowski@cern.ch
Conflicts:
hdl/rtl/fd_acam_timestamp_postprocessor.vhd
hdl/rtl/fd_acam_timestamper.vhd
hdl/testbench/svec_wr_top/main.sv
hdl/top/spec/wr/spec_top.vhd
hdl/top/svec/wr/svec_top.ucf
hdl/top/svec/wr/svec_top.vhdhttps://ohwr.org/project/fmc-delay-1ns-8cha/commit/a989eb86ae5b01dae35217911cc0af7f8ae2e107hdl/top/svec: slot order according to the front panel. SDB addresses in…2013-05-17T11:31:05ZTomasz Włostowskitomasz.wlostowski@cern.chhdl/top/svec: slot order according to the front panel. SDB addresses in ascending order. Fixed wrong WR Core SDB bridge address.
https://ohwr.org/project/fmc-delay-1ns-8cha/commit/5a62a8fb4da5e0c3c3b50679d84e21e4784c9252hdl/rtl/fine_delay_pkg: updated SDB version to 3, to allow the driver to…2013-05-17T11:29:25ZTomasz Włostowskitomasz.wlostowski@cern.chhdl/rtl/fine_delay_pkg: updated SDB version to 3, to allow the driver to distinguish between buggy (R-mode) and correct (G-mode) firmwares
https://ohwr.org/project/fmc-delay-1ns-8cha/commit/a5b65f8f153f3f5174b04505c8e3b9b444d47b75testbench/svec_wr_top: wip2013-05-17T11:28:15ZTomasz Włostowskitomasz.wlostowski@cern.chhttps://ohwr.org/project/fmc-delay-1ns-8cha/commit/36d423265413fc18e7cdeaa5059cb41ddaf451afhdl/top/spec: SPEC top level with VIC vector table preinitialization & synthe...2013-04-25T08:09:45ZTomasz Włostowskitomasz.wlostowski@cern.chhttps://ohwr.org/project/fmc-delay-1ns-8cha/commit/258f1b821140c07371bf47e0ca22c1041e54234ahdl/rtl/fine_delay_pkg: increased DDMTD calibration pulse length to improve d...2013-04-25T08:08:35ZTomasz Włostowskitomasz.wlostowski@cern.chhttps://ohwr.org/project/fmc-delay-1ns-8cha/commit/bd0f188439c1267235a76740b893ba8e3981255ehdl/top/svec: top level with SDB synthesis descriptor & VIC vector table prei...2013-04-16T16:18:28ZTomasz Włostowskitomasz.wlostowski@cern.chhttps://ohwr.org/project/fmc-delay-1ns-8cha/commit/dddcbe14556fa5338424b8379f43858716ec533bhdl/top/svec: removed VME core reset output2013-04-16T16:18:28ZTomasz Włostowskitomasz.wlostowski@cern.chhttps://ohwr.org/project/fmc-delay-1ns-8cha/commit/42bbc5eccd79004edb51ed9b040ae07a49981ae0syn/svec: added default release WR Core firmware to the manifest2013-04-16T16:18:28ZTomasz Włostowskitomasz.wlostowski@cern.chhttps://ohwr.org/project/fmc-delay-1ns-8cha/commit/9a910784816e03e66141c5e1bf1ecee36e876b8binclude/vme64x_bfm: some IRQ support (unfinished)2013-04-16T16:18:28ZTomasz Włostowskitomasz.wlostowski@cern.chhttps://ohwr.org/project/fmc-delay-1ns-8cha/commit/fee1b516e47ede9ffe7151748e9008999eb6e328top levels: updated for the newest WR core2013-04-16T16:18:28ZTomasz Włostowskitomasz.wlostowski@cern.chhttps://ohwr.org/project/fmc-delay-1ns-8cha/commit/7818810869c5a38ddc97fe6bdf81fb05e91e5881hdl/include/acam_model.svh: use 256 ns start period for G-mode testing2013-04-16T16:18:28ZTomasz Włostowskitomasz.wlostowski@cern.chhttps://ohwr.org/project/fmc-delay-1ns-8cha/commit/8f25c0df14b8c7cd43df5044a85781f84c45b8cehdl: use the TDC in G-mode (testing only)2013-04-16T16:18:28ZTomasz Włostowskitomasz.wlostowski@cern.chhttps://ohwr.org/project/fmc-delay-1ns-8cha/commit/f54972775f81c588907b8f32a8f9356da3e8b401svec pinswapping [wip]2013-04-16T16:18:28ZTomasz Włostowskitomasz.wlostowski@cern.chhttps://ohwr.org/project/fmc-delay-1ns-8cha/commit/79e647cb2c3c087f90bb54e4ad2abbe6d8236308doc: initial (incomplete version) of Hardware/HDL design notes2013-04-16T16:18:28ZTomasz Włostowskitomasz.wlostowski@cern.chhttps://ohwr.org/project/fmc-delay-1ns-8cha/commit/a7736c9bd9c9e164ca087e6e0ab066b92a9eb7e0hdl/include/ideal_timestamper.svh: fix default coarse counter range2013-02-23T18:28:28ZTomasz Włostowskitomasz.wlostowski@cern.chhttps://ohwr.org/project/fmc-delay-1ns-8cha/commit/36614c9964914ea4d782b15d6fabbc453f09585chdl/rtl/fd_main_wishbone_slave.wb: comments2013-02-23T18:27:42ZTomasz Włostowskitomasz.wlostowski@cern.chhttps://ohwr.org/project/fmc-delay-1ns-8cha/commit/5f349ccebe92e1098074e6a16e5c569fb13ad97bhdl/rtl/fd_delay_line_arbiter: 8 ns setup time before driving LEN low2013-02-23T18:26:54ZTomasz Włostowskitomasz.wlostowski@cern.chhttps://ohwr.org/project/fmc-delay-1ns-8cha/commit/26a053821b848592a94cfc26d1a58d1c69efacd2hdl/rtl/fd_acam_timestamper: reset FIFO after each sample2013-02-23T18:26:15ZTomasz Włostowskitomasz.wlostowski@cern.chhttps://ohwr.org/project/fmc-delay-1ns-8cha/commit/8c28309f9ea1ca819e302ae87f169a90b56d49f7top levels: updated for the newest WR core2013-02-23T18:25:27ZTomasz Włostowskitomasz.wlostowski@cern.chhttps://ohwr.org/project/fmc-delay-1ns-8cha/commit/9baa3508c2ef06365943916280d2a2d0c651a4cfMerge branch 'etherbone_demo'2013-02-21T15:36:01ZTomasz Włostowskitomasz.wlostowski@cern.ch
Conflicts:
hdl/rtl/fd_main_wishbone_slave.vhd
hdl/top/svec/wr/svec_top.vhd
hdl/top/svec/wr/xvme64x_core.vhdhttps://ohwr.org/project/fmc-delay-1ns-8cha/commit/985a70d9d63bc6d62f6792f664bcbc126a2c63eehdl/testbench/svec_wr_top: meaure the actual I/O delay2013-02-21T15:32:11ZTomasz Włostowskitomasz.wlostowski@cern.chhttps://ohwr.org/project/fmc-delay-1ns-8cha/commit/0e98042e9c6be3c5fcf73b7f08cda7dcd45fdbdehdl/include/random_pulse_gen.svh: burst generation2013-02-21T15:30:56ZTomasz Włostowskitomasz.wlostowski@cern.chhttps://ohwr.org/project/fmc-delay-1ns-8cha/commit/761e9b71e1cbbd67c9b1fa7305629b7cdaefa9a9tests: added random_pulse_gen2013-02-18T15:32:37ZTomasz Wlostowskitomasz.wlostowski@cern.chhttps://ohwr.org/project/fmc-delay-1ns-8cha/commit/dc8f79cb16eda3c48e0dd3d14d2f981387c85a19onewire.c: ugly fix for invalid 1st temperature readout2013-02-18T15:32:15ZTomasz Wlostowskitomasz.wlostowski@cern.chhttps://ohwr.org/project/fmc-delay-1ns-8cha/commit/f03fd9ba01f685b03796aed139cfd5c8ae119541fdelay_lib: same code for spec & svec2013-02-18T15:31:27ZTomasz Wlostowskitomasz.wlostowski@cern.chhttps://ohwr.org/project/fmc-delay-1ns-8cha/commit/7141e6e31ee81ac05eb78243f8e6e53c82373637acam: work in G mode instead of R mode (appears to fix 1.5 ns bug)2013-02-18T15:31:01ZTomasz Wlostowskitomasz.wlostowski@cern.chhttps://ohwr.org/project/fmc-delay-1ns-8cha/commit/96775589e080bd093b999da621f477424acdc567doc: initial (incomplete version) of Hardware/HDL design notes2013-01-22T13:58:00ZTomasz Włostowskitomasz.wlostowski@cern.chhttps://ohwr.org/project/fmc-delay-1ns-8cha/commit/043329c69d407b89ca9027d6e833704c4cdfb354svec pinswapping [wip]2013-01-22T13:57:33ZTomasz Włostowskitomasz.wlostowski@cern.chhttps://ohwr.org/project/fmc-delay-1ns-8cha/commit/901e9473f8ceb677606be492b9b8b7c3ac7a4d16doc: initial (incomplete version) of Hardware/HDL design notes2013-01-22T13:56:34ZTomasz Włostowskitomasz.wlostowski@cern.chhttps://ohwr.org/project/fmc-delay-1ns-8cha/commit/ef47a7bd906b3e8bc517475d6d5fcb2f98cb93fchdl/top/svec: migrate to latest version of VME64x core2012-12-14T10:36:08ZTomasz Włostowskitomasz.wlostowski@cern.chhttps://ohwr.org/project/fmc-delay-1ns-8cha/commit/52aa9a88b1634965ad785f6de013817578800779hdl/top/svec: remove useless CLOCK_DEDICATED_ROUTE constraint2012-12-14T10:36:08ZTomasz Włostowskitomasz.wlostowski@cern.chhttps://ohwr.org/project/fmc-delay-1ns-8cha/commit/37e76fae34529fa6377f7d110baad926bc200bechdl/top/svec: added power-up reset2012-12-14T10:36:08ZTomasz Włostowskitomasz.wlostowski@cern.chhttps://ohwr.org/project/fmc-delay-1ns-8cha/commit/74311c60805de4adceb2d7c45ddde64dde12ba5bhdl/rtl/fine_delay_core.vhd: direct (non-Wishbone) timestamp/trigger I/O2012-12-14T10:36:08ZTomasz Włostowskitomasz.wlostowski@cern.chhttps://ohwr.org/project/fmc-delay-1ns-8cha/commit/82d882ec33322c5418771b067eca184f244f3a7bhdl/rtl/fd_csync_generator.vhd: don't fire IRQ on DMTD lock state change2012-12-14T10:36:08ZTomasz Włostowskitomasz.wlostowski@cern.chhttps://ohwr.org/project/fmc-delay-1ns-8cha/commit/1c399c9129b3f2c433c871bc7ce34584495c6356hdl/rtl/fd_main_wishbone_slave.vhd: I2C outputs should be set to ones upon reset2012-12-14T10:36:08ZTomasz Włostowskitomasz.wlostowski@cern.chhttps://ohwr.org/project/fmc-delay-1ns-8cha/commit/7f430c0e50946a29ea4264ce2d51080e3d52cae2hdl/rtl/fd_main_wishbone_slave: fix TS buffer interrupt polarity2012-12-14T10:36:08ZTomasz Włostowskitomasz.wlostowski@cern.chhttps://ohwr.org/project/fmc-delay-1ns-8cha/commit/60df718d79122a4292b91c7a7496b236412b1b6chdl/syn: updated ISE projects for SVEC and SPEC2012-12-14T10:36:08ZTomasz Włostowskitomasz.wlostowski@cern.chhttps://ohwr.org/project/fmc-delay-1ns-8cha/commit/6deb1220daa9bb45f2273d3afddbcb93ac02d423hdl/top/svec: top level: new VME64x core, interrupts and Etherbone slave name...2012-12-14T10:36:07ZTomasz Włostowskitomasz.wlostowski@cern.chhttps://ohwr.org/project/fmc-delay-1ns-8cha/commit/4160f44e957ba883b41d5bbb5428e31733a70fefhdl/testbench: minor fixes2012-12-14T10:36:07ZTomasz Włostowskitomasz.wlostowski@cern.ch