hdl/syn/spec: updated the WR core builtin firmware to the 2.1 official release. Enabled synthesis with embedded firmware by default.

rtl: removed alignment of the DCR register to 8 (it was a bug hidden by wrong alignment handling bug in wbgen)

Conflicts:
	hdl/rtl/fd_acam_timestamp_postprocessor.vhd
	hdl/rtl/fd_acam_timestamper.vhd
	hdl/testbench/svec_wr_top/main.sv
	hdl/top/spec/wr/spec_top.vhd
	hdl/top/svec/wr/svec_top.ucf
	hdl/top/svec/wr/svec_top.vhd

hdl/top/svec: slot order according to the front panel. SDB addresses in ascending order. Fixed wrong WR Core SDB bridge address.

hdl/rtl/fine_delay_pkg: updated SDB version to 3, to allow the driver to distinguish between buggy (R-mode) and correct (G-mode) firmwares

Conflicts:
	hdl/rtl/fd_main_wishbone_slave.vhd
	hdl/top/svec/wr/svec_top.vhd
	hdl/top/svec/wr/xvme64x_core.vhd