FMC DEL 1ns 4cha:4b3978498150482817818b19dd1cf369aab5c07f commitshttps://ohwr.org/project/fmc-delay-1ns-8cha/commits/4b3978498150482817818b19dd1cf369aab5c07f2012-05-22T12:31:11Zhttps://ohwr.org/project/fmc-delay-1ns-8cha/commit/4b3978498150482817818b19dd1cf369aab5c07fsoftware/include: added TSBR_ADVANCE to main registers header2012-05-22T12:31:11ZTomasz Wlostowskitomasz.wlostowski@cern.chhttps://ohwr.org/project/fmc-delay-1ns-8cha/commit/a4189bc2d5d60fae19bc313d2506c6d969eb7cc3software/include: added debug registers & raw mode readout2012-05-18T18:09:09ZTomasz Wlostowskitomasz.wlostowski@cern.chhttps://ohwr.org/project/fmc-delay-1ns-8cha/commit/41ceeae5ac4c8433508c44f7092d369b0281fbffsoftware/lib/pp.conf: my current test config2012-05-18T18:08:41ZTomasz Wlostowskitomasz.wlostowski@cern.chhttps://ohwr.org/project/fmc-delay-1ns-8cha/commit/52ffc4638beec83ab707194ea525cc862f978047software/lib/fdelay_lib.c: raw readout mode, ATMCR value tweaking2012-05-18T18:08:23ZTomasz Wlostowskitomasz.wlostowski@cern.chhttps://ohwr.org/project/fmc-delay-1ns-8cha/commit/96c89af637b411ad56b65df63613092b7e474342software/lib/fdelay-gs.c: enable readout when all the cards have been…2012-05-18T18:07:51ZTomasz Wlostowskitomasz.wlostowski@cern.chsoftware/lib/fdelay-gs.c: enable readout when all the cards have been configured, output raw data too
https://ohwr.org/project/fmc-delay-1ns-8cha/commit/391c07d824a30288ad5058c8b4d3f0d4812f79c4software/lib/fdelay-gs: reconfigure the card on sync lost2012-05-16T16:46:28ZTomasz Wlostowskitomasz.wlostowski@cern.chhttps://ohwr.org/project/fmc-delay-1ns-8cha/commit/754b24731fdc13ca655893d1cfbe1df8433d50e7software/lib: normalize negative timestamps, SPI idle fix2012-05-16T13:28:51ZTomasz Wlostowskitomasz.wlostowski@cern.chhttps://ohwr.org/project/fmc-delay-1ns-8cha/commit/605c84cc40e97cbc7b84571216dca0ccb50bf971software: fdelay-gs ported to use test library2012-05-16T12:59:22ZTomasz Wlostowskitomasz.wlostowski@cern.chhttps://ohwr.org/project/fmc-delay-1ns-8cha/commit/7b9803b446bb6e27dfadec3857fa9215d548db1dlatest snapshot of the test program2012-05-16T09:25:34ZTomasz Wlostowskitomasz.wlostowski@cern.chhttps://ohwr.org/project/fmc-delay-1ns-8cha/commit/55c507d1c47a1abc81fa2ecc7d97126da846ed81merged software changes2012-05-04T21:03:25ZTomasz Włostowskitomasz.wlostowski@cern.chhttps://ohwr.org/project/fmc-delay-1ns-8cha/commit/e8824c5545a6dde5fd23270dcf21d5a6a0ed3951top/spec/wr: WR-enabled SPEC top-level2012-05-04T21:00:52ZTomasz Włostowskitomasz.wlostowski@cern.chhttps://ohwr.org/project/fmc-delay-1ns-8cha/commit/5a31f5c917f6c06e9b8255fc59f283a8da19d81bhdl/rtl/Manifest.py: use master branch of general-cores2012-05-04T20:59:45ZTomasz Włostowskitomasz.wlostowski@cern.chhttps://ohwr.org/project/fmc-delay-1ns-8cha/commit/2d9c8d9cd6dfc5d4b2b0c21235712f54fb0df356software/lib: WR mode added2012-05-02T17:08:24ZTomasz Wlostowskitomasz.wlostowski@cern.chhttps://ohwr.org/project/fmc-delay-1ns-8cha/commit/d8acc4aa81e0c0ae3f1c151bc6ecaf2b5836780ahdl/rtl/fd_ring_buffer: fixed ugly readout bug2012-05-01T15:29:12ZTomasz Włostowskitomasz.wlostowski@cern.chhttps://ohwr.org/project/fmc-delay-1ns-8cha/commit/8cd2e99597a3a59b06f453d1d7e2d020988b2a6dhdl/rtl/fd_csync_generator.vhd: clear DMTD status on reset2012-04-30T23:52:08ZTomasz Włostowskitomasz.wlostowski@cern.chhttps://ohwr.org/project/fmc-delay-1ns-8cha/commit/0f9d247dcbb6130b58a86b56bbcdef6e86fc0eefhdl/rtl/fine_delay_pkg: SDWB support, declared main component2012-04-30T23:51:38ZTomasz Włostowskitomasz.wlostowski@cern.chhttps://ohwr.org/project/fmc-delay-1ns-8cha/commit/7a812fac536963c340e6c678432678edb939b7efhdl/rtl/fine_delay_core.vhd: removed unused signals, wired the IRQ output line2012-04-30T23:51:11ZTomasz Włostowskitomasz.wlostowski@cern.chhttps://ohwr.org/project/fmc-delay-1ns-8cha/commit/1a685506c9180d68cc4e73c4ec8b95db535b03f8hdl/rtl/fd_delay_line_arbiter.vhd: drive delay_len_o inactive upon reset2012-04-30T23:50:19ZTomasz Włostowskitomasz.wlostowski@cern.chhttps://ohwr.org/project/fmc-delay-1ns-8cha/commit/c00e32c044152d9ecd6b9ceee0ccdf51941f5850hdl/rtl/fd_ring_buffer.vhd: fixed invalid DPRAM clock connection2012-04-30T23:49:49ZTomasz Włostowskitomasz.wlostowski@cern.chhttps://ohwr.org/project/fmc-delay-1ns-8cha/commit/a298a3e9be27f58aeda7d1d539e5eeb215e736fasoftware/lib: cleaned up fdelay_test.c program2012-04-27T09:52:32ZTomasz Wlostowskitomasz.wlostowski@cern.chhttps://ohwr.org/project/fmc-delay-1ns-8cha/commit/e1ed6c8d3147cd01b945e298be5699be5d12655esoftware: updated python demo to work with the newest rawrabbit driver2012-04-26T09:33:33ZTomasz Wlostowskitomasz.wlostowski@cern.chhttps://ohwr.org/project/fmc-delay-1ns-8cha/commit/aade9e8b6d440a05bfc62405787e5e9dd87497dfsoftware/python: updated demo GUI and library2012-04-26T09:06:48ZTomasz Wlostowskitomasz.wlostowski@cern.chhttps://ohwr.org/project/fmc-delay-1ns-8cha/commit/a9d3e9cc4cc1370e4e49918197b3cc7254a2e7d9software/lib: applied Matthieu's patches, fixing operation of multiple cards ...2012-04-26T09:06:27ZTomasz Wlostowskitomasz.wlostowski@cern.chhttps://ohwr.org/project/fmc-delay-1ns-8cha/commit/a072a95e479826e9592919e279a6d3a85610583dsoftware/lib: fix compilation error in fdelay_bus.c, disabled long tests by d...2012-04-12T15:29:46ZTomasz Wlostowskitomasz.wlostowski@cern.chhttps://ohwr.org/project/fmc-delay-1ns-8cha/commit/66491288c0730e619f3a5254d446129b4d79c135software/python: default to SPEC/PCIe address2012-04-12T15:29:12ZTomasz Wlostowskitomasz.wlostowski@cern.chhttps://ohwr.org/project/fmc-delay-1ns-8cha/commit/c8a55db93e86055665c65d22c4efb37ed5975fb2software/lib/fdelay_lib.c: added mezzanine presence check and VCXO tuning ran...2012-04-11T14:01:29ZTomasz Wlostowskitomasz.wlostowski@cern.chhttps://ohwr.org/project/fmc-delay-1ns-8cha/commit/ee3add818c4dec5c258dfba7682d73f761f5dc4bsoftware/include/fdelay_private.h: added CS_DAC SPI device select flag2012-04-11T14:01:29ZTomasz Wlostowskitomasz.wlostowski@cern.chhttps://ohwr.org/project/fmc-delay-1ns-8cha/commit/2da9c9db50c55e97f153f1f4cf9cb03e89640b58software/include: register definitions synced up with the latest HDL2012-04-11T14:01:29ZTomasz Wlostowskitomasz.wlostowski@cern.chhttps://ohwr.org/project/fmc-delay-1ns-8cha/commit/94dbf96b46f62edd88c2f152bd81b1a77bd1b7f0hdl/rtl: added root manifest2012-04-11T13:50:36ZTomasz Włostowskitomasz.wlostowski@cern.chhttps://ohwr.org/project/fmc-delay-1ns-8cha/commit/05f1e8ab13f58195fe4889fe737f664b2c5e9bb5hdl/top/spec/non_wr: added PRSNT_L FMC line2012-04-11T13:50:36ZTomasz Włostowskitomasz.wlostowski@cern.chhttps://ohwr.org/project/fmc-delay-1ns-8cha/commit/d638b41fadd099dfe1071e3c4d44cf11489a7826hdl/rtl/fine_delay_core.vhd: VCXO frequency measurement, FMC presence detecti...2012-04-11T13:50:36ZTomasz Włostowskitomasz.wlostowski@cern.chhdl/rtl/fine_delay_core.vhd: VCXO frequency measurement, FMC presence detection, new (generic-configured) WB Interconnect
https://ohwr.org/project/fmc-delay-1ns-8cha/commit/d317b7b930aee13e96668122d4ffc8e32812253ahdl/rtl/fd_acam_timestamper.vhd: disable STOP input during processing of the…2012-04-11T13:50:36ZTomasz Włostowskitomasz.wlostowski@cern.chhdl/rtl/fd_acam_timestamper.vhd: disable STOP input during processing of the pulse to avoid overloading the TDC FIFO when the stop input is driven with a very fast train of pulses
https://ohwr.org/project/fmc-delay-1ns-8cha/commit/d98201c2cd4db9d86ef3b26dd21d10edcb963a7ehdl/rtl: FMC present bit & extra debugging registers added to WB slaves2012-04-11T13:50:36ZTomasz Włostowskitomasz.wlostowski@cern.chhttps://ohwr.org/project/fmc-delay-1ns-8cha/commit/9121896bb4e2bc4a2a8330d23216fff94ce43651removed legacy hdl/sim/fine_delay_regs.v (now split into two separate WB slaves)2012-04-11T13:50:36ZTomasz Włostowskitomasz.wlostowski@cern.chhttps://ohwr.org/project/fmc-delay-1ns-8cha/commit/d7c3720939a6401582dd233acf8bbff4895ba00chdl/sim/timestamp.svh: nanoseconds to counters conversion bugfix2012-04-11T13:50:36ZTomasz Włostowskitomasz.wlostowski@cern.chhttps://ohwr.org/project/fmc-delay-1ns-8cha/commit/c1a51eb0834a5bcdf071306af82bc14273e48419hdl/sim: removed local copy of simdrv_defs header2012-04-11T13:50:36ZTomasz Włostowskitomasz.wlostowski@cern.chhttps://ohwr.org/project/fmc-delay-1ns-8cha/commit/bf7cdce8457b59c6c84cc47a7c7705a8975a37aahdl/sim/acam_model.sv: increased timestamp queue size2012-04-11T13:50:36ZTomasz Włostowskitomasz.wlostowski@cern.chhttps://ohwr.org/project/fmc-delay-1ns-8cha/commit/5e5f2f1f271a7afd585378735b8473e7f7c51e9csoftware: added missing MCP23S17 reg definition2012-04-04T09:43:59ZTomasz Wlostowskitomasz.wlostowski@cern.chhttps://ohwr.org/project/fmc-delay-1ns-8cha/commit/dcea8ebe623ce8f7bb6b00c63eef5467eed2f81csoftware: extended test procedures, added delay line linearity measurement2012-04-04T09:43:22ZTomasz Wlostowskitomasz.wlostowski@cern.chhttps://ohwr.org/project/fmc-delay-1ns-8cha/commit/6aa82cf333e9f6c91aa3e693ff53a08a8ae8bc5esoftware: uploaded spec_common.c (SPEC initialization for all test programs)2012-04-03T15:50:42ZTomasz Wlostowskitomasz.wlostowski@cern.ch