FMC DEL 1ns 4cha:36d423265413fc18e7cdeaa5059cb41ddaf451af commitshttps://ohwr.org/project/fmc-delay-1ns-8cha/commits/36d423265413fc18e7cdeaa5059cb41ddaf451af2013-04-25T08:09:45Zhttps://ohwr.org/project/fmc-delay-1ns-8cha/commit/36d423265413fc18e7cdeaa5059cb41ddaf451afhdl/top/spec: SPEC top level with VIC vector table preinitialization & synthe...2013-04-25T08:09:45ZTomasz Włostowskitomasz.wlostowski@cern.chhttps://ohwr.org/project/fmc-delay-1ns-8cha/commit/258f1b821140c07371bf47e0ca22c1041e54234ahdl/rtl/fine_delay_pkg: increased DDMTD calibration pulse length to improve d...2013-04-25T08:08:35ZTomasz Włostowskitomasz.wlostowski@cern.chhttps://ohwr.org/project/fmc-delay-1ns-8cha/commit/bd0f188439c1267235a76740b893ba8e3981255ehdl/top/svec: top level with SDB synthesis descriptor & VIC vector table prei...2013-04-16T16:18:28ZTomasz Włostowskitomasz.wlostowski@cern.chhttps://ohwr.org/project/fmc-delay-1ns-8cha/commit/dddcbe14556fa5338424b8379f43858716ec533bhdl/top/svec: removed VME core reset output2013-04-16T16:18:28ZTomasz Włostowskitomasz.wlostowski@cern.chhttps://ohwr.org/project/fmc-delay-1ns-8cha/commit/42bbc5eccd79004edb51ed9b040ae07a49981ae0syn/svec: added default release WR Core firmware to the manifest2013-04-16T16:18:28ZTomasz Włostowskitomasz.wlostowski@cern.chhttps://ohwr.org/project/fmc-delay-1ns-8cha/commit/9a910784816e03e66141c5e1bf1ecee36e876b8binclude/vme64x_bfm: some IRQ support (unfinished)2013-04-16T16:18:28ZTomasz Włostowskitomasz.wlostowski@cern.chhttps://ohwr.org/project/fmc-delay-1ns-8cha/commit/fee1b516e47ede9ffe7151748e9008999eb6e328top levels: updated for the newest WR core2013-04-16T16:18:28ZTomasz Włostowskitomasz.wlostowski@cern.chhttps://ohwr.org/project/fmc-delay-1ns-8cha/commit/7818810869c5a38ddc97fe6bdf81fb05e91e5881hdl/include/acam_model.svh: use 256 ns start period for G-mode testing2013-04-16T16:18:28ZTomasz Włostowskitomasz.wlostowski@cern.chhttps://ohwr.org/project/fmc-delay-1ns-8cha/commit/8f25c0df14b8c7cd43df5044a85781f84c45b8cehdl: use the TDC in G-mode (testing only)2013-04-16T16:18:28ZTomasz Włostowskitomasz.wlostowski@cern.chhttps://ohwr.org/project/fmc-delay-1ns-8cha/commit/f54972775f81c588907b8f32a8f9356da3e8b401svec pinswapping [wip]2013-04-16T16:18:28ZTomasz Włostowskitomasz.wlostowski@cern.chhttps://ohwr.org/project/fmc-delay-1ns-8cha/commit/79e647cb2c3c087f90bb54e4ad2abbe6d8236308doc: initial (incomplete version) of Hardware/HDL design notes2013-04-16T16:18:28ZTomasz Włostowskitomasz.wlostowski@cern.chhttps://ohwr.org/project/fmc-delay-1ns-8cha/commit/761e9b71e1cbbd67c9b1fa7305629b7cdaefa9a9tests: added random_pulse_gen2013-02-18T15:32:37ZTomasz Wlostowskitomasz.wlostowski@cern.chhttps://ohwr.org/project/fmc-delay-1ns-8cha/commit/dc8f79cb16eda3c48e0dd3d14d2f981387c85a19onewire.c: ugly fix for invalid 1st temperature readout2013-02-18T15:32:15ZTomasz Wlostowskitomasz.wlostowski@cern.chhttps://ohwr.org/project/fmc-delay-1ns-8cha/commit/f03fd9ba01f685b03796aed139cfd5c8ae119541fdelay_lib: same code for spec & svec2013-02-18T15:31:27ZTomasz Wlostowskitomasz.wlostowski@cern.chhttps://ohwr.org/project/fmc-delay-1ns-8cha/commit/7141e6e31ee81ac05eb78243f8e6e53c82373637acam: work in G mode instead of R mode (appears to fix 1.5 ns bug)2013-02-18T15:31:01ZTomasz Wlostowskitomasz.wlostowski@cern.chhttps://ohwr.org/project/fmc-delay-1ns-8cha/commit/ef47a7bd906b3e8bc517475d6d5fcb2f98cb93fchdl/top/svec: migrate to latest version of VME64x core2012-12-14T10:36:08ZTomasz Włostowskitomasz.wlostowski@cern.chhttps://ohwr.org/project/fmc-delay-1ns-8cha/commit/52aa9a88b1634965ad785f6de013817578800779hdl/top/svec: remove useless CLOCK_DEDICATED_ROUTE constraint2012-12-14T10:36:08ZTomasz Włostowskitomasz.wlostowski@cern.chhttps://ohwr.org/project/fmc-delay-1ns-8cha/commit/37e76fae34529fa6377f7d110baad926bc200bechdl/top/svec: added power-up reset2012-12-14T10:36:08ZTomasz Włostowskitomasz.wlostowski@cern.chhttps://ohwr.org/project/fmc-delay-1ns-8cha/commit/74311c60805de4adceb2d7c45ddde64dde12ba5bhdl/rtl/fine_delay_core.vhd: direct (non-Wishbone) timestamp/trigger I/O2012-12-14T10:36:08ZTomasz Włostowskitomasz.wlostowski@cern.chhttps://ohwr.org/project/fmc-delay-1ns-8cha/commit/82d882ec33322c5418771b067eca184f244f3a7bhdl/rtl/fd_csync_generator.vhd: don't fire IRQ on DMTD lock state change2012-12-14T10:36:08ZTomasz Włostowskitomasz.wlostowski@cern.chhttps://ohwr.org/project/fmc-delay-1ns-8cha/commit/1c399c9129b3f2c433c871bc7ce34584495c6356hdl/rtl/fd_main_wishbone_slave.vhd: I2C outputs should be set to ones upon reset2012-12-14T10:36:08ZTomasz Włostowskitomasz.wlostowski@cern.chhttps://ohwr.org/project/fmc-delay-1ns-8cha/commit/7f430c0e50946a29ea4264ce2d51080e3d52cae2hdl/rtl/fd_main_wishbone_slave: fix TS buffer interrupt polarity2012-12-14T10:36:08ZTomasz Włostowskitomasz.wlostowski@cern.chhttps://ohwr.org/project/fmc-delay-1ns-8cha/commit/60df718d79122a4292b91c7a7496b236412b1b6chdl/syn: updated ISE projects for SVEC and SPEC2012-12-14T10:36:08ZTomasz Włostowskitomasz.wlostowski@cern.chhttps://ohwr.org/project/fmc-delay-1ns-8cha/commit/6deb1220daa9bb45f2273d3afddbcb93ac02d423hdl/top/svec: top level: new VME64x core, interrupts and Etherbone slave name...2012-12-14T10:36:07ZTomasz Włostowskitomasz.wlostowski@cern.chhttps://ohwr.org/project/fmc-delay-1ns-8cha/commit/4160f44e957ba883b41d5bbb5428e31733a70fefhdl/testbench: minor fixes2012-12-14T10:36:07ZTomasz Włostowskitomasz.wlostowski@cern.chhttps://ohwr.org/project/fmc-delay-1ns-8cha/commit/36e07dc3fc522188cc352b37d22eebd11fc67a4ehdl/rtl/fine_delay_pkg.vhd: remove spaces from the core name in the SDB descr...2012-12-14T10:36:07ZTomasz Włostowskitomasz.wlostowski@cern.chhttps://ohwr.org/project/fmc-delay-1ns-8cha/commit/a686b99847e0bf649cebed384ac1dab7aaf4666fhdl/ip_cores: removed vme64x-core files from the repo2012-12-14T10:36:07ZTomasz Włostowskitomasz.wlostowski@cern.chhttps://ohwr.org/project/fmc-delay-1ns-8cha/commit/ec77872b2c30f8f93a7ebec1f7a166e48b1d58a5hdl/top/spec: updated Etherbone entity name2012-12-14T10:36:07ZTomasz Włostowskitomasz.wlostowski@cern.chhttps://ohwr.org/project/fmc-delay-1ns-8cha/commit/3639a71dc899e663c4b3197c4059e920f2c2ce27hdl/syn/spec: added WRC binary firmware to build2012-12-14T10:36:07ZTomasz Włostowskitomasz.wlostowski@cern.chhttps://ohwr.org/project/fmc-delay-1ns-8cha/commit/fe7dccd00878c00f4c4be323333d615352135c9fhdl/syn/spec: top level with VIC interrupt controller, removed spaces from SD...2012-12-14T10:36:07ZTomasz Włostowskitomasz.wlostowski@cern.chhttps://ohwr.org/project/fmc-delay-1ns-8cha/commit/fc2032e6c7f4162afb67f040ea83189f36aabaf2fdelay_lib.h: fix timestamp structure layout to keep python compatibility2012-09-25T07:59:38ZTomasz Włostowskitomasz.wlostowski@cern.chhttps://ohwr.org/project/fmc-delay-1ns-8cha/commit/3467c1fbcbe79220fc0b919745b1bb9997409ff8software: demo program using Etherbone2012-09-21T16:03:59ZTomasz Włostowskitomasz.wlostowski@cern.chhttps://ohwr.org/project/fmc-delay-1ns-8cha/commit/87a22048937ae51efc33bf4e0f3338d6f32b9d45hdl/top/spec: added power-on-reset generator that works both in PCIe and stan...2012-09-21T08:49:40ZTomasz Włostowskitomasz.wlostowski@cern.chhttps://ohwr.org/project/fmc-delay-1ns-8cha/commit/2ad30ecebe24ab87fd663b124a2b8e8b41877090hdl/top/svec: SDB block at 0 offset2012-09-21T08:49:08ZTomasz Włostowskitomasz.wlostowski@cern.chhttps://ohwr.org/project/fmc-delay-1ns-8cha/commit/cde561fc48bce0a5307f1aa7998bad265e0b90d2hdl/top: removed minibone2012-09-21T08:47:35ZTomasz Włostowskitomasz.wlostowski@cern.chhttps://ohwr.org/project/fmc-delay-1ns-8cha/commit/7e43140eb43fcd5253c4092b76ded20504c494d7hdl/top: new top level with Etherbone and SDB support2012-09-21T08:47:21ZTomasz Włostowskitomasz.wlostowski@cern.chhttps://ohwr.org/project/fmc-delay-1ns-8cha/commit/3e8e0ae44908cf3dcc21a92b6a58c73b2b89a0cetestbench: uploaded system-level testbenench for SVEC2012-08-13T15:28:55ZTomasz Włostowskitomasz.wlostowski@cern.chhttps://ohwr.org/project/fmc-delay-1ns-8cha/commit/a21d0b54592760a77e12a02d8dd29b6466533c87[top/syn]/svec/wr: SVEC top level with new VME Core, working WR Core and Ethe...2012-08-13T15:28:07ZTomasz Włostowskitomasz.wlostowski@cern.chhttps://ohwr.org/project/fmc-delay-1ns-8cha/commit/57dd271511fe314c78f3f41d13e7a718ce72fca8rtl/fine_delay_core.vhd: increase SPI clock speed for system-level simulation2012-08-13T15:23:26ZTomasz Włostowskitomasz.wlostowski@cern.chhttps://ohwr.org/project/fmc-delay-1ns-8cha/commit/78b34df6592041daed8262b8255aab16491942d3rtl/fine_delay_pkg.vhd: added SDB descriptor2012-08-13T15:23:04ZTomasz Włostowskitomasz.wlostowski@cern.ch