Commits · 36d423265413fc18e7cdeaa5059cb41ddaf451af · Projects / FMC DEL 1ns 4cha · Open Hardware Repository

25 Apr, 2013 2 commits
- hdl/top/spec: SPEC top level with VIC vector table preinitialization & synthesis descriptor · 36d42326
  Tomasz Wlostowski authored Apr 25, 2013
  
  36d42326
- hdl/rtl/fine_delay_pkg: increased DDMTD calibration pulse length to improve deglitcher operation · 258f1b82
  Tomasz Wlostowski authored Apr 25, 2013
  
  258f1b82
16 Apr, 2013 9 commits
- hdl/top/svec: top level with SDB synthesis descriptor & VIC vector table preinitialization · bd0f1884
  Tomasz Wlostowski authored Apr 16, 2013
  
  bd0f1884
- hdl/top/svec: removed VME core reset output · dddcbe14
  Tomasz Wlostowski authored Apr 16, 2013
  
  dddcbe14
- syn/svec: added default release WR Core firmware to the manifest · 42bbc5ec
  Tomasz Wlostowski authored Apr 16, 2013
  
  42bbc5ec
- include/vme64x_bfm: some IRQ support (unfinished) · 9a910784
  Tomasz Wlostowski authored Apr 16, 2013
  
  9a910784
- top levels: updated for the newest WR core · fee1b516
  Tomasz Wlostowski authored Feb 23, 2013
  
  fee1b516
- hdl/include/acam_model.svh: use 256 ns start period for G-mode testing · 78188108
  Tomasz Wlostowski authored Feb 21, 2013
  
  78188108
- hdl: use the TDC in G-mode (testing only) · 8f25c0df
  Tomasz Wlostowski authored Feb 21, 2013
  
  8f25c0df
- svec pinswapping [wip] · f5497277
  Tomasz Wlostowski authored Jan 22, 2013
  
  f5497277
- doc: initial (incomplete version) of Hardware/HDL design notes · 79e647cb
  Tomasz Wlostowski authored Jan 22, 2013
  
  79e647cb
18 Feb, 2013 4 commits
- tests: added random_pulse_gen · 761e9b71
  Tomasz Wlostowski authored Feb 18, 2013
  
  761e9b71
- onewire.c: ugly fix for invalid 1st temperature readout · dc8f79cb
  Tomasz Wlostowski authored Feb 18, 2013
  
  dc8f79cb
- fdelay_lib: same code for spec & svec · f03fd9ba
  Tomasz Wlostowski authored Feb 18, 2013
  
  f03fd9ba
- acam: work in G mode instead of R mode (appears to fix 1.5 ns bug) · 7141e6e3
  Tomasz Wlostowski authored Feb 18, 2013
  
  7141e6e3
14 Dec, 2012 15 commits
- hdl/top/svec: migrate to latest version of VME64x core · ef47a7bd
  Tomasz Wlostowski authored Dec 14, 2012
  
  ef47a7bd
- hdl/top/svec: remove useless CLOCK_DEDICATED_ROUTE constraint · 52aa9a88
  Tomasz Wlostowski authored Dec 14, 2012
  
  52aa9a88
- hdl/top/svec: added power-up reset · 37e76fae
  Tomasz Wlostowski authored Dec 14, 2012
  
  37e76fae
- hdl/rtl/fine_delay_core.vhd: direct (non-Wishbone) timestamp/trigger I/O · 74311c60
  Tomasz Wlostowski authored Dec 14, 2012
  
  74311c60
- hdl/rtl/fd_csync_generator.vhd: don't fire IRQ on DMTD lock state change · 82d882ec
  Tomasz Wlostowski authored Dec 14, 2012
  
  82d882ec
- hdl/rtl/fd_main_wishbone_slave.vhd: I2C outputs should be set to ones upon reset · 1c399c91
  Tomasz Wlostowski authored Dec 14, 2012
  
  1c399c91
- hdl/rtl/fd_main_wishbone_slave: fix TS buffer interrupt polarity · 7f430c0e
  Tomasz Wlostowski authored Oct 24, 2012
  
  7f430c0e
- hdl/syn: updated ISE projects for SVEC and SPEC · 60df718d
  Tomasz Wlostowski authored Oct 24, 2012
  
  60df718d
- hdl/top/svec: top level: new VME64x core, interrupts and Etherbone slave name fix · 6deb1220
  Tomasz Wlostowski authored Oct 24, 2012
  
  6deb1220
- hdl/testbench: minor fixes · 4160f44e
  Tomasz Wlostowski authored Oct 24, 2012
  
  4160f44e
- hdl/rtl/fine_delay_pkg.vhd: remove spaces from the core name in the SDB descriptor · 36e07dc3
  Tomasz Wlostowski authored Oct 24, 2012
  
  36e07dc3
- hdl/ip_cores: removed vme64x-core files from the repo · a686b998
  Tomasz Wlostowski authored Oct 24, 2012
  
  a686b998
- hdl/top/spec: updated Etherbone entity name · ec77872b
  Tomasz Wlostowski authored Oct 24, 2012
  
  ec77872b
- hdl/syn/spec: added WRC binary firmware to build · 3639a71d
  Tomasz Wlostowski authored Oct 17, 2012
  
  3639a71d
- hdl/syn/spec: top level with VIC interrupt controller, removed spaces from SDB name · fe7dccd0
  Tomasz Wlostowski authored Oct 17, 2012
  
  fe7dccd0
25 Sep, 2012 1 commit
- fdelay_lib.h: fix timestamp structure layout to keep python compatibility · fc2032e6
  Tomasz Wlostowski authored Sep 25, 2012
  
  fc2032e6
21 Sep, 2012 5 commits
- software: demo program using Etherbone · 3467c1fb
  Tomasz Wlostowski authored Sep 21, 2012
  
  3467c1fb
- hdl/top/spec: added power-on-reset generator that works both in PCIe and standalone mode · 87a22048
  Tomasz Wlostowski authored Sep 21, 2012
  
  87a22048
- hdl/top/svec: SDB block at 0 offset · 2ad30ece
  Tomasz Wlostowski authored Sep 21, 2012
  
  2ad30ece
- hdl/top: removed minibone · cde561fc
  Tomasz Wlostowski authored Sep 21, 2012
  
  cde561fc
- hdl/top: new top level with Etherbone and SDB support · 7e43140e
  Tomasz Wlostowski authored Sep 21, 2012
  
  7e43140e
13 Aug, 2012 4 commits
- testbench: uploaded system-level testbenench for SVEC · 3e8e0ae4
  Tomasz Wlostowski authored Aug 13, 2012
  
  3e8e0ae4
- [top/syn]/svec/wr: SVEC top level with new VME Core, working WR Core and Etherbone · a21d0b54
  Tomasz Wlostowski authored Aug 13, 2012
  
  a21d0b54
- rtl/fine_delay_core.vhd: increase SPI clock speed for system-level simulation · 57dd2715
  Tomasz Wlostowski authored Aug 13, 2012
  
  57dd2715
- rtl/fine_delay_pkg.vhd: added SDB descriptor · 78b34df6
  Tomasz Wlostowski authored Aug 13, 2012
  
  78b34df6