Commit ff27f1c2 authored by Dimitris Lampridis's avatar Dimitris Lampridis

Merge branch '13-make-3-0-9-release' into 'master'

Resolve "make 3.0.9 release"

Closes #13

See merge request be-cem-edl/fec/hardware-modules/fmc-delay-1ns-8cha!10
parents 56933687 282bc2d8
......@@ -6,6 +6,27 @@
Changelog
=========
3.0.9 - 2022-12-14
==================
Added
-----
- hdl: bitstreams now published under https://be-cem-edl.web.cern.ch/
- doc: now published under https://be-cem-edl.web.cern.ch/
- sw: support for newer Linux kernels
Changed
-------
- bld: many improvements to CI
- bld: build system cleanup
- hdl: update to latest releases of all dependencies
- hdl: top-level VHDL module names are now more consistent and descriptive
Fixed
-----
- hdl: WR ready bit in TCR register now always shows the validity of WR time
- sw: output pulse duty cycle now properly set to 50% by default
3.0.8 - 2021-03-17
==================
......
Subproject commit affb718e16fd0336f262441bf9f7ae7e570d55c6
Subproject commit 3b1aaab0a94a8dee1edaec3cbfb141481b876bb4
......@@ -13,15 +13,15 @@ if locals().get('fetchto', None) is None:
syn_device = "xc6slx45t"
syn_grade = "-3"
syn_package = "fgg484"
syn_project = "spec_fine_delay_top.xise"
syn_project = "spec_fine_delay.xise"
syn_tool = "ise"
syn_top = "spec_fine_delay_top"
syn_top = "spec_fine_delay"
spec_base_ucf = ['wr', 'onewire', 'spi']
board = "spec"
ctrls = ["bank3_64b_32b" ]
files = [ "buildinfo_pkg.vhd", "sourceid_spec_fine_delay_top_pkg.vhd" ]
files = [ "buildinfo_pkg.vhd", "sourceid_spec_fine_delay_pkg.vhd" ]
modules = {
"local" : [ "../../top/spec" ]
......@@ -37,7 +37,7 @@ try:
# Assume this module is in fact a git submodule of a main project that
# is in the same directory as general-cores...
exec(open(fetchto + "/general-cores/tools/gen_sourceid.py").read(),
None, {'project': 'spec_fine_delay_top'})
None, {'project': 'spec_fine_delay'})
except Exception as e:
print("Error: cannot generate source id file")
raise
......
......@@ -9,7 +9,7 @@ action = "synthesis"
syn_device = "xc6slx150t"
syn_grade = "-3"
syn_package = "fgg900"
syn_top = "svec_top"
syn_top = "svec_fine_delay"
syn_project = "svec_fine_delay.xise"
syn_tool = "ise"
......@@ -25,7 +25,7 @@ fetchto = os.path.abspath(fetchto)
files = [
"buildinfo_pkg.vhd",
"sourceid_svec_fine_delay_top_pkg.vhd",
"sourceid_svec_fine_delay_pkg.vhd",
"svec_fine_delay_top.ucf",
"svec-fd0.ucf",
"svec-fd1.ucf"
......@@ -47,7 +47,7 @@ try:
# Assume this module is in fact a git submodule of a main project that
# is in the same directory as general-cores...
exec(open(fetchto + "/general-cores/tools/gen_sourceid.py").read(),
None, {'project': 'svec_fine_delay_top'})
None, {'project': 'svec_fine_delay'})
except Exception as e:
print("Error: cannot generate source id file")
raise
......
......@@ -28,8 +28,8 @@ xilinx::project set "Pack I/O Registers/Latches into IOBs" "For Inputs and Outpu
xilinx::project set "Register Balancing" "Yes"
xilinx::project set "Register Duplication Map" "On"
#xilinx::project set "Placer Extra Effort Map" "Normal"
#xilinx::project set "Extra Effort (Highest PAR level only)" "Normal"
xilinx::project set "Placer Extra Effort Map" "Normal"
xilinx::project set "Extra Effort (Highest PAR level only)" "Normal"
#xilinx::project set "Keep Hierarchy" "Yes"
......
......@@ -8,7 +8,7 @@
-- https://ohwr.org/projects/fmc-delay-1ns-8cha
--------------------------------------------------------------------------------
--
-- unit name: spec_fine_delay_top
-- unit name: spec_fine_delay
--
-- description: Top entity for Fine Delay reference design.
--
......@@ -38,13 +38,13 @@ use work.wishbone_pkg.all;
use work.wr_board_pkg.all;
use work.wr_fabric_pkg.all;
use work.fine_delay_pkg.all;
use work.sourceid_spec_fine_delay_top_pkg;
use work.sourceid_spec_fine_delay_pkg;
library unisim;
use unisim.vcomponents.all;
entity spec_fine_delay_top is
entity spec_fine_delay is
generic (
g_WRPC_INITF : string := "../../ip_cores/wr-cores/bin/wrpc/wrc_phy8.bram";
-- Simulation-mode enable parameter. Set by default (synthesis) to 0, and
......@@ -183,9 +183,9 @@ entity spec_fine_delay_top is
fmc0_scl_b : inout std_logic;
fmc0_sda_b : inout std_logic);
end entity spec_fine_delay_top;
end entity spec_fine_delay;
architecture arch of spec_fine_delay_top is
architecture arch of spec_fine_delay is
component IBUFDS is
......@@ -310,9 +310,9 @@ begin -- architecture arch
generic map (
g_VENDOR_ID => x"0000_10DC",
g_DEVICE_ID => x"574f_0001", -- SPEC + 1xFine Delay
g_VERSION => x"0300_0008",
g_VERSION => x"0300_0009",
g_CAPABILITIES => x"0000_0000",
g_COMMIT_ID => sourceid_spec_fine_delay_top_pkg.sourceid)
g_COMMIT_ID => sourceid_spec_fine_delay_pkg.sourceid)
port map (
clk_i => clk_sys_62m5,
rst_n_i => rst_sys_62m5_n,
......
......@@ -8,7 +8,7 @@
-- https://ohwr.org/projects/fmc-delay-1ns-8cha
--------------------------------------------------------------------------------
--
-- unit name: spec_top
-- unit name: svec_fine_delay
--
-- description: Top entity for Fine Delay reference design.
--
......@@ -43,12 +43,12 @@ use work.wishbone_pkg.all;
use work.wr_board_pkg.all;
use work.wr_fabric_pkg.all;
use work.fine_delay_pkg.all;
use work.sourceid_svec_fine_delay_top_pkg;
use work.sourceid_svec_fine_delay_pkg;
library unisim;
use unisim.vcomponents.all;
entity svec_top is
entity svec_fine_delay is
generic (
g_WRPC_INITF : string := "../../ip_cores/wr-cores/bin/wrpc/wrc_phy8.bram";
-- Simulation-mode enable parameter. Set by default (synthesis) to 0, and
......@@ -274,9 +274,9 @@ entity svec_top is
fmc1_scl_b : inout std_logic;
fmc1_sda_b : inout std_logic
);
end entity svec_top;
end entity svec_fine_delay;
architecture arch of svec_top is
architecture arch of svec_fine_delay is
component fd_ddr_pll
port (
......@@ -418,9 +418,9 @@ begin -- architecture arch
generic map (
g_VENDOR_ID => x"0000_10DC",
g_DEVICE_ID => x"574f_0002", -- SVEC + 2xFineDelay
g_VERSION => x"0300_0008",
g_VERSION => x"0300_0009",
g_CAPABILITIES => x"0000_0000",
g_COMMIT_ID => sourceid_svec_fine_delay_top_pkg.sourceid)
g_COMMIT_ID => sourceid_svec_fine_delay_pkg.sourceid)
port map (
clk_i => clk_sys_62m5,
rst_n_i => rst_sys_62m5_n,
......
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