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FMC DEL 1ns 4cha
Commit f911e540 authored by Tomasz Wlostowski's avatar Tomasz Wlostowski
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Merge branch 'master' of ohwr.org:fmc-projects/fmc-delay-1ns-8cha

parents 27a6774b ec8b2e68
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Showing with 318 additions and 115 deletions
hdl/rtl/fd_acam_timestamp_postprocessor.vhd
View file @ f911e540
......@@ -6,7 +6,7 @@
-- Author : Tomasz Wlostowski
-- Company : CERN
-- Created : 2011-08-29
-- Last update: 2012-02-16
-- Last update: 2012-05-18
-- Platform : FPGA-generic
-- Standard : VHDL'93
-------------------------------------------------------------------------------
......@@ -60,10 +60,12 @@ entity fd_acam_timestamp_postprocessor is
raw_valid_i : in std_logic;
raw_utc_i : in std_logic_vector(c_TIMESTAMP_UTC_BITS-1 downto 0);
raw_utc_shifted_i : in std_logic_vector(c_TIMESTAMP_UTC_BITS-1 downto 0);
-- "start number" (value of coarse counter, counting at every start pulse of the
-- TDC, i.e. 125 MHz / 16 = 7.8215 MHz)
raw_coarse_i : in std_logic_vector(c_TIMESTAMP_COARSE_BITS-4-1 downto 0);
raw_coarse_shifted_i : in std_logic_vector(c_TIMESTAMP_COARSE_BITS-4-1 downto 0);
-- raw fractional timestamp generated by ACAM
raw_frac_i : in std_logic_vector(22 downto 0);
......@@ -81,10 +83,11 @@ entity fd_acam_timestamp_postprocessor is
-- Post-processed timestamp. WARNING! DE-NORMALIZED!
---------------------------------------------------------------------------
tag_valid_o : out std_logic;
tag_utc_o : out std_logic_vector(c_TIMESTAMP_UTC_BITS-1 downto 0);
tag_coarse_o : out std_logic_vector(c_TIMESTAMP_COARSE_BITS-1 downto 0);
tag_frac_o : out std_logic_vector(g_frac_bits-1 downto 0);
tag_valid_o : out std_logic;
tag_utc_o : out std_logic_vector(c_TIMESTAMP_UTC_BITS-1 downto 0);
tag_coarse_o : out std_logic_vector(c_TIMESTAMP_COARSE_BITS-1 downto 0);
tag_frac_o : out std_logic_vector(g_frac_bits-1 downto 0);
tag_dbg_raw_o : out std_logic_vector(31 downto 0);
-- Wishbone regs
regs_i : in t_fd_main_out_registers
......@@ -143,7 +146,7 @@ begin -- behavioral
-- situations, ACAM internally adds a constant offset (StartOffset), which we have
-- to subtract here.
pp_pipe(0) <= raw_valid_i;
post_frac_start_adj <= signed(raw_frac_i) - signed(regs_i.asor_offset_o);
......@@ -181,9 +184,9 @@ begin -- behavioral
-- the synthesis tool to spread the multiplier across several stages,
-- improving the timing of the design.
pp_pipe(3) <= pp_pipe(2);
pp_pipe(3) <= pp_pipe(2);
post_frac_multiplied_d0 <= post_frac_multiplied;
-- Pipeline stage 4:
-- Split the rescaled fractional part into the (mod 4096) tag_frac_o and add
-- the rest to the coarse part, along with the start-to-timescale offset.
......@@ -198,19 +201,37 @@ begin -- behavioral
--
-- This value is added here to align the result to our timescale
-- without messing around with the PLL.
pp_pipe(4) <= pp_pipe(3);
tag_utc_o <= std_logic_vector(post_tag_utc);
tag_coarse_o <= std_logic_vector(
signed(post_tag_coarse) -- index of start pulse (mod 16 = 0)
+ signed(acam_subcycle_offset_i) -- start-to-timescale offset
+ signed(post_frac_multiplied_d0(post_frac_multiplied_d0'left downto c_SCALER_SHIFT + g_frac_bits)));
-- extra coarse counts from ACAM's frac part after rescaling
if(regs_i.tsbcr_raw_o = '0') then
tag_utc_o <= std_logic_vector(post_tag_utc);
tag_coarse_o <= std_logic_vector(
signed(post_tag_coarse) -- index of start pulse (mod 16 = 0)
+ signed(acam_subcycle_offset_i) -- start-to-timescale offset
+ signed(post_frac_multiplied_d0(post_frac_multiplied_d0'left downto c_SCALER_SHIFT + g_frac_bits)));
-- extra coarse counts from ACAM's frac part after rescaling
tag_frac_o <= std_logic_vector(post_frac_multiplied_d0(c_SCALER_SHIFT + g_frac_bits-1 downto c_SCALER_SHIFT));
tag_valid_o <= pp_pipe(4);
elsif(raw_valid_i = '1') then
tag_utc_o <= raw_utc_i;
tag_coarse_o <= raw_coarse_i & raw_start_offset_i;
tag_frac_o <= raw_frac_i(11 downto 0);
tag_dbg_raw_o(10 downto 0) <= raw_frac_i(22 downto 12);
tag_dbg_raw_o(15 downto 11) <= acam_subcycle_offset_i;
tag_dbg_raw_o(23 downto 16) <= raw_coarse_shifted_i(7 downto 0);
tag_dbg_raw_o(31 downto 24) <= raw_utc_shifted_i(7 downto 0);
tag_valid_o <= '1';
else
tag_valid_o <= '0';
end if;
tag_frac_o <= std_logic_vector(post_frac_multiplied_d0(c_SCALER_SHIFT + g_frac_bits-1 downto c_SCALER_SHIFT));
tag_valid_o <= pp_pipe(4);
end if;
end if;
......
hdl/rtl/fd_acam_timestamper.vhd
View file @ f911e540
This diff is collapsed.
hdl/rtl/fd_main_wbgen2_pkg.vhd
View file @ f911e540
......@@ -3,7 +3,7 @@
---------------------------------------------------------------------------------------
-- File : fd_main_wbgen2_pkg.vhd
-- Author : auto-generated by wbgen2 from fd_main_wishbone_slave.wb
-- Created : Wed Apr 11 11:05:21 2012
-- Created : Mon May 21 20:09:49 2012
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE fd_main_wishbone_slave.wb
......@@ -55,6 +55,7 @@ package fd_main_wbgen2_pkg is
i2cr_scl_in_i : std_logic;
i2cr_sda_in_i : std_logic;
tder1_vcxo_freq_i : std_logic_vector(31 downto 0);
tsbr_debug_i : std_logic_vector(31 downto 0);
end record;
constant c_fd_main_in_registers_init_value: t_fd_main_in_registers := (
......@@ -91,7 +92,8 @@ package fd_main_wbgen2_pkg is
tsbr_fid_seqid_i => (others => '0'),
i2cr_scl_in_i => '0',
i2cr_sda_in_i => '0',
tder1_vcxo_freq_i => (others => '0')
tder1_vcxo_freq_i => (others => '0'),
tsbr_debug_i => (others => '0')
);
-- Output registers (WB slave -> user design)
......@@ -147,11 +149,13 @@ package fd_main_wbgen2_pkg is
tsbcr_enable_o : std_logic;
tsbcr_purge_o : std_logic;
tsbcr_rst_seq_o : std_logic;
tsbcr_raw_o : std_logic;
tsbir_timeout_o : std_logic_vector(9 downto 0);
tsbir_threshold_o : std_logic_vector(11 downto 0);
i2cr_scl_out_o : std_logic;
i2cr_sda_out_o : std_logic;
tder2_pelt_drive_o : std_logic_vector(31 downto 0);
tsbr_advance_adv_o : std_logic;
end record;
constant c_fd_main_out_registers_init_value: t_fd_main_out_registers := (
......@@ -205,11 +209,13 @@ package fd_main_wbgen2_pkg is
tsbcr_enable_o => '0',
tsbcr_purge_o => '0',
tsbcr_rst_seq_o => '0',
tsbcr_raw_o => '0',
tsbir_timeout_o => (others => '0'),
tsbir_threshold_o => (others => '0'),
i2cr_scl_out_o => '0',
i2cr_sda_out_o => '0',
tder2_pelt_drive_o => (others => '0')
tder2_pelt_drive_o => (others => '0'),
tsbr_advance_adv_o => '0'
);
function "or" (left, right: t_fd_main_in_registers) return t_fd_main_in_registers;
function f_x_to_zero (x:std_logic) return std_logic;
......@@ -274,6 +280,7 @@ tmp.tsbr_fid_seqid_i := f_x_to_zero(left.tsbr_fid_seqid_i) or f_x_to_zero(right.
tmp.i2cr_scl_in_i := f_x_to_zero(left.i2cr_scl_in_i) or f_x_to_zero(right.i2cr_scl_in_i);
tmp.i2cr_sda_in_i := f_x_to_zero(left.i2cr_sda_in_i) or f_x_to_zero(right.i2cr_sda_in_i);
tmp.tder1_vcxo_freq_i := f_x_to_zero(left.tder1_vcxo_freq_i) or f_x_to_zero(right.tder1_vcxo_freq_i);
tmp.tsbr_debug_i := f_x_to_zero(left.tsbr_debug_i) or f_x_to_zero(right.tsbr_debug_i);
return tmp;
end function;
end package body;
hdl/rtl/fd_main_wishbone_slave.vhd
View file @ f911e540
......@@ -3,7 +3,7 @@
---------------------------------------------------------------------------------------
-- File : fd_main_wishbone_slave.vhd
-- Author : auto-generated by wbgen2 from fd_main_wishbone_slave.wb
-- Created : Wed Apr 11 11:05:21 2012
-- Created : Mon May 21 20:09:49 2012
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE fd_main_wishbone_slave.wb
......@@ -36,7 +36,8 @@ entity fd_main_wb_slave is
tcr_rd_ack_o : out std_logic;
calr_rd_ack_o : out std_logic;
spllr_rd_ack_o : out std_logic;
advance_rbuf_o : out std_logic;
tsbcr_read_ack_o : out std_logic;
fid_read_ack_o : out std_logic;
irq_ts_buf_notempty_i : in std_logic;
irq_dmtd_spll_i : in std_logic;
irq_sync_status_i : in std_logic;
......@@ -233,11 +234,14 @@ signal fd_main_tsbcr_rst_seq_int_delay : std_logic ;
signal fd_main_tsbcr_rst_seq_sync0 : std_logic ;
signal fd_main_tsbcr_rst_seq_sync1 : std_logic ;
signal fd_main_tsbcr_rst_seq_sync2 : std_logic ;
signal fd_main_tsbcr_raw_int : std_logic ;
signal fd_main_tsbir_timeout_int : std_logic_vector(9 downto 0);
signal fd_main_tsbir_threshold_int : std_logic_vector(11 downto 0);
signal fd_main_i2cr_scl_out_int : std_logic ;
signal fd_main_i2cr_sda_out_int : std_logic ;
signal fd_main_tder2_pelt_drive_int : std_logic_vector(31 downto 0);
signal fd_main_tsbr_advance_adv_dly0 : std_logic ;
signal fd_main_tsbr_advance_adv_int : std_logic ;
signal eic_idr_int : std_logic_vector(2 downto 0);
signal eic_idr_write_int : std_logic ;
signal eic_ier_int : std_logic_vector(2 downto 0);
......@@ -371,12 +375,15 @@ begin
fd_main_tsbcr_purge_int <= '0';
fd_main_tsbcr_rst_seq_int <= '0';
fd_main_tsbcr_rst_seq_int_delay <= '0';
tsbcr_read_ack_o <= '0';
fd_main_tsbcr_raw_int <= '0';
fd_main_tsbir_timeout_int <= "0000000000";
fd_main_tsbir_threshold_int <= "000000000000";
advance_rbuf_o <= '0';
fid_read_ack_o <= '0';
fd_main_i2cr_scl_out_int <= '0';
fd_main_i2cr_sda_out_int <= '0';
fd_main_tder2_pelt_drive_int <= "00000000000000000000000000000000";
fd_main_tsbr_advance_adv_int <= '0';
eic_idr_write_int <= '0';
eic_ier_write_int <= '0';
eic_isr_write_int <= '0';
......@@ -396,7 +403,9 @@ begin
regs_o.scr_data_load_o <= '0';
fd_main_scr_start_int <= '0';
fd_main_tsbcr_purge_int <= '0';
advance_rbuf_o <= '0';
tsbcr_read_ack_o <= '0';
fid_read_ack_o <= '0';
fd_main_tsbr_advance_adv_int <= '0';
eic_idr_write_int <= '0';
eic_ier_write_int <= '0';
eic_isr_write_int <= '0';
......@@ -1003,6 +1012,7 @@ begin
fd_main_tsbcr_purge_int <= wrdata_reg(6);
fd_main_tsbcr_rst_seq_int <= wrdata_reg(7);
fd_main_tsbcr_rst_seq_int_delay <= wrdata_reg(7);
fd_main_tsbcr_raw_int <= wrdata_reg(22);
end if;
rddata_reg(4 downto 0) <= fd_main_tsbcr_chan_mask_int;
rddata_reg(5) <= fd_main_tsbcr_enable_int;
......@@ -1010,8 +1020,9 @@ begin
rddata_reg(7) <= 'X';
rddata_reg(8) <= regs_i.tsbcr_full_i;
rddata_reg(9) <= regs_i.tsbcr_empty_i;
tsbcr_read_ack_o <= '1';
rddata_reg(21 downto 10) <= regs_i.tsbcr_count_i;
rddata_reg(22) <= 'X';
rddata_reg(22) <= fd_main_tsbcr_raw_int;
rddata_reg(23) <= 'X';
rddata_reg(24) <= 'X';
rddata_reg(25) <= 'X';
......@@ -1094,7 +1105,7 @@ begin
rddata_reg(3 downto 0) <= regs_i.tsbr_fid_channel_i;
rddata_reg(15 downto 4) <= regs_i.tsbr_fid_fine_i;
rddata_reg(31 downto 16) <= regs_i.tsbr_fid_seqid_i;
advance_rbuf_o <= '1';
fid_read_ack_o <= '1';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "011010" =>
......@@ -1149,6 +1160,51 @@ begin
rddata_reg(31 downto 0) <= fd_main_tder2_pelt_drive_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "011101" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= regs_i.tsbr_debug_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "011110" =>
if (wb_we_i = '1') then
fd_main_tsbr_advance_adv_int <= wrdata_reg(0);
end if;
rddata_reg(0) <= 'X';
rddata_reg(0) <= 'X';
rddata_reg(1) <= 'X';
rddata_reg(2) <= 'X';
rddata_reg(3) <= 'X';
rddata_reg(4) <= 'X';
rddata_reg(5) <= 'X';
rddata_reg(6) <= 'X';
rddata_reg(7) <= 'X';
rddata_reg(8) <= 'X';
rddata_reg(9) <= 'X';
rddata_reg(10) <= 'X';
rddata_reg(11) <= 'X';
rddata_reg(12) <= 'X';
rddata_reg(13) <= 'X';
rddata_reg(14) <= 'X';
rddata_reg(15) <= 'X';
rddata_reg(16) <= 'X';
rddata_reg(17) <= 'X';
rddata_reg(18) <= 'X';
rddata_reg(19) <= 'X';
rddata_reg(20) <= 'X';
rddata_reg(21) <= 'X';
rddata_reg(22) <= 'X';
rddata_reg(23) <= 'X';
rddata_reg(24) <= 'X';
rddata_reg(25) <= 'X';
rddata_reg(26) <= 'X';
rddata_reg(27) <= 'X';
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
ack_sreg(2) <= '1';
ack_in_progress <= '1';
when "100000" =>
if (wb_we_i = '1') then
eic_idr_write_int <= '1';
......@@ -1982,6 +2038,8 @@ begin
-- Buffer full
-- Buffer empty
-- Buffer entries count
-- RAW readout mode enable
regs_o.tsbcr_raw_o <= fd_main_tsbcr_raw_int;
-- IRQ timeout [milliseconds]
regs_o.tsbir_timeout_o <= fd_main_tsbir_timeout_int;
-- Interrupt threshold
......@@ -2001,6 +2059,20 @@ begin
-- VCXO Frequency
-- Peltier PWM drive
regs_o.tder2_pelt_drive_o <= fd_main_tder2_pelt_drive_int;
-- Debug value
-- Advance buffer readout
process (clk_sys_i, rst_n_i)
begin
if (rst_n_i = '0') then
fd_main_tsbr_advance_adv_dly0 <= '0';
regs_o.tsbr_advance_adv_o <= '0';
elsif rising_edge(clk_sys_i) then
fd_main_tsbr_advance_adv_dly0 <= fd_main_tsbr_advance_adv_int;
regs_o.tsbr_advance_adv_o <= fd_main_tsbr_advance_adv_int and (not fd_main_tsbr_advance_adv_dly0);
end if;
end process;
-- extra code for reg/fifo/mem: Interrupt disable register
eic_idr_int(2 downto 0) <= wrdata_reg(2 downto 0);
-- extra code for reg/fifo/mem: Interrupt enable register
......
hdl/rtl/fd_main_wishbone_slave.wb
View file @ f911e540
......@@ -753,7 +753,9 @@ write 0: DMTD pattern generation disabled.";
type = BIT;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
ack_read = "tsbcr_read_ack_o";
};
field {
name = "Buffer entries count";
prefix = "COUNT";
......@@ -762,6 +764,14 @@ write 0: DMTD pattern generation disabled.";
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
field {
name = "RAW readout mode enable";
prefix = "RAW";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
reg {
......@@ -861,7 +871,7 @@ write 0: DMTD pattern generation disabled.";
type = SLV;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
ack_read = "advance_rbuf_o";
ack_read = "fid_read_ack_o";
};
};
......@@ -927,6 +937,32 @@ write 0: DMTD pattern generation disabled.";
};
};
reg {
name = "Timestamp Buffer Debug Values Register";
prefix = "TSBR_DEBUG";
field {
name = "Debug value";
size = 32;
type = SLV;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "Timestamp Buffer Advance Register";
prefix = "TSBR_ADVANCE";
field {
name = "Advance buffer readout";
descriptor = "write 1: transfer the latest sample from the ring buffer to TSBR_SEC/CYCLES/FID registers,\
write 0: no effect";
type = MONOSTABLE;
prefix = "ADV";
};
};
irq {
name = "TS Buffer not empty.";
......
hdl/rtl/fd_ring_buffer.vhd
View file @ f911e540
......@@ -6,7 +6,7 @@
-- Author : Tomasz Wlostowski
-- Company : CERN
-- Created : 2011-08-24
-- Last update: 2012-05-01
-- Last update: 2012-05-22
-- Platform : FPGA-generic
-- Standard : VHDL'93
-------------------------------------------------------------------------------
......@@ -66,16 +66,18 @@ entity fd_ring_buffer is
---------------------------------------------------------------------------
-- Input tags (clk_ref_i domain)
---------------------------------------------------------------------------
tag_valid_i : in std_logic;
tag_valid_i : in std_logic;
-- Tag source : 0 = TDC, 1..4 = output channels
tag_source_i : in std_logic_vector(3 downto 0);
tag_utc_i : in std_logic_vector(c_TIMESTAMP_UTC_BITS-1 downto 0);
tag_coarse_i : in std_logic_vector(c_TIMESTAMP_COARSE_BITS-1 downto 0);
tag_frac_i : in std_logic_vector(c_TIMESTAMP_FRAC_BITS-1 downto 0);
-- Advances buffer readout by 1 timestamp. Asserted upon read of TSBR_FID register.
advance_rbuf_i : in std_logic;
tag_source_i : in std_logic_vector(3 downto 0);
tag_utc_i : in std_logic_vector(c_TIMESTAMP_UTC_BITS-1 downto 0);
tag_coarse_i : in std_logic_vector(c_TIMESTAMP_COARSE_BITS-1 downto 0);
tag_frac_i : in std_logic_vector(c_TIMESTAMP_FRAC_BITS-1 downto 0);
tag_dbg_raw_i : in std_logic_vector(31 downto 0);
-- Flushes the latest timestamp to the output registers
tsbcr_read_ack_i: in std_logic;
fid_read_ack_i: in std_logic;
-- Buffer interrupt (level-sensitive)
buf_irq_o : out std_logic;
......@@ -88,7 +90,7 @@ end fd_ring_buffer;
architecture behavioral of fd_ring_buffer is
constant c_PACKED_TS_SIZE : integer := 4 + c_TIMESTAMP_UTC_BITS + c_TIMESTAMP_COARSE_BITS + c_TIMESTAMP_FRAC_BITS + 16;
constant c_PACKED_TS_SIZE : integer := 32 + 4 + c_TIMESTAMP_UTC_BITS + c_TIMESTAMP_COARSE_BITS + c_TIMESTAMP_FRAC_BITS + 16;
constant c_FIFO_SIZE : integer := 8;
type t_internal_timestamp is record
......@@ -97,19 +99,21 @@ architecture behavioral of fd_ring_buffer is
coarse : std_logic_vector(c_TIMESTAMP_COARSE_BITS-1 downto 0);
frac : std_logic_vector(c_TIMESTAMP_FRAC_BITS-1 downto 0);
seq_id : std_logic_vector(15 downto 0);
dbg : std_logic_vector(31 downto 0);
end record;
function f_pack_timestamp(ts : t_internal_timestamp) return std_logic_vector is
begin
return ts.utc & ts.coarse & ts.frac & ts.seq_id & ts.src;
return ts.dbg & ts.utc & ts.coarse & ts.frac & ts.seq_id & ts.src;
end f_pack_timestamp;
function f_unpack_timestamp(ts : std_logic_vector)return t_internal_timestamp is
variable tmp : t_internal_timestamp;
begin
tmp.utc := ts(c_PACKED_TS_SIZE-1 downto c_PACKED_TS_SIZE-c_TIMESTAMP_UTC_BITS);
tmp.coarse := ts(c_PACKED_TS_SIZE-c_TIMESTAMP_UTC_BITS-1 downto c_PACKED_TS_SIZE-c_TIMESTAMP_UTC_BITS-c_TIMESTAMP_COARSE_BITS);
tmp.dbg := ts(c_PACKED_TS_SIZE-1 downto c_PACKED_TS_SIZE-32);
tmp.utc := ts(-32 + c_PACKED_TS_SIZE-1 downto -32 + c_PACKED_TS_SIZE-c_TIMESTAMP_UTC_BITS);
tmp.coarse := ts(-32 + c_PACKED_TS_SIZE-c_TIMESTAMP_UTC_BITS-1 downto -32 + c_PACKED_TS_SIZE-c_TIMESTAMP_UTC_BITS-c_TIMESTAMP_COARSE_BITS);
tmp.frac := ts(16+4+c_TIMESTAMP_FRAC_BITS-1 downto 16+4);
tmp.seq_id := ts(16+4-1 downto 4);
tmp.src := ts(3 downto 0);
......@@ -128,7 +132,7 @@ architecture behavioral of fd_ring_buffer is
signal buf_count : unsigned(g_size_log2 downto 0);
signal buf_full, buf_empty : std_logic;
signal buf_wr_data, buf_rd_data : std_logic_vector(c_PACKED_TS_SIZE-1 downto 0);
signal buf_write, buf_read : std_logic;
signal buf_write, buf_read, buf_overflow : std_logic;
signal buf_ram_out, buf_out_reg : t_internal_timestamp;
......@@ -137,12 +141,15 @@ architecture behavioral of fd_ring_buffer is
signal tmr_div : unsigned(f_log2_size(c_REF_CLK_FREQ/1000+1)-1 downto 0);
signal tmr_tick : std_logic;
signal tmr_timeout : unsigned(9 downto 0);
signal buf_irq_int : std_logic;
signal buf_read_d0, buf_read_d1 : std_logic;
signal tmr_div : unsigned(f_log2_size(c_REF_CLK_FREQ/1000+1)-1 downto 0);
signal tmr_tick : std_logic;
signal tmr_timeout : unsigned(9 downto 0);
signal buf_irq_int : std_logic;
signal buf_read_d0, buf_read_d1 : std_logic;
signal empty_d : std_logic_vector(4 downto 0);
signal read_ack, read_ack_d, read_ack_p : std_logic;
begin -- behavioral
......@@ -160,6 +167,7 @@ begin -- behavioral
fifo_in <= f_pack_timestamp(ts_fifo_in);
ts_fifo_in.dbg <= tag_dbg_raw_i;
ts_fifo_in.utc <= tag_utc_i;
ts_fifo_in.coarse <= tag_coarse_i;
ts_fifo_in.frac <= tag_frac_i;
......@@ -211,12 +219,13 @@ begin -- behavioral
buf_full <= '1' when (buf_wr_ptr + 1 = buf_rd_ptr) else '0';
buf_empty <= '1' when (buf_wr_ptr = buf_rd_ptr) else '0';
buf_write <= regs_i.tsbcr_enable_o and fifo_read_d0;
buf_read <= '1' when (advance_rbuf_i = '1' and buf_empty = '0') or (buf_write = '1' and buf_full = '1') else '0';
buf_overflow <= '1' when (buf_write = '1' and buf_full = '1') else '0';
buf_read <= '1' when (regs_i.tsbr_advance_adv_o = '1' and buf_empty = '0') or buf_overflow = '1' else '0';
buf_ram_out <= f_unpack_timestamp(buf_rd_data);
-- drive WB registers
regs_o.tsbcr_empty_i <= buf_empty;
regs_o.tsbcr_full_i <= buf_full;
regs_o.tsbcr_empty_i <= buf_empty;
p_buffer_control : process(clk_sys_i)
begin
......@@ -226,14 +235,12 @@ begin -- behavioral
buf_wr_ptr <= (others => '0');
buf_count <= (others => '0');
fifo_read_d0 <= '0';
buf_read_d0 <= '0';
buf_read_d1 <= '0';
else
fifo_read_d0 <= fifo_read;
buf_read_d0 <= buf_read;
buf_read_d1 <= buf_read_d0;
fifo_read_d0 <= fifo_read;
if(buf_write = '1') then
buf_wr_ptr <= buf_wr_ptr + 1;
end if;
......@@ -256,9 +263,7 @@ begin -- behavioral
p_output_register : process(clk_sys_i)
begin
if rising_edge(clk_sys_i) then
if(buf_write = '1' and buf_empty = '1') then
buf_out_reg <= f_unpack_timestamp(buf_wr_data);
elsif(buf_read_d1 = '1') then
if(buf_read = '1' and buf_overflow = '0') then
buf_out_reg <= buf_ram_out;
end if;
end if;
......@@ -317,12 +322,15 @@ begin -- behavioral
end if;
end process;
regs_o.tsbr_sech_i <= buf_out_reg.utc(39 downto 32);
regs_o.tsbr_secl_i <= buf_out_reg.utc(31 downto 0);
regs_o.tsbr_cycles_i <= buf_out_reg.coarse;
regs_o.tsbr_fid_fine_i <= buf_out_reg.frac;
regs_o.tsbr_fid_seqid_i <= buf_out_reg.seq_id;
regs_o.tsbr_fid_channel_i <= buf_out_reg.src;
regs_o.tsbr_debug_i <= buf_out_reg.dbg;
regs_o.tsbcr_count_i <= std_logic_vector(resize(buf_count, regs_o.tsbcr_count_i'length));
buf_irq_o <= buf_irq_int;
......
hdl/rtl/fine_delay_core.vhd
View file @ f911e540
......@@ -6,7 +6,7 @@
-- Author : Tomasz Wlostowski
-- Company : CERN
-- Created : 2011-08-24
-- Last update: 2012-04-25
-- Last update: 2012-05-21
-- Platform : FPGA-generic
-- Standard : VHDL'93
-------------------------------------------------------------------------------
......@@ -253,6 +253,7 @@ architecture rtl of fine_delay_core is
signal tag_frac : std_logic_vector(c_TIMESTAMP_FRAC_BITS-1 downto 0);
signal tag_coarse : std_logic_vector(c_TIMESTAMP_COARSE_BITS-1 downto 0);
signal tag_utc : std_logic_vector(c_TIMESTAMP_UTC_BITS-1 downto 0);
signal tag_dbg : std_logic_vector(31 downto 0);
signal tag_valid : std_logic;
signal rbuf_mux_ts : t_timestamp_array(0 to 4);
......@@ -271,7 +272,7 @@ architecture rtl of fine_delay_core is
signal rst_n_sys, rst_n_ref : std_logic;
signal advance_rbuf : std_logic;
signal tsbcr_read_ack, fid_read_ack : std_logic;
signal irq_rbuf, irq_spll, irq_sync : std_logic;
......@@ -463,7 +464,8 @@ begin -- rtl
irq_ts_buf_notempty_i => irq_rbuf,
irq_dmtd_spll_i => irq_spll,
irq_sync_status_i => irq_sync,
advance_rbuf_o => advance_rbuf,
tsbcr_read_ack_o => tsbcr_read_ack,
fid_read_ack_o => fid_read_ack,
spllr_rd_ack_o => spllr_rd_ack,
calr_rd_ack_o => calr_rd_ack
);
......@@ -496,6 +498,7 @@ begin -- rtl
tag_coarse_o => tag_coarse,
tag_utc_o => tag_utc,
tag_valid_o => tag_valid,
tag_dbg_raw_o => tag_dbg,
tag_rearm_p1_i => '1',
......@@ -549,8 +552,10 @@ begin -- rtl
tag_utc_i => rbuf_in_ts.u,
tag_coarse_i => rbuf_in_ts.c,
tag_frac_i => rbuf_in_ts.f,
tag_dbg_raw_i => tag_dbg,
advance_rbuf_i => advance_rbuf,
tsbcr_read_ack_i => tsbcr_read_ack,
fid_read_ack_i => fid_read_ack,
buf_irq_o => irq_rbuf,
regs_i => regs_fromwb,
regs_o => regs_towb_rbuf);
......
hdl/rtl/fine_delay_pkg.vhd
View file @ f911e540
......@@ -6,7 +6,7 @@
-- Author : Tomasz Wlostowski
-- Company : CERN
-- Created : 2011-08-24
-- Last update: 2012-04-25
-- Last update: 2012-05-21
-- Platform : FPGA-generic
-- Standard : VHDL'93
-------------------------------------------------------------------------------
......@@ -53,24 +53,24 @@ package fine_delay_pkg is
-----------------------------------------------------------------------------
-- Timestamp field bits (if you change them, you must also change the WB files)
constant c_TIMESTAMP_UTC_BITS : integer := 40;
constant c_TIMESTAMP_COARSE_BITS : integer := 28;
constant c_TIMESTAMP_FRAC_BITS : integer := 12;
constant c_TIMESTAMP_UTC_BITS : integer := 40;
constant c_TIMESTAMP_COARSE_BITS : integer := 28;
constant c_TIMESTAMP_FRAC_BITS : integer := 12;
-- log2(Number of entries in the timestamp buffer)
constant c_RING_BUFFER_SIZE_LOG2 : integer := 10;
constant c_RING_BUFFER_SIZE_LOG2 : integer := 10;
-- Reference clock frequency in Hz
constant c_REF_CLK_FREQ : integer := 125000000;
constant c_REF_CLK_FREQ : integer := 125000000;
-- System clock frequency in Hz
constant c_SYS_CLK_FREQ : integer := 62500000;
constant c_SYS_CLK_FREQ : integer := 62500000;
-- Reference clock period in picoseconds
constant c_REF_CLK_PERIOD_PS : integer := 8000;
constant c_REF_CLK_PERIOD_PS : integer := 8000;
-- Number of card outputs
constant c_FD_NUM_OUTPUTS : integer := 4;
constant c_FD_NUM_OUTPUTS : integer := 4;
-- Number of reference clock cycles per one DDMTD calibration period
constant c_FD_DMTD_CALIBRATION_PERIOD : integer := 125;
......@@ -93,7 +93,7 @@ package fine_delay_pkg is
dev_version => x"00000001",
dev_date => x"20120425",
description => "Fine Delay Core ");
type t_fd_timestamp is record
u : std_logic_vector(c_TIMESTAMP_UTC_BITS-1 downto 0);
c : std_logic_vector(c_TIMESTAMP_COARSE_BITS-1 downto 0);
......@@ -183,6 +183,7 @@ package fine_delay_pkg is
tag_coarse_o : out std_logic_vector(c_TIMESTAMP_COARSE_BITS-1 downto 0);
tag_utc_o : out std_logic_vector(c_TIMESTAMP_UTC_BITS-1 downto 0);
tag_rearm_p1_i : in std_logic;
tag_dbg_raw_o : out std_logic_vector(31 downto 0);
tag_valid_o : out std_logic;
csync_coarse_i : in std_logic_vector(c_TIMESTAMP_COARSE_BITS-1 downto 0);
csync_utc_i : in std_logic_vector(c_TIMESTAMP_UTC_BITS-1 downto 0);
......@@ -214,7 +215,7 @@ package fine_delay_pkg is
regs_i : in t_fd_main_out_registers;
regs_o : out t_fd_main_in_registers;
tcr_rd_ack_i : in std_logic;
csync_pps_o: out std_logic;
csync_pps_o : out std_logic;
irq_sync_o : out std_logic);
end component;
......@@ -254,7 +255,8 @@ package fine_delay_pkg is
tcr_rd_ack_o : out std_logic;
calr_rd_ack_o : out std_logic;
spllr_rd_ack_o : out std_logic;
advance_rbuf_o : out std_logic;
tsbcr_read_ack_o : out std_logic;
fid_read_ack_o: out std_logic;
irq_ts_buf_notempty_i : in std_logic;
irq_dmtd_spll_i : in std_logic;
irq_sync_status_i : in std_logic;
......@@ -329,24 +331,25 @@ package fine_delay_pkg is
dmtd_dac_wr_o : out std_logic);
end component;
component fd_ring_buffer
generic (
g_size_log2 : integer);
port (
rst_n_sys_i : in std_logic;
rst_n_ref_i : in std_logic;
clk_ref_i : in std_logic;
clk_sys_i : in std_logic;
tag_valid_i : in std_logic;
tag_source_i : in std_logic_vector(3 downto 0);
tag_utc_i : in std_logic_vector(c_TIMESTAMP_UTC_BITS-1 downto 0);
tag_coarse_i : in std_logic_vector(c_TIMESTAMP_COARSE_BITS-1 downto 0);
tag_frac_i : in std_logic_vector(c_TIMESTAMP_FRAC_BITS-1 downto 0);
advance_rbuf_i : in std_logic;
buf_irq_o : out std_logic;
regs_i : in t_fd_main_out_registers;
regs_o : out t_fd_main_in_registers);
rst_n_sys_i : in std_logic;
rst_n_ref_i : in std_logic;
clk_ref_i : in std_logic;
clk_sys_i : in std_logic;
tag_valid_i : in std_logic;
tag_source_i : in std_logic_vector(3 downto 0);
tag_utc_i : in std_logic_vector(c_TIMESTAMP_UTC_BITS-1 downto 0);
tag_coarse_i : in std_logic_vector(c_TIMESTAMP_COARSE_BITS-1 downto 0);
tag_frac_i : in std_logic_vector(c_TIMESTAMP_FRAC_BITS-1 downto 0);
tag_dbg_raw_i : in std_logic_vector(31 downto 0);
tsbcr_read_ack_i : in std_logic;
fid_read_ack_i : in std_logic;
buf_irq_o : out std_logic;
regs_i : in t_fd_main_out_registers;
regs_o : out t_fd_main_in_registers);
end component;
component fd_spi_dac_arbiter
......@@ -376,7 +379,7 @@ package fine_delay_pkg is
q_o : out std_logic);
end component;
component fine_delay_core
component fine_delay_core
generic (
g_with_wr_core : boolean;
g_simulation : boolean;
......
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