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FMC DEL 1ns 4cha
Commits
f6a2b0a9
Commit
f6a2b0a9
authored
Apr 02, 2019
by
Tomasz Wlostowski
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hdl: added IODELAY control to the WB register block
parent
198cf18b
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5 changed files
with
2680 additions
and
2481 deletions
+2680
-2481
fd_channel_wbgen2_pkg.vhd
hdl/rtl/fd_channel_wbgen2_pkg.vhd
+100
-74
fd_channel_wishbone_slave.vhd
hdl/rtl/fd_channel_wishbone_slave.vhd
+531
-532
fd_main_wbgen2_pkg.vhd
hdl/rtl/fd_main_wbgen2_pkg.vhd
+214
-171
fd_main_wishbone_slave.vhd
hdl/rtl/fd_main_wishbone_slave.vhd
+1793
-1703
fd_main_wishbone_slave.wb
hdl/rtl/fd_main_wishbone_slave.wb
+42
-1
No files found.
hdl/rtl/fd_channel_wbgen2_pkg.vhd
View file @
f6a2b0a9
...
...
@@ -3,7 +3,7 @@
---------------------------------------------------------------------------------------
-- File : fd_channel_wbgen2_pkg.vhd
-- Author : auto-generated by wbgen2 from fd_channel_wishbone_slave.wb
-- Created : Wed
Dec 4 17:20:17 2013
-- Created : Wed
Mar 20 23:27:12 2019
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE fd_channel_wishbone_slave.wb
...
...
@@ -78,37 +78,63 @@ package fd_channel_wbgen2_pkg is
rcr_rep_cnt_o
=>
(
others
=>
'0'
),
rcr_cont_o
=>
'0'
);
function
"or"
(
left
,
right
:
t_fd_channel_in_registers
)
return
t_fd_channel_in_registers
;
function
f_x_to_zero
(
x
:
std_logic
)
return
std_logic
;
function
f_x_to_zero
(
x
:
std_logic_vector
)
return
std_logic_vector
;
function
"or"
(
left
,
right
:
t_fd_channel_in_registers
)
return
t_fd_channel_in_registers
;
function
f_x_to_zero
(
x
:
std_logic
)
return
std_logic
;
function
f_x_to_zero
(
x
:
std_logic_vector
)
return
std_logic_vector
;
component
fd_channel_wb_slave
is
port
(
rst_n_i
:
in
std_logic
;
clk_sys_i
:
in
std_logic
;
wb_adr_i
:
in
std_logic_vector
(
3
downto
0
);
wb_dat_i
:
in
std_logic_vector
(
31
downto
0
);
wb_dat_o
:
out
std_logic_vector
(
31
downto
0
);
wb_cyc_i
:
in
std_logic
;
wb_sel_i
:
in
std_logic_vector
(
3
downto
0
);
wb_stb_i
:
in
std_logic
;
wb_we_i
:
in
std_logic
;
wb_ack_o
:
out
std_logic
;
wb_err_o
:
out
std_logic
;
wb_rty_o
:
out
std_logic
;
wb_stall_o
:
out
std_logic
;
clk_ref_i
:
in
std_logic
;
regs_i
:
in
t_fd_channel_in_registers
;
regs_o
:
out
t_fd_channel_out_registers
);
end
component
;
end
package
;
package
body
fd_channel_wbgen2_pkg
is
function
f_x_to_zero
(
x
:
std_logic
)
return
std_logic
is
begin
if
x
=
'1'
then
return
'1'
;
else
return
'0'
;
end
if
;
if
x
=
'1'
then
return
'1'
;
else
return
'0'
;
end
if
;
end
function
;
function
f_x_to_zero
(
x
:
std_logic_vector
)
return
std_logic_vector
is
variable
tmp
:
std_logic_vector
(
x
'length
-1
downto
0
);
variable
tmp
:
std_logic_vector
(
x
'length
-1
downto
0
);
begin
for
i
in
0
to
x
'length
-1
loop
if
(
x
(
i
)
=
'X'
or
x
(
i
)
=
'U'
)
then
tmp
(
i
):
=
'0'
;
else
tmp
(
i
):
=
x
(
i
);
end
if
;
end
loop
;
return
tmp
;
for
i
in
0
to
x
'length
-1
loop
if
(
x
(
i
)
=
'X'
or
x
(
i
)
=
'U'
)
then
tmp
(
i
):
=
'0'
;
else
tmp
(
i
):
=
x
(
i
);
end
if
;
end
loop
;
return
tmp
;
end
function
;
function
"or"
(
left
,
right
:
t_fd_channel_in_registers
)
return
t_fd_channel_in_registers
is
variable
tmp
:
t_fd_channel_in_registers
;
variable
tmp
:
t_fd_channel_in_registers
;
begin
tmp
.
dcr_pg_trig_i
:
=
f_x_to_zero
(
left
.
dcr_pg_trig_i
)
or
f_x_to_zero
(
right
.
dcr_pg_trig_i
);
tmp
.
dcr_upd_done_i
:
=
f_x_to_zero
(
left
.
dcr_upd_done_i
)
or
f_x_to_zero
(
right
.
dcr_upd_done_i
);
return
tmp
;
tmp
.
dcr_pg_trig_i
:
=
f_x_to_zero
(
left
.
dcr_pg_trig_i
)
or
f_x_to_zero
(
right
.
dcr_pg_trig_i
);
tmp
.
dcr_upd_done_i
:
=
f_x_to_zero
(
left
.
dcr_upd_done_i
)
or
f_x_to_zero
(
right
.
dcr_upd_done_i
);
return
tmp
;
end
function
;
end
package
body
;
hdl/rtl/fd_channel_wishbone_slave.vhd
View file @
f6a2b0a9
...
...
@@ -3,7 +3,7 @@
---------------------------------------------------------------------------------------
-- File : fd_channel_wishbone_slave.vhd
-- Author : auto-generated by wbgen2 from fd_channel_wishbone_slave.wb
-- Created : Wed
Dec 4 17:20:17 2013
-- Created : Wed
Mar 20 23:27:12 2019
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE fd_channel_wishbone_slave.wb
...
...
@@ -18,7 +18,7 @@ use work.fd_channel_wbgen2_pkg.all;
entity
fd_channel_wb_slave
is
port
(
port
(
rst_n_i
:
in
std_logic
;
clk_sys_i
:
in
std_logic
;
wb_adr_i
:
in
std_logic_vector
(
3
downto
0
);
...
...
@@ -29,11 +29,13 @@ entity fd_channel_wb_slave is
wb_stb_i
:
in
std_logic
;
wb_we_i
:
in
std_logic
;
wb_ack_o
:
out
std_logic
;
wb_err_o
:
out
std_logic
;
wb_rty_o
:
out
std_logic
;
wb_stall_o
:
out
std_logic
;
clk_ref_i
:
in
std_logic
;
regs_i
:
in
t_fd_channel_in_registers
;
regs_o
:
out
t_fd_channel_out_registers
);
);
end
fd_channel_wb_slave
;
architecture
syn
of
fd_channel_wb_slave
is
...
...
@@ -94,17 +96,12 @@ signal allones : std_logic_vector(31 downto 0);
signal
allzeros
:
std_logic_vector
(
31
downto
0
);
begin
-- Some internal signals assignments. For (foreseen) compatibility with other bus standards.
wrdata_reg
<=
wb_dat_i
;
bwsel_reg
<=
wb_sel_i
;
rd_int
<=
wb_cyc_i
and
(
wb_stb_i
and
(
not
wb_we_i
));
wr_int
<=
wb_cyc_i
and
(
wb_stb_i
and
wb_we_i
);
allones
<=
(
others
=>
'1'
);
allzeros
<=
(
others
=>
'0'
);
-- Some internal signals assignments
wrdata_reg
<=
wb_dat_i
;
--
-- Main register bank access process.
process
(
clk_sys_i
,
rst_n_i
)
begin
process
(
clk_sys_i
,
rst_n_i
)
begin
if
(
rst_n_i
=
'0'
)
then
ack_sreg
<=
"0000000000"
;
ack_in_progress
<=
'0'
;
...
...
@@ -490,15 +487,15 @@ begin
end
if
;
end
if
;
end
if
;
end
process
;
end
process
;
-- Drive the data output bus
wb_dat_o
<=
rddata_reg
;
wb_dat_o
<=
rddata_reg
;
-- Enable channel
-- synchronizer chain for field : Enable channel (type RW/RO, clk_sys_i <-> clk_ref_i)
process
(
clk_ref_i
,
rst_n_i
)
begin
process
(
clk_ref_i
,
rst_n_i
)
begin
if
(
rst_n_i
=
'0'
)
then
regs_o
.
dcr_enable_o
<=
'0'
;
fd_channel_dcr_enable_sync0
<=
'0'
;
...
...
@@ -508,14 +505,14 @@ begin
fd_channel_dcr_enable_sync1
<=
fd_channel_dcr_enable_sync0
;
regs_o
.
dcr_enable_o
<=
fd_channel_dcr_enable_sync1
;
end
if
;
end
process
;
end
process
;
-- Delay mode select
regs_o
.
dcr_mode_o
<=
fd_channel_dcr_mode_int
;
regs_o
.
dcr_mode_o
<=
fd_channel_dcr_mode_int
;
-- Pulse generator arm
process
(
clk_ref_i
,
rst_n_i
)
begin
process
(
clk_ref_i
,
rst_n_i
)
begin
if
(
rst_n_i
=
'0'
)
then
regs_o
.
dcr_pg_arm_o
<=
'0'
;
fd_channel_dcr_pg_arm_sync0
<=
'0'
;
...
...
@@ -527,13 +524,13 @@ begin
fd_channel_dcr_pg_arm_sync2
<=
fd_channel_dcr_pg_arm_sync1
;
regs_o
.
dcr_pg_arm_o
<=
fd_channel_dcr_pg_arm_sync2
and
(
not
fd_channel_dcr_pg_arm_sync1
);
end
if
;
end
process
;
end
process
;
-- Pulse generator triggered
-- synchronizer chain for field : Pulse generator triggered (type RO/WO, clk_ref_i -> clk_sys_i)
process
(
clk_ref_i
,
rst_n_i
)
begin
process
(
clk_ref_i
,
rst_n_i
)
begin
if
(
rst_n_i
=
'0'
)
then
fd_channel_dcr_pg_trig_sync0
<=
'0'
;
fd_channel_dcr_pg_trig_sync1
<=
'0'
;
...
...
@@ -541,12 +538,12 @@ begin
fd_channel_dcr_pg_trig_sync0
<=
regs_i
.
dcr_pg_trig_i
;
fd_channel_dcr_pg_trig_sync1
<=
fd_channel_dcr_pg_trig_sync0
;
end
if
;
end
process
;
end
process
;
-- Update delay/absolute trigger time
process
(
clk_ref_i
,
rst_n_i
)
begin
process
(
clk_ref_i
,
rst_n_i
)
begin
if
(
rst_n_i
=
'0'
)
then
regs_o
.
dcr_update_o
<=
'0'
;
fd_channel_dcr_update_sync0
<=
'0'
;
...
...
@@ -558,13 +555,13 @@ begin
fd_channel_dcr_update_sync2
<=
fd_channel_dcr_update_sync1
;
regs_o
.
dcr_update_o
<=
fd_channel_dcr_update_sync2
and
(
not
fd_channel_dcr_update_sync1
);
end
if
;
end
process
;
end
process
;
-- Delay update done flag
-- synchronizer chain for field : Delay update done flag (type RO/WO, clk_ref_i -> clk_sys_i)
process
(
clk_ref_i
,
rst_n_i
)
begin
process
(
clk_ref_i
,
rst_n_i
)
begin
if
(
rst_n_i
=
'0'
)
then
fd_channel_dcr_upd_done_sync0
<=
'0'
;
fd_channel_dcr_upd_done_sync1
<=
'0'
;
...
...
@@ -572,12 +569,12 @@ begin
fd_channel_dcr_upd_done_sync0
<=
regs_i
.
dcr_upd_done_i
;
fd_channel_dcr_upd_done_sync1
<=
fd_channel_dcr_upd_done_sync0
;
end
if
;
end
process
;
end
process
;
-- Force calibration delay
process
(
clk_ref_i
,
rst_n_i
)
begin
process
(
clk_ref_i
,
rst_n_i
)
begin
if
(
rst_n_i
=
'0'
)
then
regs_o
.
dcr_force_dly_o
<=
'0'
;
fd_channel_dcr_force_dly_sync0
<=
'0'
;
...
...
@@ -589,17 +586,17 @@ begin
fd_channel_dcr_force_dly_sync2
<=
fd_channel_dcr_force_dly_sync1
;
regs_o
.
dcr_force_dly_o
<=
fd_channel_dcr_force_dly_sync2
and
(
not
fd_channel_dcr_force_dly_sync1
);
end
if
;
end
process
;
end
process
;
-- Disable fine part update
regs_o
.
dcr_no_fine_o
<=
fd_channel_dcr_no_fine_int
;
regs_o
.
dcr_no_fine_o
<=
fd_channel_dcr_no_fine_int
;
-- Force output high
regs_o
.
dcr_force_hi_o
<=
fd_channel_dcr_force_hi_int
;
regs_o
.
dcr_force_hi_o
<=
fd_channel_dcr_force_hi_int
;
-- Fine range in SY89825 taps.
-- asynchronous std_logic_vector register : Fine range in SY89825 taps. (type RW/RO, clk_ref_i <-> clk_sys_i)
process
(
clk_ref_i
,
rst_n_i
)
begin
process
(
clk_ref_i
,
rst_n_i
)
begin
if
(
rst_n_i
=
'0'
)
then
fd_channel_frr_swb_s0
<=
'0'
;
fd_channel_frr_swb_s1
<=
'0'
;
...
...
@@ -613,37 +610,39 @@ begin
regs_o
.
frr_o
<=
fd_channel_frr_int
;
end
if
;
end
if
;
end
process
;
end
process
;
-- TAI seconds (MSB)
regs_o
.
u_starth_o
<=
fd_channel_u_starth_int
;
regs_o
.
u_starth_o
<=
fd_channel_u_starth_int
;
-- TAI seconds (LSB)
regs_o
.
u_startl_o
<=
fd_channel_u_startl_int
;
regs_o
.
u_startl_o
<=
fd_channel_u_startl_int
;
-- Reference clock cycles
regs_o
.
c_start_o
<=
fd_channel_c_start_int
;
regs_o
.
c_start_o
<=
fd_channel_c_start_int
;
-- Fractional part
regs_o
.
f_start_o
<=
fd_channel_f_start_int
;
regs_o
.
f_start_o
<=
fd_channel_f_start_int
;
-- TAI seconds (MSB)
regs_o
.
u_endh_o
<=
fd_channel_u_endh_int
;
regs_o
.
u_endh_o
<=
fd_channel_u_endh_int
;
-- TAI seconds (LSB)
regs_o
.
u_endl_o
<=
fd_channel_u_endl_int
;
regs_o
.
u_endl_o
<=
fd_channel_u_endl_int
;
-- Reference clock cycles
regs_o
.
c_end_o
<=
fd_channel_c_end_int
;
regs_o
.
c_end_o
<=
fd_channel_c_end_int
;
-- Fractional part
regs_o
.
f_end_o
<=
fd_channel_f_end_int
;
regs_o
.
f_end_o
<=
fd_channel_f_end_int
;
-- TAI seconds
regs_o
.
u_delta_o
<=
fd_channel_u_delta_int
;
regs_o
.
u_delta_o
<=
fd_channel_u_delta_int
;
-- Reference clock cycles
regs_o
.
c_delta_o
<=
fd_channel_c_delta_int
;
regs_o
.
c_delta_o
<=
fd_channel_c_delta_int
;
-- Fractional part
regs_o
.
f_delta_o
<=
fd_channel_f_delta_int
;
regs_o
.
f_delta_o
<=
fd_channel_f_delta_int
;
-- Repeat Count
regs_o
.
rcr_rep_cnt_o
<=
fd_channel_rcr_rep_cnt_int
;
regs_o
.
rcr_rep_cnt_o
<=
fd_channel_rcr_rep_cnt_int
;
-- Continuous Waveform Mode
regs_o
.
rcr_cont_o
<=
fd_channel_rcr_cont_int
;
rwaddr_reg
<=
wb_adr_i
;
wb_stall_o
<=
(
not
ack_sreg
(
0
))
and
(
wb_stb_i
and
wb_cyc_i
);
regs_o
.
rcr_cont_o
<=
fd_channel_rcr_cont_int
;
rwaddr_reg
<=
wb_adr_i
;
wb_stall_o
<=
(
not
ack_sreg
(
0
))
and
(
wb_stb_i
and
wb_cyc_i
);
wb_err_o
<=
'0'
;
wb_rty_o
<=
'0'
;
-- ACK signal generation. Just pass the LSB of ACK counter.
wb_ack_o
<=
ack_sreg
(
0
);
wb_ack_o
<=
ack_sreg
(
0
);
end
syn
;
hdl/rtl/fd_main_wbgen2_pkg.vhd
View file @
f6a2b0a9
This diff is collapsed.
Click to expand it.
hdl/rtl/fd_main_wishbone_slave.vhd
View file @
f6a2b0a9
This diff is collapsed.
Click to expand it.
hdl/rtl/fd_main_wishbone_slave.wb
View file @
f6a2b0a9
...
...
@@ -404,6 +404,47 @@ peripheral {
prefix = "ALUTRIG";
type = MONOSTABLE;
};
field {
clock = "clk_ref_i";
name = "IDELAY CE (pulse)";
description = "Write 1 to pulse the IDELAY CE line for 1 clock tick.";
prefix = "IDELAY_CE";
type = MONOSTABLE;
};
field {
clock = "clk_ref_i";
name = "IDELAY RST (GPIO)";
description = "State of IDELAY RST line";
prefix = "IDELAY_RST";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
clock = "clk_ref_i";
name = "IDELAY CAL (GPIO)";
description = "State of IDELAY CAL line";
prefix = "IDELAY_CAL";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
clock = "clk_ref_i";
name = "IDELAY CAL (GPIO)";
description = "State of IDELAY INC line";
prefix = "IDELAY_INC";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
reg {
...
...
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