Skip to content

F
FMC DEL 1ns 4cha
Commit f6a2b0a9 authored by Tomasz Wlostowski's avatar Tomasz Wlostowski
Browse files
Options

hdl: added IODELAY control to the WB register block

parent 198cf18b
Hide whitespace changes
Inline Side-by-side
Showing with 2680 additions and 2481 deletions
hdl/rtl/fd_channel_wbgen2_pkg.vhd
View file @ f6a2b0a9
......@@ -3,7 +3,7 @@
---------------------------------------------------------------------------------------
-- File : fd_channel_wbgen2_pkg.vhd
-- Author : auto-generated by wbgen2 from fd_channel_wishbone_slave.wb
-- Created : Wed Dec 4 17:20:17 2013
-- Created : Wed Mar 20 23:27:12 2019
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE fd_channel_wishbone_slave.wb
......@@ -22,93 +22,119 @@ package fd_channel_wbgen2_pkg is
type t_fd_channel_in_registers is record
dcr_pg_trig_i : std_logic;
dcr_upd_done_i : std_logic;
end record;
end record;
constant c_fd_channel_in_registers_init_value: t_fd_channel_in_registers := (
dcr_pg_trig_i => '0',
dcr_upd_done_i => '0'
);
-- Output registers (WB slave -> user design)
type t_fd_channel_out_registers is record
dcr_enable_o : std_logic;
dcr_mode_o : std_logic;
dcr_pg_arm_o : std_logic;
dcr_update_o : std_logic;
dcr_force_dly_o : std_logic;
dcr_no_fine_o : std_logic;
dcr_force_hi_o : std_logic;
frr_o : std_logic_vector(9 downto 0);
u_starth_o : std_logic_vector(7 downto 0);
u_startl_o : std_logic_vector(31 downto 0);
c_start_o : std_logic_vector(27 downto 0);
f_start_o : std_logic_vector(11 downto 0);
u_endh_o : std_logic_vector(7 downto 0);
u_endl_o : std_logic_vector(31 downto 0);
c_end_o : std_logic_vector(27 downto 0);
f_end_o : std_logic_vector(11 downto 0);
u_delta_o : std_logic_vector(3 downto 0);
c_delta_o : std_logic_vector(27 downto 0);
f_delta_o : std_logic_vector(11 downto 0);
rcr_rep_cnt_o : std_logic_vector(15 downto 0);
rcr_cont_o : std_logic;
end record;
constant c_fd_channel_out_registers_init_value: t_fd_channel_out_registers := (
dcr_enable_o => '0',
dcr_mode_o => '0',
dcr_pg_arm_o => '0',
dcr_update_o => '0',
dcr_force_dly_o => '0',
dcr_no_fine_o => '0',
dcr_force_hi_o => '0',
frr_o => (others => '0'),
u_starth_o => (others => '0'),
u_startl_o => (others => '0'),
c_start_o => (others => '0'),
f_start_o => (others => '0'),
u_endh_o => (others => '0'),
u_endl_o => (others => '0'),
c_end_o => (others => '0'),
f_end_o => (others => '0'),
u_delta_o => (others => '0'),
c_delta_o => (others => '0'),
f_delta_o => (others => '0'),
rcr_rep_cnt_o => (others => '0'),
rcr_cont_o => '0'
);
function "or" (left, right: t_fd_channel_in_registers) return t_fd_channel_in_registers;
function f_x_to_zero (x:std_logic) return std_logic;
function f_x_to_zero (x:std_logic_vector) return std_logic_vector;
);
-- Output registers (WB slave -> user design)
type t_fd_channel_out_registers is record
dcr_enable_o : std_logic;
dcr_mode_o : std_logic;
dcr_pg_arm_o : std_logic;
dcr_update_o : std_logic;
dcr_force_dly_o : std_logic;
dcr_no_fine_o : std_logic;
dcr_force_hi_o : std_logic;
frr_o : std_logic_vector(9 downto 0);
u_starth_o : std_logic_vector(7 downto 0);
u_startl_o : std_logic_vector(31 downto 0);
c_start_o : std_logic_vector(27 downto 0);
f_start_o : std_logic_vector(11 downto 0);
u_endh_o : std_logic_vector(7 downto 0);
u_endl_o : std_logic_vector(31 downto 0);
c_end_o : std_logic_vector(27 downto 0);
f_end_o : std_logic_vector(11 downto 0);
u_delta_o : std_logic_vector(3 downto 0);
c_delta_o : std_logic_vector(27 downto 0);
f_delta_o : std_logic_vector(11 downto 0);
rcr_rep_cnt_o : std_logic_vector(15 downto 0);
rcr_cont_o : std_logic;
end record;
constant c_fd_channel_out_registers_init_value: t_fd_channel_out_registers := (
dcr_enable_o => '0',
dcr_mode_o => '0',
dcr_pg_arm_o => '0',
dcr_update_o => '0',
dcr_force_dly_o => '0',
dcr_no_fine_o => '0',
dcr_force_hi_o => '0',
frr_o => (others => '0'),
u_starth_o => (others => '0'),
u_startl_o => (others => '0'),
c_start_o => (others => '0'),
f_start_o => (others => '0'),
u_endh_o => (others => '0'),
u_endl_o => (others => '0'),
c_end_o => (others => '0'),
f_end_o => (others => '0'),
u_delta_o => (others => '0'),
c_delta_o => (others => '0'),
f_delta_o => (others => '0'),
rcr_rep_cnt_o => (others => '0'),
rcr_cont_o => '0'
);
function "or" (left, right: t_fd_channel_in_registers) return t_fd_channel_in_registers;
function f_x_to_zero (x:std_logic) return std_logic;
function f_x_to_zero (x:std_logic_vector) return std_logic_vector;
component fd_channel_wb_slave is
port (
rst_n_i : in std_logic;
clk_sys_i : in std_logic;
wb_adr_i : in std_logic_vector(3 downto 0);
wb_dat_i : in std_logic_vector(31 downto 0);
wb_dat_o : out std_logic_vector(31 downto 0);
wb_cyc_i : in std_logic;
wb_sel_i : in std_logic_vector(3 downto 0);
wb_stb_i : in std_logic;
wb_we_i : in std_logic;
wb_ack_o : out std_logic;
wb_err_o : out std_logic;
wb_rty_o : out std_logic;
wb_stall_o : out std_logic;
clk_ref_i : in std_logic;
regs_i : in t_fd_channel_in_registers;
regs_o : out t_fd_channel_out_registers
);
end component;
end package;
package body fd_channel_wbgen2_pkg is
function f_x_to_zero (x:std_logic) return std_logic is
begin
if x = '1' then
return '1';
else
return '0';
end if;
if x = '1' then
return '1';
else
return '0';
end if;
end function;
function f_x_to_zero (x:std_logic_vector) return std_logic_vector is
variable tmp: std_logic_vector(x'length-1 downto 0);
variable tmp: std_logic_vector(x'length-1 downto 0);
begin
for i in 0 to x'length-1 loop
if(x(i) = 'X' or x(i) = 'U') then
tmp(i):= '0';
else
tmp(i):=x(i);
end if;
end loop;
return tmp;
for i in 0 to x'length-1 loop
if(x(i) = 'X' or x(i) = 'U') then
tmp(i):= '0';
else
tmp(i):=x(i);
end if;
end loop;
return tmp;
end function;
function "or" (left, right: t_fd_channel_in_registers) return t_fd_channel_in_registers is
variable tmp: t_fd_channel_in_registers;
variable tmp: t_fd_channel_in_registers;
begin
tmp.dcr_pg_trig_i := f_x_to_zero(left.dcr_pg_trig_i) or f_x_to_zero(right.dcr_pg_trig_i);
tmp.dcr_upd_done_i := f_x_to_zero(left.dcr_upd_done_i) or f_x_to_zero(right.dcr_upd_done_i);
return tmp;
tmp.dcr_pg_trig_i := f_x_to_zero(left.dcr_pg_trig_i) or f_x_to_zero(right.dcr_pg_trig_i);
tmp.dcr_upd_done_i := f_x_to_zero(left.dcr_upd_done_i) or f_x_to_zero(right.dcr_upd_done_i);
return tmp;
end function;
end package body;
hdl/rtl/fd_channel_wishbone_slave.vhd
View file @ f6a2b0a9
......@@ -3,7 +3,7 @@
---------------------------------------------------------------------------------------
-- File : fd_channel_wishbone_slave.vhd
-- Author : auto-generated by wbgen2 from fd_channel_wishbone_slave.wb
-- Created : Wed Dec 4 17:20:17 2013
-- Created : Wed Mar 20 23:27:12 2019
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE fd_channel_wishbone_slave.wb
......@@ -18,22 +18,24 @@ use work.fd_channel_wbgen2_pkg.all;
entity fd_channel_wb_slave is
port (
rst_n_i : in std_logic;
clk_sys_i : in std_logic;
wb_adr_i : in std_logic_vector(3 downto 0);
wb_dat_i : in std_logic_vector(31 downto 0);
wb_dat_o : out std_logic_vector(31 downto 0);
wb_cyc_i : in std_logic;
wb_sel_i : in std_logic_vector(3 downto 0);
wb_stb_i : in std_logic;
wb_we_i : in std_logic;
wb_ack_o : out std_logic;
wb_stall_o : out std_logic;
clk_ref_i : in std_logic;
regs_i : in t_fd_channel_in_registers;
regs_o : out t_fd_channel_out_registers
);
port (
rst_n_i : in std_logic;
clk_sys_i : in std_logic;
wb_adr_i : in std_logic_vector(3 downto 0);
wb_dat_i : in std_logic_vector(31 downto 0);
wb_dat_o : out std_logic_vector(31 downto 0);
wb_cyc_i : in std_logic;
wb_sel_i : in std_logic_vector(3 downto 0);
wb_stb_i : in std_logic;
wb_we_i : in std_logic;
wb_ack_o : out std_logic;
wb_err_o : out std_logic;
wb_rty_o : out std_logic;
wb_stall_o : out std_logic;
clk_ref_i : in std_logic;
regs_i : in t_fd_channel_in_registers;
regs_o : out t_fd_channel_out_registers
);
end fd_channel_wb_slave;
architecture syn of fd_channel_wb_slave is
......@@ -94,556 +96,553 @@ signal allones : std_logic_vector(31 downto 0);
signal allzeros : std_logic_vector(31 downto 0);
begin
-- Some internal signals assignments. For (foreseen) compatibility with other bus standards.
wrdata_reg <= wb_dat_i;
bwsel_reg <= wb_sel_i;
rd_int <= wb_cyc_i and (wb_stb_i and (not wb_we_i));
wr_int <= wb_cyc_i and (wb_stb_i and wb_we_i);
allones <= (others => '1');
allzeros <= (others => '0');
-- Some internal signals assignments
wrdata_reg <= wb_dat_i;
--
-- Main register bank access process.
process (clk_sys_i, rst_n_i)
begin
if (rst_n_i = '0') then
ack_sreg <= "0000000000";
ack_in_progress <= '0';
rddata_reg <= "00000000000000000000000000000000";
fd_channel_dcr_enable_int <= '0';
fd_channel_dcr_mode_int <= '0';
fd_channel_dcr_pg_arm_int <= '0';
fd_channel_dcr_pg_arm_int_delay <= '0';
fd_channel_dcr_update_int <= '0';
fd_channel_dcr_update_int_delay <= '0';
fd_channel_dcr_force_dly_int <= '0';
fd_channel_dcr_force_dly_int_delay <= '0';
fd_channel_dcr_no_fine_int <= '0';
fd_channel_dcr_force_hi_int <= '0';
fd_channel_frr_int <= "0000000000";
fd_channel_frr_swb <= '0';
fd_channel_frr_swb_delay <= '0';
fd_channel_u_starth_int <= "00000000";
fd_channel_u_startl_int <= "00000000000000000000000000000000";
fd_channel_c_start_int <= "0000000000000000000000000000";
fd_channel_f_start_int <= "000000000000";
fd_channel_u_endh_int <= "00000000";
fd_channel_u_endl_int <= "00000000000000000000000000000000";
fd_channel_c_end_int <= "0000000000000000000000000000";
fd_channel_f_end_int <= "000000000000";
fd_channel_u_delta_int <= "0000";
fd_channel_c_delta_int <= "0000000000000000000000000000";
fd_channel_f_delta_int <= "000000000000";
fd_channel_rcr_rep_cnt_int <= "0000000000000000";
fd_channel_rcr_cont_int <= '0';
elsif rising_edge(clk_sys_i) then
process (clk_sys_i, rst_n_i)
begin
if (rst_n_i = '0') then
ack_sreg <= "0000000000";
ack_in_progress <= '0';
rddata_reg <= "00000000000000000000000000000000";
fd_channel_dcr_enable_int <= '0';
fd_channel_dcr_mode_int <= '0';
fd_channel_dcr_pg_arm_int <= '0';
fd_channel_dcr_pg_arm_int_delay <= '0';
fd_channel_dcr_update_int <= '0';
fd_channel_dcr_update_int_delay <= '0';
fd_channel_dcr_force_dly_int <= '0';
fd_channel_dcr_force_dly_int_delay <= '0';
fd_channel_dcr_no_fine_int <= '0';
fd_channel_dcr_force_hi_int <= '0';
fd_channel_frr_int <= "0000000000";
fd_channel_frr_swb <= '0';
fd_channel_frr_swb_delay <= '0';
fd_channel_u_starth_int <= "00000000";
fd_channel_u_startl_int <= "00000000000000000000000000000000";
fd_channel_c_start_int <= "0000000000000000000000000000";
fd_channel_f_start_int <= "000000000000";
fd_channel_u_endh_int <= "00000000";
fd_channel_u_endl_int <= "00000000000000000000000000000000";
fd_channel_c_end_int <= "0000000000000000000000000000";
fd_channel_f_end_int <= "000000000000";
fd_channel_u_delta_int <= "0000";
fd_channel_c_delta_int <= "0000000000000000000000000000";
fd_channel_f_delta_int <= "000000000000";
fd_channel_rcr_rep_cnt_int <= "0000000000000000";
fd_channel_rcr_cont_int <= '0';
elsif rising_edge(clk_sys_i) then
-- advance the ACK generator shift register
ack_sreg(8 downto 0) <= ack_sreg(9 downto 1);
ack_sreg(9) <= '0';
if (ack_in_progress = '1') then
if (ack_sreg(0) = '1') then
ack_in_progress <= '0';
else
fd_channel_dcr_pg_arm_int <= fd_channel_dcr_pg_arm_int_delay;
fd_channel_dcr_pg_arm_int_delay <= '0';
fd_channel_dcr_update_int <= fd_channel_dcr_update_int_delay;
fd_channel_dcr_update_int_delay <= '0';
fd_channel_dcr_force_dly_int <= fd_channel_dcr_force_dly_int_delay;
fd_channel_dcr_force_dly_int_delay <= '0';
fd_channel_frr_swb <= fd_channel_frr_swb_delay;
fd_channel_frr_swb_delay <= '0';
end if;
ack_sreg(8 downto 0) <= ack_sreg(9 downto 1);
ack_sreg(9) <= '0';
if (ack_in_progress = '1') then
if (ack_sreg(0) = '1') then
ack_in_progress <= '0';
else
if ((wb_cyc_i = '1') and (wb_stb_i = '1')) then
case rwaddr_reg(3 downto 0) is
when "0000" =>
if (wb_we_i = '1') then
fd_channel_dcr_enable_int <= wrdata_reg(0);
fd_channel_dcr_mode_int <= wrdata_reg(1);
fd_channel_dcr_pg_arm_int <= wrdata_reg(2);
fd_channel_dcr_pg_arm_int_delay <= wrdata_reg(2);
fd_channel_dcr_update_int <= wrdata_reg(4);
fd_channel_dcr_update_int_delay <= wrdata_reg(4);
fd_channel_dcr_force_dly_int <= wrdata_reg(6);
fd_channel_dcr_force_dly_int_delay <= wrdata_reg(6);
fd_channel_dcr_no_fine_int <= wrdata_reg(7);
fd_channel_dcr_force_hi_int <= wrdata_reg(8);
end if;
rddata_reg(0) <= fd_channel_dcr_enable_int;
rddata_reg(1) <= fd_channel_dcr_mode_int;
rddata_reg(2) <= '0';
rddata_reg(3) <= fd_channel_dcr_pg_trig_sync1;
rddata_reg(4) <= '0';
rddata_reg(5) <= fd_channel_dcr_upd_done_sync1;
rddata_reg(6) <= '0';
rddata_reg(7) <= fd_channel_dcr_no_fine_int;
rddata_reg(8) <= fd_channel_dcr_force_hi_int;
rddata_reg(9) <= 'X';
rddata_reg(10) <= 'X';
rddata_reg(11) <= 'X';
rddata_reg(12) <= 'X';
rddata_reg(13) <= 'X';
rddata_reg(14) <= 'X';
rddata_reg(15) <= 'X';
rddata_reg(16) <= 'X';
rddata_reg(17) <= 'X';
rddata_reg(18) <= 'X';
rddata_reg(19) <= 'X';
rddata_reg(20) <= 'X';
rddata_reg(21) <= 'X';
rddata_reg(22) <= 'X';
rddata_reg(23) <= 'X';
rddata_reg(24) <= 'X';
rddata_reg(25) <= 'X';
rddata_reg(26) <= 'X';
rddata_reg(27) <= 'X';
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
ack_sreg(4) <= '1';
ack_in_progress <= '1';
when "0001" =>
if (wb_we_i = '1') then
fd_channel_frr_int <= wrdata_reg(9 downto 0);
fd_channel_frr_swb <= '1';
fd_channel_frr_swb_delay <= '1';
end if;
rddata_reg(9 downto 0) <= fd_channel_frr_int;
rddata_reg(10) <= 'X';
rddata_reg(11) <= 'X';
rddata_reg(12) <= 'X';
rddata_reg(13) <= 'X';
rddata_reg(14) <= 'X';
rddata_reg(15) <= 'X';
rddata_reg(16) <= 'X';
rddata_reg(17) <= 'X';
rddata_reg(18) <= 'X';
rddata_reg(19) <= 'X';
rddata_reg(20) <= 'X';
rddata_reg(21) <= 'X';
rddata_reg(22) <= 'X';
rddata_reg(23) <= 'X';
rddata_reg(24) <= 'X';
rddata_reg(25) <= 'X';
rddata_reg(26) <= 'X';
rddata_reg(27) <= 'X';
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
ack_sreg(3) <= '1';
ack_in_progress <= '1';
when "0010" =>
if (wb_we_i = '1') then
fd_channel_u_starth_int <= wrdata_reg(7 downto 0);
end if;
rddata_reg(7 downto 0) <= fd_channel_u_starth_int;
rddata_reg(8) <= 'X';
rddata_reg(9) <= 'X';
rddata_reg(10) <= 'X';
rddata_reg(11) <= 'X';
rddata_reg(12) <= 'X';
rddata_reg(13) <= 'X';
rddata_reg(14) <= 'X';
rddata_reg(15) <= 'X';
rddata_reg(16) <= 'X';
rddata_reg(17) <= 'X';
rddata_reg(18) <= 'X';
rddata_reg(19) <= 'X';
rddata_reg(20) <= 'X';
rddata_reg(21) <= 'X';
rddata_reg(22) <= 'X';
rddata_reg(23) <= 'X';
rddata_reg(24) <= 'X';
rddata_reg(25) <= 'X';
rddata_reg(26) <= 'X';
rddata_reg(27) <= 'X';
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "0011" =>
if (wb_we_i = '1') then
fd_channel_u_startl_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= fd_channel_u_startl_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "0100" =>
if (wb_we_i = '1') then
fd_channel_c_start_int <= wrdata_reg(27 downto 0);
end if;
rddata_reg(27 downto 0) <= fd_channel_c_start_int;
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "0101" =>
if (wb_we_i = '1') then
fd_channel_f_start_int <= wrdata_reg(11 downto 0);
end if;
rddata_reg(11 downto 0) <= fd_channel_f_start_int;
rddata_reg(12) <= 'X';
rddata_reg(13) <= 'X';
rddata_reg(14) <= 'X';
rddata_reg(15) <= 'X';
rddata_reg(16) <= 'X';
rddata_reg(17) <= 'X';
rddata_reg(18) <= 'X';
rddata_reg(19) <= 'X';
rddata_reg(20) <= 'X';
rddata_reg(21) <= 'X';
rddata_reg(22) <= 'X';
rddata_reg(23) <= 'X';
rddata_reg(24) <= 'X';
rddata_reg(25) <= 'X';
rddata_reg(26) <= 'X';
rddata_reg(27) <= 'X';
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "0110" =>
if (wb_we_i = '1') then
fd_channel_u_endh_int <= wrdata_reg(7 downto 0);
end if;
rddata_reg(7 downto 0) <= fd_channel_u_endh_int;
rddata_reg(8) <= 'X';
rddata_reg(9) <= 'X';
rddata_reg(10) <= 'X';
rddata_reg(11) <= 'X';
rddata_reg(12) <= 'X';
rddata_reg(13) <= 'X';
rddata_reg(14) <= 'X';
rddata_reg(15) <= 'X';
rddata_reg(16) <= 'X';
rddata_reg(17) <= 'X';
rddata_reg(18) <= 'X';
rddata_reg(19) <= 'X';
rddata_reg(20) <= 'X';
rddata_reg(21) <= 'X';
rddata_reg(22) <= 'X';
rddata_reg(23) <= 'X';
rddata_reg(24) <= 'X';
rddata_reg(25) <= 'X';
rddata_reg(26) <= 'X';
rddata_reg(27) <= 'X';
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "0111" =>
if (wb_we_i = '1') then
fd_channel_u_endl_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= fd_channel_u_endl_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "1000" =>
if (wb_we_i = '1') then
fd_channel_c_end_int <= wrdata_reg(27 downto 0);
end if;
rddata_reg(27 downto 0) <= fd_channel_c_end_int;
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "1001" =>
if (wb_we_i = '1') then
fd_channel_f_end_int <= wrdata_reg(11 downto 0);
end if;
rddata_reg(11 downto 0) <= fd_channel_f_end_int;
rddata_reg(12) <= 'X';
rddata_reg(13) <= 'X';
rddata_reg(14) <= 'X';
rddata_reg(15) <= 'X';
rddata_reg(16) <= 'X';
rddata_reg(17) <= 'X';
rddata_reg(18) <= 'X';
rddata_reg(19) <= 'X';
rddata_reg(20) <= 'X';
rddata_reg(21) <= 'X';
rddata_reg(22) <= 'X';
rddata_reg(23) <= 'X';
rddata_reg(24) <= 'X';
rddata_reg(25) <= 'X';
rddata_reg(26) <= 'X';
rddata_reg(27) <= 'X';
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "1010" =>
if (wb_we_i = '1') then
fd_channel_u_delta_int <= wrdata_reg(3 downto 0);
end if;
rddata_reg(3 downto 0) <= fd_channel_u_delta_int;
rddata_reg(4) <= 'X';
rddata_reg(5) <= 'X';
rddata_reg(6) <= 'X';
rddata_reg(7) <= 'X';
rddata_reg(8) <= 'X';
rddata_reg(9) <= 'X';
rddata_reg(10) <= 'X';
rddata_reg(11) <= 'X';
rddata_reg(12) <= 'X';
rddata_reg(13) <= 'X';
rddata_reg(14) <= 'X';
rddata_reg(15) <= 'X';
rddata_reg(16) <= 'X';
rddata_reg(17) <= 'X';
rddata_reg(18) <= 'X';
rddata_reg(19) <= 'X';
rddata_reg(20) <= 'X';
rddata_reg(21) <= 'X';
rddata_reg(22) <= 'X';
rddata_reg(23) <= 'X';
rddata_reg(24) <= 'X';
rddata_reg(25) <= 'X';
rddata_reg(26) <= 'X';
rddata_reg(27) <= 'X';
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "1011" =>
if (wb_we_i = '1') then
fd_channel_c_delta_int <= wrdata_reg(27 downto 0);
end if;
rddata_reg(27 downto 0) <= fd_channel_c_delta_int;
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "1100" =>
if (wb_we_i = '1') then
fd_channel_f_delta_int <= wrdata_reg(11 downto 0);
end if;
rddata_reg(11 downto 0) <= fd_channel_f_delta_int;
rddata_reg(12) <= 'X';
rddata_reg(13) <= 'X';
rddata_reg(14) <= 'X';
rddata_reg(15) <= 'X';
rddata_reg(16) <= 'X';
rddata_reg(17) <= 'X';
rddata_reg(18) <= 'X';
rddata_reg(19) <= 'X';
rddata_reg(20) <= 'X';
rddata_reg(21) <= 'X';
rddata_reg(22) <= 'X';
rddata_reg(23) <= 'X';
rddata_reg(24) <= 'X';
rddata_reg(25) <= 'X';
rddata_reg(26) <= 'X';
rddata_reg(27) <= 'X';
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "1101" =>
if (wb_we_i = '1') then
fd_channel_rcr_rep_cnt_int <= wrdata_reg(15 downto 0);
fd_channel_rcr_cont_int <= wrdata_reg(16);
end if;
rddata_reg(15 downto 0) <= fd_channel_rcr_rep_cnt_int;
rddata_reg(16) <= fd_channel_rcr_cont_int;
rddata_reg(17) <= 'X';
rddata_reg(18) <= 'X';
rddata_reg(19) <= 'X';
rddata_reg(20) <= 'X';
rddata_reg(21) <= 'X';
rddata_reg(22) <= 'X';
rddata_reg(23) <= 'X';
rddata_reg(24) <= 'X';
rddata_reg(25) <= 'X';
rddata_reg(26) <= 'X';
rddata_reg(27) <= 'X';
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when others =>
fd_channel_dcr_pg_arm_int <= fd_channel_dcr_pg_arm_int_delay;
fd_channel_dcr_pg_arm_int_delay <= '0';
fd_channel_dcr_update_int <= fd_channel_dcr_update_int_delay;
fd_channel_dcr_update_int_delay <= '0';
fd_channel_dcr_force_dly_int <= fd_channel_dcr_force_dly_int_delay;
fd_channel_dcr_force_dly_int_delay <= '0';
fd_channel_frr_swb <= fd_channel_frr_swb_delay;
fd_channel_frr_swb_delay <= '0';
end if;
else
if ((wb_cyc_i = '1') and (wb_stb_i = '1')) then
case rwaddr_reg(3 downto 0) is
when "0000" =>
if (wb_we_i = '1') then
fd_channel_dcr_enable_int <= wrdata_reg(0);
fd_channel_dcr_mode_int <= wrdata_reg(1);
fd_channel_dcr_pg_arm_int <= wrdata_reg(2);
fd_channel_dcr_pg_arm_int_delay <= wrdata_reg(2);
fd_channel_dcr_update_int <= wrdata_reg(4);
fd_channel_dcr_update_int_delay <= wrdata_reg(4);
fd_channel_dcr_force_dly_int <= wrdata_reg(6);
fd_channel_dcr_force_dly_int_delay <= wrdata_reg(6);
fd_channel_dcr_no_fine_int <= wrdata_reg(7);
fd_channel_dcr_force_hi_int <= wrdata_reg(8);
end if;
rddata_reg(0) <= fd_channel_dcr_enable_int;
rddata_reg(1) <= fd_channel_dcr_mode_int;
rddata_reg(2) <= '0';
rddata_reg(3) <= fd_channel_dcr_pg_trig_sync1;
rddata_reg(4) <= '0';
rddata_reg(5) <= fd_channel_dcr_upd_done_sync1;
rddata_reg(6) <= '0';
rddata_reg(7) <= fd_channel_dcr_no_fine_int;
rddata_reg(8) <= fd_channel_dcr_force_hi_int;
rddata_reg(9) <= 'X';
rddata_reg(10) <= 'X';
rddata_reg(11) <= 'X';
rddata_reg(12) <= 'X';
rddata_reg(13) <= 'X';
rddata_reg(14) <= 'X';
rddata_reg(15) <= 'X';
rddata_reg(16) <= 'X';
rddata_reg(17) <= 'X';
rddata_reg(18) <= 'X';
rddata_reg(19) <= 'X';
rddata_reg(20) <= 'X';
rddata_reg(21) <= 'X';
rddata_reg(22) <= 'X';
rddata_reg(23) <= 'X';
rddata_reg(24) <= 'X';
rddata_reg(25) <= 'X';
rddata_reg(26) <= 'X';
rddata_reg(27) <= 'X';
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
ack_sreg(4) <= '1';
ack_in_progress <= '1';
when "0001" =>
if (wb_we_i = '1') then
fd_channel_frr_int <= wrdata_reg(9 downto 0);
fd_channel_frr_swb <= '1';
fd_channel_frr_swb_delay <= '1';
end if;
rddata_reg(9 downto 0) <= fd_channel_frr_int;
rddata_reg(10) <= 'X';
rddata_reg(11) <= 'X';
rddata_reg(12) <= 'X';
rddata_reg(13) <= 'X';
rddata_reg(14) <= 'X';
rddata_reg(15) <= 'X';
rddata_reg(16) <= 'X';
rddata_reg(17) <= 'X';
rddata_reg(18) <= 'X';
rddata_reg(19) <= 'X';
rddata_reg(20) <= 'X';
rddata_reg(21) <= 'X';
rddata_reg(22) <= 'X';
rddata_reg(23) <= 'X';
rddata_reg(24) <= 'X';
rddata_reg(25) <= 'X';
rddata_reg(26) <= 'X';
rddata_reg(27) <= 'X';
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
ack_sreg(3) <= '1';
ack_in_progress <= '1';
when "0010" =>
if (wb_we_i = '1') then
fd_channel_u_starth_int <= wrdata_reg(7 downto 0);
end if;
rddata_reg(7 downto 0) <= fd_channel_u_starth_int;
rddata_reg(8) <= 'X';
rddata_reg(9) <= 'X';
rddata_reg(10) <= 'X';
rddata_reg(11) <= 'X';
rddata_reg(12) <= 'X';
rddata_reg(13) <= 'X';
rddata_reg(14) <= 'X';
rddata_reg(15) <= 'X';
rddata_reg(16) <= 'X';
rddata_reg(17) <= 'X';
rddata_reg(18) <= 'X';
rddata_reg(19) <= 'X';
rddata_reg(20) <= 'X';
rddata_reg(21) <= 'X';
rddata_reg(22) <= 'X';
rddata_reg(23) <= 'X';
rddata_reg(24) <= 'X';
rddata_reg(25) <= 'X';
rddata_reg(26) <= 'X';
rddata_reg(27) <= 'X';
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "0011" =>
if (wb_we_i = '1') then
fd_channel_u_startl_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= fd_channel_u_startl_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "0100" =>
if (wb_we_i = '1') then
fd_channel_c_start_int <= wrdata_reg(27 downto 0);
end if;
rddata_reg(27 downto 0) <= fd_channel_c_start_int;
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "0101" =>
if (wb_we_i = '1') then
fd_channel_f_start_int <= wrdata_reg(11 downto 0);
end if;
rddata_reg(11 downto 0) <= fd_channel_f_start_int;
rddata_reg(12) <= 'X';
rddata_reg(13) <= 'X';
rddata_reg(14) <= 'X';
rddata_reg(15) <= 'X';
rddata_reg(16) <= 'X';
rddata_reg(17) <= 'X';
rddata_reg(18) <= 'X';
rddata_reg(19) <= 'X';
rddata_reg(20) <= 'X';
rddata_reg(21) <= 'X';
rddata_reg(22) <= 'X';
rddata_reg(23) <= 'X';
rddata_reg(24) <= 'X';
rddata_reg(25) <= 'X';
rddata_reg(26) <= 'X';
rddata_reg(27) <= 'X';
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "0110" =>
if (wb_we_i = '1') then
fd_channel_u_endh_int <= wrdata_reg(7 downto 0);
end if;
rddata_reg(7 downto 0) <= fd_channel_u_endh_int;
rddata_reg(8) <= 'X';
rddata_reg(9) <= 'X';
rddata_reg(10) <= 'X';
rddata_reg(11) <= 'X';
rddata_reg(12) <= 'X';
rddata_reg(13) <= 'X';
rddata_reg(14) <= 'X';
rddata_reg(15) <= 'X';
rddata_reg(16) <= 'X';
rddata_reg(17) <= 'X';
rddata_reg(18) <= 'X';
rddata_reg(19) <= 'X';
rddata_reg(20) <= 'X';
rddata_reg(21) <= 'X';
rddata_reg(22) <= 'X';
rddata_reg(23) <= 'X';
rddata_reg(24) <= 'X';
rddata_reg(25) <= 'X';
rddata_reg(26) <= 'X';
rddata_reg(27) <= 'X';
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "0111" =>
if (wb_we_i = '1') then
fd_channel_u_endl_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= fd_channel_u_endl_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "1000" =>
if (wb_we_i = '1') then
fd_channel_c_end_int <= wrdata_reg(27 downto 0);
end if;
rddata_reg(27 downto 0) <= fd_channel_c_end_int;
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "1001" =>
if (wb_we_i = '1') then
fd_channel_f_end_int <= wrdata_reg(11 downto 0);
end if;
rddata_reg(11 downto 0) <= fd_channel_f_end_int;
rddata_reg(12) <= 'X';
rddata_reg(13) <= 'X';
rddata_reg(14) <= 'X';
rddata_reg(15) <= 'X';
rddata_reg(16) <= 'X';
rddata_reg(17) <= 'X';
rddata_reg(18) <= 'X';
rddata_reg(19) <= 'X';
rddata_reg(20) <= 'X';
rddata_reg(21) <= 'X';
rddata_reg(22) <= 'X';
rddata_reg(23) <= 'X';
rddata_reg(24) <= 'X';
rddata_reg(25) <= 'X';
rddata_reg(26) <= 'X';
rddata_reg(27) <= 'X';
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "1010" =>
if (wb_we_i = '1') then
fd_channel_u_delta_int <= wrdata_reg(3 downto 0);
end if;
rddata_reg(3 downto 0) <= fd_channel_u_delta_int;
rddata_reg(4) <= 'X';
rddata_reg(5) <= 'X';
rddata_reg(6) <= 'X';
rddata_reg(7) <= 'X';
rddata_reg(8) <= 'X';
rddata_reg(9) <= 'X';
rddata_reg(10) <= 'X';
rddata_reg(11) <= 'X';
rddata_reg(12) <= 'X';
rddata_reg(13) <= 'X';
rddata_reg(14) <= 'X';
rddata_reg(15) <= 'X';
rddata_reg(16) <= 'X';
rddata_reg(17) <= 'X';
rddata_reg(18) <= 'X';
rddata_reg(19) <= 'X';
rddata_reg(20) <= 'X';
rddata_reg(21) <= 'X';
rddata_reg(22) <= 'X';
rddata_reg(23) <= 'X';
rddata_reg(24) <= 'X';
rddata_reg(25) <= 'X';
rddata_reg(26) <= 'X';
rddata_reg(27) <= 'X';
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "1011" =>
if (wb_we_i = '1') then
fd_channel_c_delta_int <= wrdata_reg(27 downto 0);
end if;
rddata_reg(27 downto 0) <= fd_channel_c_delta_int;
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "1100" =>
if (wb_we_i = '1') then
fd_channel_f_delta_int <= wrdata_reg(11 downto 0);
end if;
rddata_reg(11 downto 0) <= fd_channel_f_delta_int;
rddata_reg(12) <= 'X';
rddata_reg(13) <= 'X';
rddata_reg(14) <= 'X';
rddata_reg(15) <= 'X';
rddata_reg(16) <= 'X';
rddata_reg(17) <= 'X';
rddata_reg(18) <= 'X';
rddata_reg(19) <= 'X';
rddata_reg(20) <= 'X';
rddata_reg(21) <= 'X';
rddata_reg(22) <= 'X';
rddata_reg(23) <= 'X';
rddata_reg(24) <= 'X';
rddata_reg(25) <= 'X';
rddata_reg(26) <= 'X';
rddata_reg(27) <= 'X';
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "1101" =>
if (wb_we_i = '1') then
fd_channel_rcr_rep_cnt_int <= wrdata_reg(15 downto 0);
fd_channel_rcr_cont_int <= wrdata_reg(16);
end if;
rddata_reg(15 downto 0) <= fd_channel_rcr_rep_cnt_int;
rddata_reg(16) <= fd_channel_rcr_cont_int;
rddata_reg(17) <= 'X';
rddata_reg(18) <= 'X';
rddata_reg(19) <= 'X';
rddata_reg(20) <= 'X';
rddata_reg(21) <= 'X';
rddata_reg(22) <= 'X';
rddata_reg(23) <= 'X';
rddata_reg(24) <= 'X';
rddata_reg(25) <= 'X';
rddata_reg(26) <= 'X';
rddata_reg(27) <= 'X';
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when others =>
-- prevent the slave from hanging the bus on invalid address
ack_in_progress <= '1';
ack_sreg(0) <= '1';
end case;
end if;
ack_in_progress <= '1';
ack_sreg(0) <= '1';
end case;
end if;
end if;
end process;
end if;
end process;
-- Drive the data output bus
wb_dat_o <= rddata_reg;
wb_dat_o <= rddata_reg;
-- Enable channel
-- synchronizer chain for field : Enable channel (type RW/RO, clk_sys_i <-> clk_ref_i)
process (clk_ref_i, rst_n_i)
begin
if (rst_n_i = '0') then
regs_o.dcr_enable_o <= '0';
fd_channel_dcr_enable_sync0 <= '0';
fd_channel_dcr_enable_sync1 <= '0';
elsif rising_edge(clk_ref_i) then
fd_channel_dcr_enable_sync0 <= fd_channel_dcr_enable_int;
fd_channel_dcr_enable_sync1 <= fd_channel_dcr_enable_sync0;
regs_o.dcr_enable_o <= fd_channel_dcr_enable_sync1;
end if;
end process;
process (clk_ref_i, rst_n_i)
begin
if (rst_n_i = '0') then
regs_o.dcr_enable_o <= '0';
fd_channel_dcr_enable_sync0 <= '0';
fd_channel_dcr_enable_sync1 <= '0';
elsif rising_edge(clk_ref_i) then
fd_channel_dcr_enable_sync0 <= fd_channel_dcr_enable_int;
fd_channel_dcr_enable_sync1 <= fd_channel_dcr_enable_sync0;
regs_o.dcr_enable_o <= fd_channel_dcr_enable_sync1;
end if;
end process;
-- Delay mode select
regs_o.dcr_mode_o <= fd_channel_dcr_mode_int;
regs_o.dcr_mode_o <= fd_channel_dcr_mode_int;
-- Pulse generator arm
process (clk_ref_i, rst_n_i)
begin
if (rst_n_i = '0') then
regs_o.dcr_pg_arm_o <= '0';
fd_channel_dcr_pg_arm_sync0 <= '0';
fd_channel_dcr_pg_arm_sync1 <= '0';
fd_channel_dcr_pg_arm_sync2 <= '0';
elsif rising_edge(clk_ref_i) then
fd_channel_dcr_pg_arm_sync0 <= fd_channel_dcr_pg_arm_int;
fd_channel_dcr_pg_arm_sync1 <= fd_channel_dcr_pg_arm_sync0;
fd_channel_dcr_pg_arm_sync2 <= fd_channel_dcr_pg_arm_sync1;
regs_o.dcr_pg_arm_o <= fd_channel_dcr_pg_arm_sync2 and (not fd_channel_dcr_pg_arm_sync1);
end if;
end process;
process (clk_ref_i, rst_n_i)
begin
if (rst_n_i = '0') then
regs_o.dcr_pg_arm_o <= '0';
fd_channel_dcr_pg_arm_sync0 <= '0';
fd_channel_dcr_pg_arm_sync1 <= '0';
fd_channel_dcr_pg_arm_sync2 <= '0';
elsif rising_edge(clk_ref_i) then
fd_channel_dcr_pg_arm_sync0 <= fd_channel_dcr_pg_arm_int;
fd_channel_dcr_pg_arm_sync1 <= fd_channel_dcr_pg_arm_sync0;
fd_channel_dcr_pg_arm_sync2 <= fd_channel_dcr_pg_arm_sync1;
regs_o.dcr_pg_arm_o <= fd_channel_dcr_pg_arm_sync2 and (not fd_channel_dcr_pg_arm_sync1);
end if;
end process;
-- Pulse generator triggered
-- synchronizer chain for field : Pulse generator triggered (type RO/WO, clk_ref_i -> clk_sys_i)
process (clk_ref_i, rst_n_i)
begin
if (rst_n_i = '0') then
fd_channel_dcr_pg_trig_sync0 <= '0';
fd_channel_dcr_pg_trig_sync1 <= '0';
elsif rising_edge(clk_ref_i) then
fd_channel_dcr_pg_trig_sync0 <= regs_i.dcr_pg_trig_i;
fd_channel_dcr_pg_trig_sync1 <= fd_channel_dcr_pg_trig_sync0;
end if;
end process;
process (clk_ref_i, rst_n_i)
begin
if (rst_n_i = '0') then
fd_channel_dcr_pg_trig_sync0 <= '0';
fd_channel_dcr_pg_trig_sync1 <= '0';
elsif rising_edge(clk_ref_i) then
fd_channel_dcr_pg_trig_sync0 <= regs_i.dcr_pg_trig_i;
fd_channel_dcr_pg_trig_sync1 <= fd_channel_dcr_pg_trig_sync0;
end if;
end process;
-- Update delay/absolute trigger time
process (clk_ref_i, rst_n_i)
begin
if (rst_n_i = '0') then
regs_o.dcr_update_o <= '0';
fd_channel_dcr_update_sync0 <= '0';
fd_channel_dcr_update_sync1 <= '0';
fd_channel_dcr_update_sync2 <= '0';
elsif rising_edge(clk_ref_i) then
fd_channel_dcr_update_sync0 <= fd_channel_dcr_update_int;
fd_channel_dcr_update_sync1 <= fd_channel_dcr_update_sync0;
fd_channel_dcr_update_sync2 <= fd_channel_dcr_update_sync1;
regs_o.dcr_update_o <= fd_channel_dcr_update_sync2 and (not fd_channel_dcr_update_sync1);
end if;
end process;
process (clk_ref_i, rst_n_i)
begin
if (rst_n_i = '0') then
regs_o.dcr_update_o <= '0';
fd_channel_dcr_update_sync0 <= '0';
fd_channel_dcr_update_sync1 <= '0';
fd_channel_dcr_update_sync2 <= '0';
elsif rising_edge(clk_ref_i) then
fd_channel_dcr_update_sync0 <= fd_channel_dcr_update_int;
fd_channel_dcr_update_sync1 <= fd_channel_dcr_update_sync0;
fd_channel_dcr_update_sync2 <= fd_channel_dcr_update_sync1;
regs_o.dcr_update_o <= fd_channel_dcr_update_sync2 and (not fd_channel_dcr_update_sync1);
end if;
end process;
-- Delay update done flag
-- synchronizer chain for field : Delay update done flag (type RO/WO, clk_ref_i -> clk_sys_i)
process (clk_ref_i, rst_n_i)
begin
if (rst_n_i = '0') then
fd_channel_dcr_upd_done_sync0 <= '0';
fd_channel_dcr_upd_done_sync1 <= '0';
elsif rising_edge(clk_ref_i) then
fd_channel_dcr_upd_done_sync0 <= regs_i.dcr_upd_done_i;
fd_channel_dcr_upd_done_sync1 <= fd_channel_dcr_upd_done_sync0;
end if;
end process;
process (clk_ref_i, rst_n_i)
begin
if (rst_n_i = '0') then
fd_channel_dcr_upd_done_sync0 <= '0';
fd_channel_dcr_upd_done_sync1 <= '0';
elsif rising_edge(clk_ref_i) then
fd_channel_dcr_upd_done_sync0 <= regs_i.dcr_upd_done_i;
fd_channel_dcr_upd_done_sync1 <= fd_channel_dcr_upd_done_sync0;
end if;
end process;
-- Force calibration delay
process (clk_ref_i, rst_n_i)
begin
if (rst_n_i = '0') then
regs_o.dcr_force_dly_o <= '0';
fd_channel_dcr_force_dly_sync0 <= '0';
fd_channel_dcr_force_dly_sync1 <= '0';
fd_channel_dcr_force_dly_sync2 <= '0';
elsif rising_edge(clk_ref_i) then
fd_channel_dcr_force_dly_sync0 <= fd_channel_dcr_force_dly_int;
fd_channel_dcr_force_dly_sync1 <= fd_channel_dcr_force_dly_sync0;
fd_channel_dcr_force_dly_sync2 <= fd_channel_dcr_force_dly_sync1;
regs_o.dcr_force_dly_o <= fd_channel_dcr_force_dly_sync2 and (not fd_channel_dcr_force_dly_sync1);
end if;
end process;
process (clk_ref_i, rst_n_i)
begin
if (rst_n_i = '0') then
regs_o.dcr_force_dly_o <= '0';
fd_channel_dcr_force_dly_sync0 <= '0';
fd_channel_dcr_force_dly_sync1 <= '0';
fd_channel_dcr_force_dly_sync2 <= '0';
elsif rising_edge(clk_ref_i) then
fd_channel_dcr_force_dly_sync0 <= fd_channel_dcr_force_dly_int;
fd_channel_dcr_force_dly_sync1 <= fd_channel_dcr_force_dly_sync0;
fd_channel_dcr_force_dly_sync2 <= fd_channel_dcr_force_dly_sync1;
regs_o.dcr_force_dly_o <= fd_channel_dcr_force_dly_sync2 and (not fd_channel_dcr_force_dly_sync1);
end if;
end process;
-- Disable fine part update
regs_o.dcr_no_fine_o <= fd_channel_dcr_no_fine_int;
regs_o.dcr_no_fine_o <= fd_channel_dcr_no_fine_int;
-- Force output high
regs_o.dcr_force_hi_o <= fd_channel_dcr_force_hi_int;
regs_o.dcr_force_hi_o <= fd_channel_dcr_force_hi_int;
-- Fine range in SY89825 taps.
-- asynchronous std_logic_vector register : Fine range in SY89825 taps. (type RW/RO, clk_ref_i <-> clk_sys_i)
process (clk_ref_i, rst_n_i)
begin
if (rst_n_i = '0') then
fd_channel_frr_swb_s0 <= '0';
fd_channel_frr_swb_s1 <= '0';
fd_channel_frr_swb_s2 <= '0';
regs_o.frr_o <= "0000000000";
elsif rising_edge(clk_ref_i) then
fd_channel_frr_swb_s0 <= fd_channel_frr_swb;
fd_channel_frr_swb_s1 <= fd_channel_frr_swb_s0;
fd_channel_frr_swb_s2 <= fd_channel_frr_swb_s1;
if ((fd_channel_frr_swb_s2 = '0') and (fd_channel_frr_swb_s1 = '1')) then
regs_o.frr_o <= fd_channel_frr_int;
end if;
process (clk_ref_i, rst_n_i)
begin
if (rst_n_i = '0') then
fd_channel_frr_swb_s0 <= '0';
fd_channel_frr_swb_s1 <= '0';
fd_channel_frr_swb_s2 <= '0';
regs_o.frr_o <= "0000000000";
elsif rising_edge(clk_ref_i) then
fd_channel_frr_swb_s0 <= fd_channel_frr_swb;
fd_channel_frr_swb_s1 <= fd_channel_frr_swb_s0;
fd_channel_frr_swb_s2 <= fd_channel_frr_swb_s1;
if ((fd_channel_frr_swb_s2 = '0') and (fd_channel_frr_swb_s1 = '1')) then
regs_o.frr_o <= fd_channel_frr_int;
end if;
end process;
end if;
end process;
-- TAI seconds (MSB)
regs_o.u_starth_o <= fd_channel_u_starth_int;
regs_o.u_starth_o <= fd_channel_u_starth_int;
-- TAI seconds (LSB)
regs_o.u_startl_o <= fd_channel_u_startl_int;
regs_o.u_startl_o <= fd_channel_u_startl_int;
-- Reference clock cycles
regs_o.c_start_o <= fd_channel_c_start_int;
regs_o.c_start_o <= fd_channel_c_start_int;
-- Fractional part
regs_o.f_start_o <= fd_channel_f_start_int;
regs_o.f_start_o <= fd_channel_f_start_int;
-- TAI seconds (MSB)
regs_o.u_endh_o <= fd_channel_u_endh_int;
regs_o.u_endh_o <= fd_channel_u_endh_int;
-- TAI seconds (LSB)
regs_o.u_endl_o <= fd_channel_u_endl_int;
regs_o.u_endl_o <= fd_channel_u_endl_int;
-- Reference clock cycles
regs_o.c_end_o <= fd_channel_c_end_int;
regs_o.c_end_o <= fd_channel_c_end_int;
-- Fractional part
regs_o.f_end_o <= fd_channel_f_end_int;
regs_o.f_end_o <= fd_channel_f_end_int;
-- TAI seconds
regs_o.u_delta_o <= fd_channel_u_delta_int;
regs_o.u_delta_o <= fd_channel_u_delta_int;
-- Reference clock cycles
regs_o.c_delta_o <= fd_channel_c_delta_int;
regs_o.c_delta_o <= fd_channel_c_delta_int;
-- Fractional part
regs_o.f_delta_o <= fd_channel_f_delta_int;
regs_o.f_delta_o <= fd_channel_f_delta_int;
-- Repeat Count
regs_o.rcr_rep_cnt_o <= fd_channel_rcr_rep_cnt_int;
regs_o.rcr_rep_cnt_o <= fd_channel_rcr_rep_cnt_int;
-- Continuous Waveform Mode
regs_o.rcr_cont_o <= fd_channel_rcr_cont_int;
rwaddr_reg <= wb_adr_i;
wb_stall_o <= (not ack_sreg(0)) and (wb_stb_i and wb_cyc_i);
regs_o.rcr_cont_o <= fd_channel_rcr_cont_int;
rwaddr_reg <= wb_adr_i;
wb_stall_o <= (not ack_sreg(0)) and (wb_stb_i and wb_cyc_i);
wb_err_o <= '0';
wb_rty_o <= '0';
-- ACK signal generation. Just pass the LSB of ACK counter.
wb_ack_o <= ack_sreg(0);
wb_ack_o <= ack_sreg(0);
end syn;
hdl/rtl/fd_main_wbgen2_pkg.vhd
View file @ f6a2b0a9
......@@ -3,7 +3,7 @@
---------------------------------------------------------------------------------------
-- File : fd_main_wbgen2_pkg.vhd
-- Author : auto-generated by wbgen2 from fd_main_wishbone_slave.wb
-- Created : Wed Dec 4 17:20:16 2013
-- Created : Wed Mar 20 23:27:12 2019
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE fd_main_wishbone_slave.wb
......@@ -56,7 +56,7 @@ package fd_main_wbgen2_pkg is
i2cr_sda_in_i : std_logic;
tder1_vcxo_freq_i : std_logic_vector(31 downto 0);
tsbr_debug_i : std_logic_vector(31 downto 0);
end record;
end record;
constant c_fd_main_in_registers_init_value: t_fd_main_in_registers := (
gcr_ddr_locked_i => '0',
......@@ -94,185 +94,228 @@ package fd_main_wbgen2_pkg is
i2cr_sda_in_i => '0',
tder1_vcxo_freq_i => (others => '0'),
tsbr_debug_i => (others => '0')
);
-- Output registers (WB slave -> user design)
type t_fd_main_out_registers is record
rstr_rst_fmc_o : std_logic;
rstr_rst_fmc_wr_o : std_logic;
rstr_rst_core_o : std_logic;
rstr_rst_core_wr_o : std_logic;
rstr_lock_o : std_logic_vector(15 downto 0);
rstr_lock_wr_o : std_logic;
gcr_bypass_o : std_logic;
gcr_input_en_o : std_logic;
tcr_wr_enable_o : std_logic;
tcr_cap_time_o : std_logic;
tcr_set_time_o : std_logic;
tm_sech_o : std_logic_vector(7 downto 0);
tm_sech_load_o : std_logic;
tm_secl_o : std_logic_vector(31 downto 0);
tm_secl_load_o : std_logic;
tm_cycles_o : std_logic_vector(27 downto 0);
tm_cycles_load_o : std_logic;
tdr_o : std_logic_vector(27 downto 0);
tdr_load_o : std_logic;
tdcsr_write_o : std_logic;
tdcsr_read_o : std_logic;
tdcsr_stop_en_o : std_logic;
tdcsr_start_dis_o : std_logic;
tdcsr_start_en_o : std_logic;
tdcsr_stop_dis_o : std_logic;
tdcsr_alutrig_o : std_logic;
calr_cal_pulse_o : std_logic;
calr_cal_pps_o : std_logic;
calr_cal_dmtd_o : std_logic;
calr_psel_o : std_logic_vector(3 downto 0);
adsfr_o : std_logic_vector(17 downto 0);
atmcr_c_thr_o : std_logic_vector(7 downto 0);
atmcr_f_thr_o : std_logic_vector(22 downto 0);
asor_offset_o : std_logic_vector(22 downto 0);
iepd_rst_stat_o : std_logic;
scr_data_o : std_logic_vector(23 downto 0);
scr_data_load_o : std_logic;
scr_sel_dac_o : std_logic;
scr_sel_pll_o : std_logic;
scr_sel_gpio_o : std_logic;
scr_cpol_o : std_logic;
scr_start_o : std_logic;
tsbcr_chan_mask_o : std_logic_vector(4 downto 0);
tsbcr_enable_o : std_logic;
tsbcr_purge_o : std_logic;
tsbcr_rst_seq_o : std_logic;
tsbcr_raw_o : std_logic;
tsbir_timeout_o : std_logic_vector(9 downto 0);
tsbir_threshold_o : std_logic_vector(11 downto 0);
i2cr_scl_out_o : std_logic;
i2cr_sda_out_o : std_logic;
tder2_pelt_drive_o : std_logic_vector(31 downto 0);
tsbr_advance_adv_o : std_logic;
end record;
constant c_fd_main_out_registers_init_value: t_fd_main_out_registers := (
rstr_rst_fmc_o => '0',
rstr_rst_fmc_wr_o => '0',
rstr_rst_core_o => '0',
rstr_rst_core_wr_o => '0',
rstr_lock_o => (others => '0'),
rstr_lock_wr_o => '0',
gcr_bypass_o => '0',
gcr_input_en_o => '0',
tcr_wr_enable_o => '0',
tcr_cap_time_o => '0',
tcr_set_time_o => '0',
tm_sech_o => (others => '0'),
tm_sech_load_o => '0',
tm_secl_o => (others => '0'),
tm_secl_load_o => '0',
tm_cycles_o => (others => '0'),
tm_cycles_load_o => '0',
tdr_o => (others => '0'),
tdr_load_o => '0',
tdcsr_write_o => '0',
tdcsr_read_o => '0',
tdcsr_stop_en_o => '0',
tdcsr_start_dis_o => '0',
tdcsr_start_en_o => '0',
tdcsr_stop_dis_o => '0',
tdcsr_alutrig_o => '0',
calr_cal_pulse_o => '0',
calr_cal_pps_o => '0',
calr_cal_dmtd_o => '0',
calr_psel_o => (others => '0'),
adsfr_o => (others => '0'),
atmcr_c_thr_o => (others => '0'),
atmcr_f_thr_o => (others => '0'),
asor_offset_o => (others => '0'),
iepd_rst_stat_o => '0',
scr_data_o => (others => '0'),
scr_data_load_o => '0',
scr_sel_dac_o => '0',
scr_sel_pll_o => '0',
scr_sel_gpio_o => '0',
scr_cpol_o => '0',
scr_start_o => '0',
tsbcr_chan_mask_o => (others => '0'),
tsbcr_enable_o => '0',
tsbcr_purge_o => '0',
tsbcr_rst_seq_o => '0',
tsbcr_raw_o => '0',
tsbir_timeout_o => (others => '0'),
tsbir_threshold_o => (others => '0'),
i2cr_scl_out_o => '0',
i2cr_sda_out_o => '0',
tder2_pelt_drive_o => (others => '0'),
tsbr_advance_adv_o => '0'
);
function "or" (left, right: t_fd_main_in_registers) return t_fd_main_in_registers;
function f_x_to_zero (x:std_logic) return std_logic;
function f_x_to_zero (x:std_logic_vector) return std_logic_vector;
);
-- Output registers (WB slave -> user design)
type t_fd_main_out_registers is record
rstr_rst_fmc_o : std_logic;
rstr_rst_fmc_wr_o : std_logic;
rstr_rst_core_o : std_logic;
rstr_rst_core_wr_o : std_logic;
rstr_lock_o : std_logic_vector(15 downto 0);
rstr_lock_wr_o : std_logic;
gcr_bypass_o : std_logic;
gcr_input_en_o : std_logic;
tcr_wr_enable_o : std_logic;
tcr_cap_time_o : std_logic;
tcr_set_time_o : std_logic;
tm_sech_o : std_logic_vector(7 downto 0);
tm_sech_load_o : std_logic;
tm_secl_o : std_logic_vector(31 downto 0);
tm_secl_load_o : std_logic;
tm_cycles_o : std_logic_vector(27 downto 0);
tm_cycles_load_o : std_logic;
tdr_o : std_logic_vector(27 downto 0);
tdr_load_o : std_logic;
tdcsr_write_o : std_logic;
tdcsr_read_o : std_logic;
tdcsr_stop_en_o : std_logic;
tdcsr_start_dis_o : std_logic;
tdcsr_start_en_o : std_logic;
tdcsr_stop_dis_o : std_logic;
tdcsr_alutrig_o : std_logic;
tdcsr_idelay_ce_o : std_logic;
tdcsr_idelay_rst_o : std_logic;
tdcsr_idelay_cal_o : std_logic;
tdcsr_idelay_inc_o : std_logic;
calr_cal_pulse_o : std_logic;
calr_cal_pps_o : std_logic;
calr_cal_dmtd_o : std_logic;
calr_psel_o : std_logic_vector(3 downto 0);
adsfr_o : std_logic_vector(17 downto 0);
atmcr_c_thr_o : std_logic_vector(7 downto 0);
atmcr_f_thr_o : std_logic_vector(22 downto 0);
asor_offset_o : std_logic_vector(22 downto 0);
iepd_rst_stat_o : std_logic;
scr_data_o : std_logic_vector(23 downto 0);
scr_data_load_o : std_logic;
scr_sel_dac_o : std_logic;
scr_sel_pll_o : std_logic;
scr_sel_gpio_o : std_logic;
scr_cpol_o : std_logic;
scr_start_o : std_logic;
tsbcr_chan_mask_o : std_logic_vector(4 downto 0);
tsbcr_enable_o : std_logic;
tsbcr_purge_o : std_logic;
tsbcr_rst_seq_o : std_logic;
tsbcr_raw_o : std_logic;
tsbir_timeout_o : std_logic_vector(9 downto 0);
tsbir_threshold_o : std_logic_vector(11 downto 0);
i2cr_scl_out_o : std_logic;
i2cr_sda_out_o : std_logic;
tder2_pelt_drive_o : std_logic_vector(31 downto 0);
tsbr_advance_adv_o : std_logic;
end record;
constant c_fd_main_out_registers_init_value: t_fd_main_out_registers := (
rstr_rst_fmc_o => '0',
rstr_rst_fmc_wr_o => '0',
rstr_rst_core_o => '0',
rstr_rst_core_wr_o => '0',
rstr_lock_o => (others => '0'),
rstr_lock_wr_o => '0',
gcr_bypass_o => '0',
gcr_input_en_o => '0',
tcr_wr_enable_o => '0',
tcr_cap_time_o => '0',
tcr_set_time_o => '0',
tm_sech_o => (others => '0'),
tm_sech_load_o => '0',
tm_secl_o => (others => '0'),
tm_secl_load_o => '0',
tm_cycles_o => (others => '0'),
tm_cycles_load_o => '0',
tdr_o => (others => '0'),
tdr_load_o => '0',
tdcsr_write_o => '0',
tdcsr_read_o => '0',
tdcsr_stop_en_o => '0',
tdcsr_start_dis_o => '0',
tdcsr_start_en_o => '0',
tdcsr_stop_dis_o => '0',
tdcsr_alutrig_o => '0',
tdcsr_idelay_ce_o => '0',
tdcsr_idelay_rst_o => '0',
tdcsr_idelay_cal_o => '0',
tdcsr_idelay_inc_o => '0',
calr_cal_pulse_o => '0',
calr_cal_pps_o => '0',
calr_cal_dmtd_o => '0',
calr_psel_o => (others => '0'),
adsfr_o => (others => '0'),
atmcr_c_thr_o => (others => '0'),
atmcr_f_thr_o => (others => '0'),
asor_offset_o => (others => '0'),
iepd_rst_stat_o => '0',
scr_data_o => (others => '0'),
scr_data_load_o => '0',
scr_sel_dac_o => '0',
scr_sel_pll_o => '0',
scr_sel_gpio_o => '0',
scr_cpol_o => '0',
scr_start_o => '0',
tsbcr_chan_mask_o => (others => '0'),
tsbcr_enable_o => '0',
tsbcr_purge_o => '0',
tsbcr_rst_seq_o => '0',
tsbcr_raw_o => '0',
tsbir_timeout_o => (others => '0'),
tsbir_threshold_o => (others => '0'),
i2cr_scl_out_o => '0',
i2cr_sda_out_o => '0',
tder2_pelt_drive_o => (others => '0'),
tsbr_advance_adv_o => '0'
);
function "or" (left, right: t_fd_main_in_registers) return t_fd_main_in_registers;
function f_x_to_zero (x:std_logic) return std_logic;
function f_x_to_zero (x:std_logic_vector) return std_logic_vector;
component fd_main_wb_slave is
port (
rst_n_i : in std_logic;
clk_sys_i : in std_logic;
wb_adr_i : in std_logic_vector(5 downto 0);
wb_dat_i : in std_logic_vector(31 downto 0);
wb_dat_o : out std_logic_vector(31 downto 0);
wb_cyc_i : in std_logic;
wb_sel_i : in std_logic_vector(3 downto 0);
wb_stb_i : in std_logic;
wb_we_i : in std_logic;
wb_ack_o : out std_logic;
wb_err_o : out std_logic;
wb_rty_o : out std_logic;
wb_stall_o : out std_logic;
wb_int_o : out std_logic;
clk_ref_i : in std_logic;
tcr_rd_ack_o : out std_logic;
dmtr_in_rd_ack_o : out std_logic;
dmtr_out_rd_ack_o : out std_logic;
tsbcr_read_ack_o : out std_logic;
fid_read_ack_o : out std_logic;
irq_ts_buf_notempty_i : in std_logic;
irq_dmtd_spll_i : in std_logic;
irq_sync_status_i : in std_logic;
regs_i : in t_fd_main_in_registers;
regs_o : out t_fd_main_out_registers
);
end component;
end package;
package body fd_main_wbgen2_pkg is
function f_x_to_zero (x:std_logic) return std_logic is
begin
if x = '1' then
return '1';
else
return '0';
end if;
if x = '1' then
return '1';
else
return '0';
end if;
end function;
function f_x_to_zero (x:std_logic_vector) return std_logic_vector is
variable tmp: std_logic_vector(x'length-1 downto 0);
variable tmp: std_logic_vector(x'length-1 downto 0);
begin
for i in 0 to x'length-1 loop
if(x(i) = 'X' or x(i) = 'U') then
tmp(i):= '0';
else
tmp(i):=x(i);
end if;
end loop;
return tmp;
for i in 0 to x'length-1 loop
if(x(i) = 'X' or x(i) = 'U') then
tmp(i):= '0';
else
tmp(i):=x(i);
end if;
end loop;
return tmp;
end function;
function "or" (left, right: t_fd_main_in_registers) return t_fd_main_in_registers is
variable tmp: t_fd_main_in_registers;
variable tmp: t_fd_main_in_registers;
begin
tmp.gcr_ddr_locked_i := f_x_to_zero(left.gcr_ddr_locked_i) or f_x_to_zero(right.gcr_ddr_locked_i);
tmp.gcr_fmc_present_i := f_x_to_zero(left.gcr_fmc_present_i) or f_x_to_zero(right.gcr_fmc_present_i);
tmp.tcr_dmtd_stat_i := f_x_to_zero(left.tcr_dmtd_stat_i) or f_x_to_zero(right.tcr_dmtd_stat_i);
tmp.tcr_wr_locked_i := f_x_to_zero(left.tcr_wr_locked_i) or f_x_to_zero(right.tcr_wr_locked_i);
tmp.tcr_wr_present_i := f_x_to_zero(left.tcr_wr_present_i) or f_x_to_zero(right.tcr_wr_present_i);
tmp.tcr_wr_ready_i := f_x_to_zero(left.tcr_wr_ready_i) or f_x_to_zero(right.tcr_wr_ready_i);
tmp.tcr_wr_link_i := f_x_to_zero(left.tcr_wr_link_i) or f_x_to_zero(right.tcr_wr_link_i);
tmp.tm_sech_i := f_x_to_zero(left.tm_sech_i) or f_x_to_zero(right.tm_sech_i);
tmp.tm_secl_i := f_x_to_zero(left.tm_secl_i) or f_x_to_zero(right.tm_secl_i);
tmp.tm_cycles_i := f_x_to_zero(left.tm_cycles_i) or f_x_to_zero(right.tm_cycles_i);
tmp.tdr_i := f_x_to_zero(left.tdr_i) or f_x_to_zero(right.tdr_i);
tmp.tdcsr_empty_i := f_x_to_zero(left.tdcsr_empty_i) or f_x_to_zero(right.tdcsr_empty_i);
tmp.dmtr_in_tag_i := f_x_to_zero(left.dmtr_in_tag_i) or f_x_to_zero(right.dmtr_in_tag_i);
tmp.dmtr_in_rdy_i := f_x_to_zero(left.dmtr_in_rdy_i) or f_x_to_zero(right.dmtr_in_rdy_i);
tmp.dmtr_out_tag_i := f_x_to_zero(left.dmtr_out_tag_i) or f_x_to_zero(right.dmtr_out_tag_i);
tmp.dmtr_out_rdy_i := f_x_to_zero(left.dmtr_out_rdy_i) or f_x_to_zero(right.dmtr_out_rdy_i);
tmp.iecraw_i := f_x_to_zero(left.iecraw_i) or f_x_to_zero(right.iecraw_i);
tmp.iectag_i := f_x_to_zero(left.iectag_i) or f_x_to_zero(right.iectag_i);
tmp.iepd_pdelay_i := f_x_to_zero(left.iepd_pdelay_i) or f_x_to_zero(right.iepd_pdelay_i);
tmp.scr_data_i := f_x_to_zero(left.scr_data_i) or f_x_to_zero(right.scr_data_i);
tmp.scr_ready_i := f_x_to_zero(left.scr_ready_i) or f_x_to_zero(right.scr_ready_i);
tmp.rcrr_i := f_x_to_zero(left.rcrr_i) or f_x_to_zero(right.rcrr_i);
tmp.tsbcr_full_i := f_x_to_zero(left.tsbcr_full_i) or f_x_to_zero(right.tsbcr_full_i);
tmp.tsbcr_empty_i := f_x_to_zero(left.tsbcr_empty_i) or f_x_to_zero(right.tsbcr_empty_i);
tmp.tsbcr_count_i := f_x_to_zero(left.tsbcr_count_i) or f_x_to_zero(right.tsbcr_count_i);
tmp.tsbr_sech_i := f_x_to_zero(left.tsbr_sech_i) or f_x_to_zero(right.tsbr_sech_i);
tmp.tsbr_secl_i := f_x_to_zero(left.tsbr_secl_i) or f_x_to_zero(right.tsbr_secl_i);
tmp.tsbr_cycles_i := f_x_to_zero(left.tsbr_cycles_i) or f_x_to_zero(right.tsbr_cycles_i);
tmp.tsbr_fid_channel_i := f_x_to_zero(left.tsbr_fid_channel_i) or f_x_to_zero(right.tsbr_fid_channel_i);
tmp.tsbr_fid_fine_i := f_x_to_zero(left.tsbr_fid_fine_i) or f_x_to_zero(right.tsbr_fid_fine_i);
tmp.tsbr_fid_seqid_i := f_x_to_zero(left.tsbr_fid_seqid_i) or f_x_to_zero(right.tsbr_fid_seqid_i);
tmp.i2cr_scl_in_i := f_x_to_zero(left.i2cr_scl_in_i) or f_x_to_zero(right.i2cr_scl_in_i);
tmp.i2cr_sda_in_i := f_x_to_zero(left.i2cr_sda_in_i) or f_x_to_zero(right.i2cr_sda_in_i);
tmp.tder1_vcxo_freq_i := f_x_to_zero(left.tder1_vcxo_freq_i) or f_x_to_zero(right.tder1_vcxo_freq_i);
tmp.tsbr_debug_i := f_x_to_zero(left.tsbr_debug_i) or f_x_to_zero(right.tsbr_debug_i);
return tmp;
tmp.gcr_ddr_locked_i := f_x_to_zero(left.gcr_ddr_locked_i) or f_x_to_zero(right.gcr_ddr_locked_i);
tmp.gcr_fmc_present_i := f_x_to_zero(left.gcr_fmc_present_i) or f_x_to_zero(right.gcr_fmc_present_i);
tmp.tcr_dmtd_stat_i := f_x_to_zero(left.tcr_dmtd_stat_i) or f_x_to_zero(right.tcr_dmtd_stat_i);
tmp.tcr_wr_locked_i := f_x_to_zero(left.tcr_wr_locked_i) or f_x_to_zero(right.tcr_wr_locked_i);
tmp.tcr_wr_present_i := f_x_to_zero(left.tcr_wr_present_i) or f_x_to_zero(right.tcr_wr_present_i);
tmp.tcr_wr_ready_i := f_x_to_zero(left.tcr_wr_ready_i) or f_x_to_zero(right.tcr_wr_ready_i);
tmp.tcr_wr_link_i := f_x_to_zero(left.tcr_wr_link_i) or f_x_to_zero(right.tcr_wr_link_i);
tmp.tm_sech_i := f_x_to_zero(left.tm_sech_i) or f_x_to_zero(right.tm_sech_i);
tmp.tm_secl_i := f_x_to_zero(left.tm_secl_i) or f_x_to_zero(right.tm_secl_i);
tmp.tm_cycles_i := f_x_to_zero(left.tm_cycles_i) or f_x_to_zero(right.tm_cycles_i);
tmp.tdr_i := f_x_to_zero(left.tdr_i) or f_x_to_zero(right.tdr_i);
tmp.tdcsr_empty_i := f_x_to_zero(left.tdcsr_empty_i) or f_x_to_zero(right.tdcsr_empty_i);
tmp.dmtr_in_tag_i := f_x_to_zero(left.dmtr_in_tag_i) or f_x_to_zero(right.dmtr_in_tag_i);
tmp.dmtr_in_rdy_i := f_x_to_zero(left.dmtr_in_rdy_i) or f_x_to_zero(right.dmtr_in_rdy_i);
tmp.dmtr_out_tag_i := f_x_to_zero(left.dmtr_out_tag_i) or f_x_to_zero(right.dmtr_out_tag_i);
tmp.dmtr_out_rdy_i := f_x_to_zero(left.dmtr_out_rdy_i) or f_x_to_zero(right.dmtr_out_rdy_i);
tmp.iecraw_i := f_x_to_zero(left.iecraw_i) or f_x_to_zero(right.iecraw_i);
tmp.iectag_i := f_x_to_zero(left.iectag_i) or f_x_to_zero(right.iectag_i);
tmp.iepd_pdelay_i := f_x_to_zero(left.iepd_pdelay_i) or f_x_to_zero(right.iepd_pdelay_i);
tmp.scr_data_i := f_x_to_zero(left.scr_data_i) or f_x_to_zero(right.scr_data_i);
tmp.scr_ready_i := f_x_to_zero(left.scr_ready_i) or f_x_to_zero(right.scr_ready_i);
tmp.rcrr_i := f_x_to_zero(left.rcrr_i) or f_x_to_zero(right.rcrr_i);
tmp.tsbcr_full_i := f_x_to_zero(left.tsbcr_full_i) or f_x_to_zero(right.tsbcr_full_i);
tmp.tsbcr_empty_i := f_x_to_zero(left.tsbcr_empty_i) or f_x_to_zero(right.tsbcr_empty_i);
tmp.tsbcr_count_i := f_x_to_zero(left.tsbcr_count_i) or f_x_to_zero(right.tsbcr_count_i);
tmp.tsbr_sech_i := f_x_to_zero(left.tsbr_sech_i) or f_x_to_zero(right.tsbr_sech_i);
tmp.tsbr_secl_i := f_x_to_zero(left.tsbr_secl_i) or f_x_to_zero(right.tsbr_secl_i);
tmp.tsbr_cycles_i := f_x_to_zero(left.tsbr_cycles_i) or f_x_to_zero(right.tsbr_cycles_i);
tmp.tsbr_fid_channel_i := f_x_to_zero(left.tsbr_fid_channel_i) or f_x_to_zero(right.tsbr_fid_channel_i);
tmp.tsbr_fid_fine_i := f_x_to_zero(left.tsbr_fid_fine_i) or f_x_to_zero(right.tsbr_fid_fine_i);
tmp.tsbr_fid_seqid_i := f_x_to_zero(left.tsbr_fid_seqid_i) or f_x_to_zero(right.tsbr_fid_seqid_i);
tmp.i2cr_scl_in_i := f_x_to_zero(left.i2cr_scl_in_i) or f_x_to_zero(right.i2cr_scl_in_i);
tmp.i2cr_sda_in_i := f_x_to_zero(left.i2cr_sda_in_i) or f_x_to_zero(right.i2cr_sda_in_i);
tmp.tder1_vcxo_freq_i := f_x_to_zero(left.tder1_vcxo_freq_i) or f_x_to_zero(right.tder1_vcxo_freq_i);
tmp.tsbr_debug_i := f_x_to_zero(left.tsbr_debug_i) or f_x_to_zero(right.tsbr_debug_i);
return tmp;
end function;
end package body;
hdl/rtl/fd_main_wishbone_slave.vhd
View file @ f6a2b0a9
This source diff could not be displayed because it is too large. You can view the blob instead.
hdl/rtl/fd_main_wishbone_slave.wb
View file @ f6a2b0a9
......@@ -404,7 +404,48 @@ peripheral {
prefix = "ALUTRIG";
type = MONOSTABLE;
};
};
field {
clock = "clk_ref_i";
name = "IDELAY CE (pulse)";
description = "Write 1 to pulse the IDELAY CE line for 1 clock tick.";
prefix = "IDELAY_CE";
type = MONOSTABLE;
};
field {
clock = "clk_ref_i";
name = "IDELAY RST (GPIO)";
description = "State of IDELAY RST line";
prefix = "IDELAY_RST";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
clock = "clk_ref_i";
name = "IDELAY CAL (GPIO)";
description = "State of IDELAY CAL line";
prefix = "IDELAY_CAL";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
clock = "clk_ref_i";
name = "IDELAY CAL (GPIO)";
description = "State of IDELAY INC line";
prefix = "IDELAY_INC";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
reg {
prefix = "CALR";
......
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment