Commit f6a2b0a9 authored by Tomasz Wlostowski's avatar Tomasz Wlostowski

hdl: added IODELAY control to the WB register block

parent 198cf18b
......@@ -3,7 +3,7 @@
---------------------------------------------------------------------------------------
-- File : fd_channel_wbgen2_pkg.vhd
-- Author : auto-generated by wbgen2 from fd_channel_wishbone_slave.wb
-- Created : Wed Dec 4 17:20:17 2013
-- Created : Wed Mar 20 23:27:12 2019
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE fd_channel_wishbone_slave.wb
......@@ -22,93 +22,119 @@ package fd_channel_wbgen2_pkg is
type t_fd_channel_in_registers is record
dcr_pg_trig_i : std_logic;
dcr_upd_done_i : std_logic;
end record;
end record;
constant c_fd_channel_in_registers_init_value: t_fd_channel_in_registers := (
dcr_pg_trig_i => '0',
dcr_upd_done_i => '0'
);
-- Output registers (WB slave -> user design)
type t_fd_channel_out_registers is record
dcr_enable_o : std_logic;
dcr_mode_o : std_logic;
dcr_pg_arm_o : std_logic;
dcr_update_o : std_logic;
dcr_force_dly_o : std_logic;
dcr_no_fine_o : std_logic;
dcr_force_hi_o : std_logic;
frr_o : std_logic_vector(9 downto 0);
u_starth_o : std_logic_vector(7 downto 0);
u_startl_o : std_logic_vector(31 downto 0);
c_start_o : std_logic_vector(27 downto 0);
f_start_o : std_logic_vector(11 downto 0);
u_endh_o : std_logic_vector(7 downto 0);
u_endl_o : std_logic_vector(31 downto 0);
c_end_o : std_logic_vector(27 downto 0);
f_end_o : std_logic_vector(11 downto 0);
u_delta_o : std_logic_vector(3 downto 0);
c_delta_o : std_logic_vector(27 downto 0);
f_delta_o : std_logic_vector(11 downto 0);
rcr_rep_cnt_o : std_logic_vector(15 downto 0);
rcr_cont_o : std_logic;
end record;
constant c_fd_channel_out_registers_init_value: t_fd_channel_out_registers := (
dcr_enable_o => '0',
dcr_mode_o => '0',
dcr_pg_arm_o => '0',
dcr_update_o => '0',
dcr_force_dly_o => '0',
dcr_no_fine_o => '0',
dcr_force_hi_o => '0',
frr_o => (others => '0'),
u_starth_o => (others => '0'),
u_startl_o => (others => '0'),
c_start_o => (others => '0'),
f_start_o => (others => '0'),
u_endh_o => (others => '0'),
u_endl_o => (others => '0'),
c_end_o => (others => '0'),
f_end_o => (others => '0'),
u_delta_o => (others => '0'),
c_delta_o => (others => '0'),
f_delta_o => (others => '0'),
rcr_rep_cnt_o => (others => '0'),
rcr_cont_o => '0'
);
function "or" (left, right: t_fd_channel_in_registers) return t_fd_channel_in_registers;
function f_x_to_zero (x:std_logic) return std_logic;
function f_x_to_zero (x:std_logic_vector) return std_logic_vector;
);
-- Output registers (WB slave -> user design)
type t_fd_channel_out_registers is record
dcr_enable_o : std_logic;
dcr_mode_o : std_logic;
dcr_pg_arm_o : std_logic;
dcr_update_o : std_logic;
dcr_force_dly_o : std_logic;
dcr_no_fine_o : std_logic;
dcr_force_hi_o : std_logic;
frr_o : std_logic_vector(9 downto 0);
u_starth_o : std_logic_vector(7 downto 0);
u_startl_o : std_logic_vector(31 downto 0);
c_start_o : std_logic_vector(27 downto 0);
f_start_o : std_logic_vector(11 downto 0);
u_endh_o : std_logic_vector(7 downto 0);
u_endl_o : std_logic_vector(31 downto 0);
c_end_o : std_logic_vector(27 downto 0);
f_end_o : std_logic_vector(11 downto 0);
u_delta_o : std_logic_vector(3 downto 0);
c_delta_o : std_logic_vector(27 downto 0);
f_delta_o : std_logic_vector(11 downto 0);
rcr_rep_cnt_o : std_logic_vector(15 downto 0);
rcr_cont_o : std_logic;
end record;
constant c_fd_channel_out_registers_init_value: t_fd_channel_out_registers := (
dcr_enable_o => '0',
dcr_mode_o => '0',
dcr_pg_arm_o => '0',
dcr_update_o => '0',
dcr_force_dly_o => '0',
dcr_no_fine_o => '0',
dcr_force_hi_o => '0',
frr_o => (others => '0'),
u_starth_o => (others => '0'),
u_startl_o => (others => '0'),
c_start_o => (others => '0'),
f_start_o => (others => '0'),
u_endh_o => (others => '0'),
u_endl_o => (others => '0'),
c_end_o => (others => '0'),
f_end_o => (others => '0'),
u_delta_o => (others => '0'),
c_delta_o => (others => '0'),
f_delta_o => (others => '0'),
rcr_rep_cnt_o => (others => '0'),
rcr_cont_o => '0'
);
function "or" (left, right: t_fd_channel_in_registers) return t_fd_channel_in_registers;
function f_x_to_zero (x:std_logic) return std_logic;
function f_x_to_zero (x:std_logic_vector) return std_logic_vector;
component fd_channel_wb_slave is
port (
rst_n_i : in std_logic;
clk_sys_i : in std_logic;
wb_adr_i : in std_logic_vector(3 downto 0);
wb_dat_i : in std_logic_vector(31 downto 0);
wb_dat_o : out std_logic_vector(31 downto 0);
wb_cyc_i : in std_logic;
wb_sel_i : in std_logic_vector(3 downto 0);
wb_stb_i : in std_logic;
wb_we_i : in std_logic;
wb_ack_o : out std_logic;
wb_err_o : out std_logic;
wb_rty_o : out std_logic;
wb_stall_o : out std_logic;
clk_ref_i : in std_logic;
regs_i : in t_fd_channel_in_registers;
regs_o : out t_fd_channel_out_registers
);
end component;
end package;
package body fd_channel_wbgen2_pkg is
function f_x_to_zero (x:std_logic) return std_logic is
begin
if x = '1' then
return '1';
else
return '0';
end if;
if x = '1' then
return '1';
else
return '0';
end if;
end function;
function f_x_to_zero (x:std_logic_vector) return std_logic_vector is
variable tmp: std_logic_vector(x'length-1 downto 0);
variable tmp: std_logic_vector(x'length-1 downto 0);
begin
for i in 0 to x'length-1 loop
if(x(i) = 'X' or x(i) = 'U') then
tmp(i):= '0';
else
tmp(i):=x(i);
end if;
end loop;
return tmp;
for i in 0 to x'length-1 loop
if(x(i) = 'X' or x(i) = 'U') then
tmp(i):= '0';
else
tmp(i):=x(i);
end if;
end loop;
return tmp;
end function;
function "or" (left, right: t_fd_channel_in_registers) return t_fd_channel_in_registers is
variable tmp: t_fd_channel_in_registers;
variable tmp: t_fd_channel_in_registers;
begin
tmp.dcr_pg_trig_i := f_x_to_zero(left.dcr_pg_trig_i) or f_x_to_zero(right.dcr_pg_trig_i);
tmp.dcr_upd_done_i := f_x_to_zero(left.dcr_upd_done_i) or f_x_to_zero(right.dcr_upd_done_i);
return tmp;
tmp.dcr_pg_trig_i := f_x_to_zero(left.dcr_pg_trig_i) or f_x_to_zero(right.dcr_pg_trig_i);
tmp.dcr_upd_done_i := f_x_to_zero(left.dcr_upd_done_i) or f_x_to_zero(right.dcr_upd_done_i);
return tmp;
end function;
end package body;
......@@ -3,7 +3,7 @@
---------------------------------------------------------------------------------------
-- File : fd_channel_wishbone_slave.vhd
-- Author : auto-generated by wbgen2 from fd_channel_wishbone_slave.wb
-- Created : Wed Dec 4 17:20:17 2013
-- Created : Wed Mar 20 23:27:12 2019
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE fd_channel_wishbone_slave.wb
......@@ -18,22 +18,24 @@ use work.fd_channel_wbgen2_pkg.all;
entity fd_channel_wb_slave is
port (
rst_n_i : in std_logic;
clk_sys_i : in std_logic;
wb_adr_i : in std_logic_vector(3 downto 0);
wb_dat_i : in std_logic_vector(31 downto 0);
wb_dat_o : out std_logic_vector(31 downto 0);
wb_cyc_i : in std_logic;
wb_sel_i : in std_logic_vector(3 downto 0);
wb_stb_i : in std_logic;
wb_we_i : in std_logic;
wb_ack_o : out std_logic;
wb_stall_o : out std_logic;
clk_ref_i : in std_logic;
regs_i : in t_fd_channel_in_registers;
regs_o : out t_fd_channel_out_registers
);
port (
rst_n_i : in std_logic;
clk_sys_i : in std_logic;
wb_adr_i : in std_logic_vector(3 downto 0);
wb_dat_i : in std_logic_vector(31 downto 0);
wb_dat_o : out std_logic_vector(31 downto 0);
wb_cyc_i : in std_logic;
wb_sel_i : in std_logic_vector(3 downto 0);
wb_stb_i : in std_logic;
wb_we_i : in std_logic;
wb_ack_o : out std_logic;
wb_err_o : out std_logic;
wb_rty_o : out std_logic;
wb_stall_o : out std_logic;
clk_ref_i : in std_logic;
regs_i : in t_fd_channel_in_registers;
regs_o : out t_fd_channel_out_registers
);
end fd_channel_wb_slave;
architecture syn of fd_channel_wb_slave is
......@@ -94,556 +96,553 @@ signal allones : std_logic_vector(31 downto 0);
signal allzeros : std_logic_vector(31 downto 0);
begin
-- Some internal signals assignments. For (foreseen) compatibility with other bus standards.
wrdata_reg <= wb_dat_i;
bwsel_reg <= wb_sel_i;
rd_int <= wb_cyc_i and (wb_stb_i and (not wb_we_i));
wr_int <= wb_cyc_i and (wb_stb_i and wb_we_i);
allones <= (others => '1');
allzeros <= (others => '0');
-- Some internal signals assignments
wrdata_reg <= wb_dat_i;
--
-- Main register bank access process.
process (clk_sys_i, rst_n_i)
begin
if (rst_n_i = '0') then
ack_sreg <= "0000000000";
ack_in_progress <= '0';
rddata_reg <= "00000000000000000000000000000000";
fd_channel_dcr_enable_int <= '0';
fd_channel_dcr_mode_int <= '0';
fd_channel_dcr_pg_arm_int <= '0';
fd_channel_dcr_pg_arm_int_delay <= '0';
fd_channel_dcr_update_int <= '0';
fd_channel_dcr_update_int_delay <= '0';
fd_channel_dcr_force_dly_int <= '0';
fd_channel_dcr_force_dly_int_delay <= '0';
fd_channel_dcr_no_fine_int <= '0';
fd_channel_dcr_force_hi_int <= '0';
fd_channel_frr_int <= "0000000000";
fd_channel_frr_swb <= '0';
fd_channel_frr_swb_delay <= '0';
fd_channel_u_starth_int <= "00000000";
fd_channel_u_startl_int <= "00000000000000000000000000000000";
fd_channel_c_start_int <= "0000000000000000000000000000";
fd_channel_f_start_int <= "000000000000";
fd_channel_u_endh_int <= "00000000";
fd_channel_u_endl_int <= "00000000000000000000000000000000";
fd_channel_c_end_int <= "0000000000000000000000000000";
fd_channel_f_end_int <= "000000000000";
fd_channel_u_delta_int <= "0000";
fd_channel_c_delta_int <= "0000000000000000000000000000";
fd_channel_f_delta_int <= "000000000000";
fd_channel_rcr_rep_cnt_int <= "0000000000000000";
fd_channel_rcr_cont_int <= '0';
elsif rising_edge(clk_sys_i) then
process (clk_sys_i, rst_n_i)
begin
if (rst_n_i = '0') then
ack_sreg <= "0000000000";
ack_in_progress <= '0';
rddata_reg <= "00000000000000000000000000000000";
fd_channel_dcr_enable_int <= '0';
fd_channel_dcr_mode_int <= '0';
fd_channel_dcr_pg_arm_int <= '0';
fd_channel_dcr_pg_arm_int_delay <= '0';
fd_channel_dcr_update_int <= '0';
fd_channel_dcr_update_int_delay <= '0';
fd_channel_dcr_force_dly_int <= '0';
fd_channel_dcr_force_dly_int_delay <= '0';
fd_channel_dcr_no_fine_int <= '0';
fd_channel_dcr_force_hi_int <= '0';
fd_channel_frr_int <= "0000000000";
fd_channel_frr_swb <= '0';
fd_channel_frr_swb_delay <= '0';
fd_channel_u_starth_int <= "00000000";
fd_channel_u_startl_int <= "00000000000000000000000000000000";
fd_channel_c_start_int <= "0000000000000000000000000000";
fd_channel_f_start_int <= "000000000000";
fd_channel_u_endh_int <= "00000000";
fd_channel_u_endl_int <= "00000000000000000000000000000000";
fd_channel_c_end_int <= "0000000000000000000000000000";
fd_channel_f_end_int <= "000000000000";
fd_channel_u_delta_int <= "0000";
fd_channel_c_delta_int <= "0000000000000000000000000000";
fd_channel_f_delta_int <= "000000000000";
fd_channel_rcr_rep_cnt_int <= "0000000000000000";
fd_channel_rcr_cont_int <= '0';
elsif rising_edge(clk_sys_i) then
-- advance the ACK generator shift register
ack_sreg(8 downto 0) <= ack_sreg(9 downto 1);
ack_sreg(9) <= '0';
if (ack_in_progress = '1') then
if (ack_sreg(0) = '1') then
ack_in_progress <= '0';
else
fd_channel_dcr_pg_arm_int <= fd_channel_dcr_pg_arm_int_delay;
fd_channel_dcr_pg_arm_int_delay <= '0';
fd_channel_dcr_update_int <= fd_channel_dcr_update_int_delay;
fd_channel_dcr_update_int_delay <= '0';
fd_channel_dcr_force_dly_int <= fd_channel_dcr_force_dly_int_delay;
fd_channel_dcr_force_dly_int_delay <= '0';
fd_channel_frr_swb <= fd_channel_frr_swb_delay;
fd_channel_frr_swb_delay <= '0';
end if;
ack_sreg(8 downto 0) <= ack_sreg(9 downto 1);
ack_sreg(9) <= '0';
if (ack_in_progress = '1') then
if (ack_sreg(0) = '1') then
ack_in_progress <= '0';
else
if ((wb_cyc_i = '1') and (wb_stb_i = '1')) then
case rwaddr_reg(3 downto 0) is
when "0000" =>
if (wb_we_i = '1') then
fd_channel_dcr_enable_int <= wrdata_reg(0);
fd_channel_dcr_mode_int <= wrdata_reg(1);
fd_channel_dcr_pg_arm_int <= wrdata_reg(2);
fd_channel_dcr_pg_arm_int_delay <= wrdata_reg(2);
fd_channel_dcr_update_int <= wrdata_reg(4);
fd_channel_dcr_update_int_delay <= wrdata_reg(4);
fd_channel_dcr_force_dly_int <= wrdata_reg(6);
fd_channel_dcr_force_dly_int_delay <= wrdata_reg(6);
fd_channel_dcr_no_fine_int <= wrdata_reg(7);
fd_channel_dcr_force_hi_int <= wrdata_reg(8);
end if;
rddata_reg(0) <= fd_channel_dcr_enable_int;
rddata_reg(1) <= fd_channel_dcr_mode_int;
rddata_reg(2) <= '0';
rddata_reg(3) <= fd_channel_dcr_pg_trig_sync1;
rddata_reg(4) <= '0';
rddata_reg(5) <= fd_channel_dcr_upd_done_sync1;
rddata_reg(6) <= '0';
rddata_reg(7) <= fd_channel_dcr_no_fine_int;
rddata_reg(8) <= fd_channel_dcr_force_hi_int;
rddata_reg(9) <= 'X';
rddata_reg(10) <= 'X';
rddata_reg(11) <= 'X';
rddata_reg(12) <= 'X';
rddata_reg(13) <= 'X';
rddata_reg(14) <= 'X';
rddata_reg(15) <= 'X';
rddata_reg(16) <= 'X';
rddata_reg(17) <= 'X';
rddata_reg(18) <= 'X';
rddata_reg(19) <= 'X';
rddata_reg(20) <= 'X';
rddata_reg(21) <= 'X';
rddata_reg(22) <= 'X';
rddata_reg(23) <= 'X';
rddata_reg(24) <= 'X';
rddata_reg(25) <= 'X';
rddata_reg(26) <= 'X';
rddata_reg(27) <= 'X';
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
ack_sreg(4) <= '1';
ack_in_progress <= '1';
when "0001" =>
if (wb_we_i = '1') then
fd_channel_frr_int <= wrdata_reg(9 downto 0);
fd_channel_frr_swb <= '1';
fd_channel_frr_swb_delay <= '1';
end if;
rddata_reg(9 downto 0) <= fd_channel_frr_int;
rddata_reg(10) <= 'X';
rddata_reg(11) <= 'X';
rddata_reg(12) <= 'X';
rddata_reg(13) <= 'X';
rddata_reg(14) <= 'X';
rddata_reg(15) <= 'X';
rddata_reg(16) <= 'X';
rddata_reg(17) <= 'X';
rddata_reg(18) <= 'X';
rddata_reg(19) <= 'X';
rddata_reg(20) <= 'X';
rddata_reg(21) <= 'X';
rddata_reg(22) <= 'X';
rddata_reg(23) <= 'X';
rddata_reg(24) <= 'X';
rddata_reg(25) <= 'X';
rddata_reg(26) <= 'X';
rddata_reg(27) <= 'X';
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
ack_sreg(3) <= '1';
ack_in_progress <= '1';
when "0010" =>
if (wb_we_i = '1') then
fd_channel_u_starth_int <= wrdata_reg(7 downto 0);
end if;
rddata_reg(7 downto 0) <= fd_channel_u_starth_int;
rddata_reg(8) <= 'X';
rddata_reg(9) <= 'X';
rddata_reg(10) <= 'X';
rddata_reg(11) <= 'X';
rddata_reg(12) <= 'X';
rddata_reg(13) <= 'X';
rddata_reg(14) <= 'X';
rddata_reg(15) <= 'X';
rddata_reg(16) <= 'X';
rddata_reg(17) <= 'X';
rddata_reg(18) <= 'X';
rddata_reg(19) <= 'X';
rddata_reg(20) <= 'X';
rddata_reg(21) <= 'X';
rddata_reg(22) <= 'X';
rddata_reg(23) <= 'X';
rddata_reg(24) <= 'X';
rddata_reg(25) <= 'X';
rddata_reg(26) <= 'X';
rddata_reg(27) <= 'X';
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "0011" =>
if (wb_we_i = '1') then
fd_channel_u_startl_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= fd_channel_u_startl_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "0100" =>
if (wb_we_i = '1') then
fd_channel_c_start_int <= wrdata_reg(27 downto 0);
end if;
rddata_reg(27 downto 0) <= fd_channel_c_start_int;
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "0101" =>
if (wb_we_i = '1') then
fd_channel_f_start_int <= wrdata_reg(11 downto 0);
end if;
rddata_reg(11 downto 0) <= fd_channel_f_start_int;
rddata_reg(12) <= 'X';
rddata_reg(13) <= 'X';
rddata_reg(14) <= 'X';
rddata_reg(15) <= 'X';
rddata_reg(16) <= 'X';
rddata_reg(17) <= 'X';
rddata_reg(18) <= 'X';
rddata_reg(19) <= 'X';
rddata_reg(20) <= 'X';
rddata_reg(21) <= 'X';
rddata_reg(22) <= 'X';
rddata_reg(23) <= 'X';
rddata_reg(24) <= 'X';
rddata_reg(25) <= 'X';
rddata_reg(26) <= 'X';
rddata_reg(27) <= 'X';
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "0110" =>
if (wb_we_i = '1') then
fd_channel_u_endh_int <= wrdata_reg(7 downto 0);
end if;
rddata_reg(7 downto 0) <= fd_channel_u_endh_int;
rddata_reg(8) <= 'X';
rddata_reg(9) <= 'X';
rddata_reg(10) <= 'X';
rddata_reg(11) <= 'X';
rddata_reg(12) <= 'X';
rddata_reg(13) <= 'X';
rddata_reg(14) <= 'X';
rddata_reg(15) <= 'X';
rddata_reg(16) <= 'X';
rddata_reg(17) <= 'X';
rddata_reg(18) <= 'X';
rddata_reg(19) <= 'X';
rddata_reg(20) <= 'X';
rddata_reg(21) <= 'X';
rddata_reg(22) <= 'X';
rddata_reg(23) <= 'X';
rddata_reg(24) <= 'X';
rddata_reg(25) <= 'X';
rddata_reg(26) <= 'X';
rddata_reg(27) <= 'X';
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "0111" =>
if (wb_we_i = '1') then
fd_channel_u_endl_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= fd_channel_u_endl_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "1000" =>
if (wb_we_i = '1') then
fd_channel_c_end_int <= wrdata_reg(27 downto 0);
end if;
rddata_reg(27 downto 0) <= fd_channel_c_end_int;
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "1001" =>
if (wb_we_i = '1') then
fd_channel_f_end_int <= wrdata_reg(11 downto 0);
end if;
rddata_reg(11 downto 0) <= fd_channel_f_end_int;
rddata_reg(12) <= 'X';
rddata_reg(13) <= 'X';
rddata_reg(14) <= 'X';
rddata_reg(15) <= 'X';
rddata_reg(16) <= 'X';
rddata_reg(17) <= 'X';
rddata_reg(18) <= 'X';
rddata_reg(19) <= 'X';
rddata_reg(20) <= 'X';
rddata_reg(21) <= 'X';
rddata_reg(22) <= 'X';
rddata_reg(23) <= 'X';
rddata_reg(24) <= 'X';
rddata_reg(25) <= 'X';
rddata_reg(26) <= 'X';
rddata_reg(27) <= 'X';
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "1010" =>
if (wb_we_i = '1') then
fd_channel_u_delta_int <= wrdata_reg(3 downto 0);
end if;
rddata_reg(3 downto 0) <= fd_channel_u_delta_int;
rddata_reg(4) <= 'X';
rddata_reg(5) <= 'X';
rddata_reg(6) <= 'X';
rddata_reg(7) <= 'X';
rddata_reg(8) <= 'X';
rddata_reg(9) <= 'X';
rddata_reg(10) <= 'X';
rddata_reg(11) <= 'X';
rddata_reg(12) <= 'X';
rddata_reg(13) <= 'X';
rddata_reg(14) <= 'X';
rddata_reg(15) <= 'X';
rddata_reg(16) <= 'X';
rddata_reg(17) <= 'X';
rddata_reg(18) <= 'X';
rddata_reg(19) <= 'X';
rddata_reg(20) <= 'X';
rddata_reg(21) <= 'X';
rddata_reg(22) <= 'X';
rddata_reg(23) <= 'X';
rddata_reg(24) <= 'X';
rddata_reg(25) <= 'X';
rddata_reg(26) <= 'X';
rddata_reg(27) <= 'X';
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "1011" =>
if (wb_we_i = '1') then
fd_channel_c_delta_int <= wrdata_reg(27 downto 0);
end if;
rddata_reg(27 downto 0) <= fd_channel_c_delta_int;
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "1100" =>
if (wb_we_i = '1') then
fd_channel_f_delta_int <= wrdata_reg(11 downto 0);
end if;
rddata_reg(11 downto 0) <= fd_channel_f_delta_int;
rddata_reg(12) <= 'X';
rddata_reg(13) <= 'X';
rddata_reg(14) <= 'X';
rddata_reg(15) <= 'X';
rddata_reg(16) <= 'X';
rddata_reg(17) <= 'X';
rddata_reg(18) <= 'X';
rddata_reg(19) <= 'X';
rddata_reg(20) <= 'X';
rddata_reg(21) <= 'X';
rddata_reg(22) <= 'X';
rddata_reg(23) <= 'X';
rddata_reg(24) <= 'X';
rddata_reg(25) <= 'X';
rddata_reg(26) <= 'X';
rddata_reg(27) <= 'X';
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "1101" =>
if (wb_we_i = '1') then
fd_channel_rcr_rep_cnt_int <= wrdata_reg(15 downto 0);
fd_channel_rcr_cont_int <= wrdata_reg(16);
end if;
rddata_reg(15 downto 0) <= fd_channel_rcr_rep_cnt_int;
rddata_reg(16) <= fd_channel_rcr_cont_int;
rddata_reg(17) <= 'X';
rddata_reg(18) <= 'X';
rddata_reg(19) <= 'X';
rddata_reg(20) <= 'X';
rddata_reg(21) <= 'X';
rddata_reg(22) <= 'X';
rddata_reg(23) <= 'X';
rddata_reg(24) <= 'X';
rddata_reg(25) <= 'X';
rddata_reg(26) <= 'X';
rddata_reg(27) <= 'X';
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when others =>
fd_channel_dcr_pg_arm_int <= fd_channel_dcr_pg_arm_int_delay;
fd_channel_dcr_pg_arm_int_delay <= '0';
fd_channel_dcr_update_int <= fd_channel_dcr_update_int_delay;
fd_channel_dcr_update_int_delay <= '0';
fd_channel_dcr_force_dly_int <= fd_channel_dcr_force_dly_int_delay;
fd_channel_dcr_force_dly_int_delay <= '0';