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FMC DEL 1ns 4cha
Commits
f5f3da02
Commit
f5f3da02
authored
Jul 04, 2013
by
Tomasz Wlostowski
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hdl/rtl: fix unclear timebase offset signal name
parent
4e9db31d
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2 changed files
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12 additions
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12 deletions
+12
-12
fd_acam_timestamp_postprocessor.vhd
hdl/rtl/fd_acam_timestamp_postprocessor.vhd
+6
-6
fd_acam_timestamper.vhd
hdl/rtl/fd_acam_timestamper.vhd
+6
-6
No files found.
hdl/rtl/fd_acam_timestamp_postprocessor.vhd
View file @
f5f3da02
...
@@ -6,7 +6,7 @@
...
@@ -6,7 +6,7 @@
-- Author : Tomasz Wlostowski
-- Author : Tomasz Wlostowski
-- Company : CERN
-- Company : CERN
-- Created : 2011-08-29
-- Created : 2011-08-29
-- Last update: 2013-0
2-06
-- Last update: 2013-0
7-02
-- Platform : FPGA-generic
-- Platform : FPGA-generic
-- Standard : VHDL'93
-- Standard : VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
...
@@ -75,7 +75,7 @@ entity fd_acam_timestamp_postprocessor is
...
@@ -75,7 +75,7 @@ entity fd_acam_timestamp_postprocessor is
-- Offset between the actual timescale and the ACAM fixed start signal generated
-- Offset between the actual timescale and the ACAM fixed start signal generated
-- by the AD9516 PLL. Used to align the timestamps to the externally
-- by the AD9516 PLL. Used to align the timestamps to the externally
-- provided time base (e.g. by White Rabbit).
-- provided time base (e.g. by White Rabbit).
acam_
subcycl
e_offset_i
:
in
std_logic_vector
(
5
downto
0
);
acam_
timebas
e_offset_i
:
in
std_logic_vector
(
5
downto
0
);
---------------------------------------------------------------------------
---------------------------------------------------------------------------
-- Post-processed timestamp. WARNING! DE-NORMALIZED!
-- Post-processed timestamp. WARNING! DE-NORMALIZED!
...
@@ -195,7 +195,7 @@ begin -- behavioral
...
@@ -195,7 +195,7 @@ begin -- behavioral
-- 16 at the AD9516 PLL). So, every time there's a counter resync event
-- 16 at the AD9516 PLL). So, every time there's a counter resync event
-- (from associated WR PTP Core or an internal one), we simply count
-- (from associated WR PTP Core or an internal one), we simply count
-- the number of ref clock cycles between the 1-PPS and the nearest TDC
-- the number of ref clock cycles between the 1-PPS and the nearest TDC
-- start edge and store it in acam_
subcycl
e_offset_i.
-- start edge and store it in acam_
timebas
e_offset_i.
--
--
-- This value is added here to align the result to our timescale
-- This value is added here to align the result to our timescale
-- without messing around with the PLL.
-- without messing around with the PLL.
...
@@ -207,7 +207,7 @@ begin -- behavioral
...
@@ -207,7 +207,7 @@ begin -- behavioral
tag_utc_o
<=
std_logic_vector
(
post_tag_utc
);
tag_utc_o
<=
std_logic_vector
(
post_tag_utc
);
tag_coarse_o
<=
std_logic_vector
(
tag_coarse_o
<=
std_logic_vector
(
signed
(
post_tag_coarse
)
-- index of start pulse (mod 16 = 0)
signed
(
post_tag_coarse
)
-- index of start pulse (mod 16 = 0)
+
signed
(
acam_
subcycl
e_offset_i
)
-- start-to-timescale offset
+
signed
(
acam_
timebas
e_offset_i
)
-- start-to-timescale offset
+
signed
(
post_frac_multiplied_d0
(
post_frac_multiplied_d0
'left
downto
c_SCALER_SHIFT
+
g_frac_bits
)));
+
signed
(
post_frac_multiplied_d0
(
post_frac_multiplied_d0
'left
downto
c_SCALER_SHIFT
+
g_frac_bits
)));
-- extra coarse counts from ACAM's frac part after rescaling
-- extra coarse counts from ACAM's frac part after rescaling
...
@@ -221,10 +221,10 @@ begin -- behavioral
...
@@ -221,10 +221,10 @@ begin -- behavioral
tag_coarse_o
<=
raw_coarse_i
&
raw_start_offset_i
;
tag_coarse_o
<=
raw_coarse_i
&
raw_start_offset_i
;
tag_frac_o
<=
raw_frac_i
(
11
downto
0
);
tag_frac_o
<=
raw_frac_i
(
11
downto
0
);
tag_dbg_raw_o
(
10
downto
0
)
<=
raw_frac_i
(
22
downto
12
);
tag_dbg_raw_o
(
10
downto
0
)
<=
raw_frac_i
(
22
downto
12
);
tag_dbg_raw_o
(
15
downto
11
)
<=
acam_
subcycl
e_offset_i
(
4
downto
0
);
tag_dbg_raw_o
(
15
downto
11
)
<=
acam_
timebas
e_offset_i
(
4
downto
0
);
tag_dbg_raw_o
(
23
downto
16
)
<=
raw_coarse_i
(
7
downto
0
);
tag_dbg_raw_o
(
23
downto
16
)
<=
raw_coarse_i
(
7
downto
0
);
tag_dbg_raw_o
(
30
downto
24
)
<=
raw_utc_i
(
6
downto
0
);
tag_dbg_raw_o
(
30
downto
24
)
<=
raw_utc_i
(
6
downto
0
);
tag_dbg_raw_o
(
31
)
<=
acam_
subcycl
e_offset_i
(
5
);
tag_dbg_raw_o
(
31
)
<=
acam_
timebas
e_offset_i
(
5
);
tag_valid_o
<=
'1'
;
tag_valid_o
<=
'1'
;
else
else
...
...
hdl/rtl/fd_acam_timestamper.vhd
View file @
f5f3da02
...
@@ -6,7 +6,7 @@
...
@@ -6,7 +6,7 @@
-- Author : Tomasz Wlostowski
-- Author : Tomasz Wlostowski
-- Company : CERN
-- Company : CERN
-- Created : 2011-08-24
-- Created : 2011-08-24
-- Last update: 2013-0
2-1
2
-- Last update: 2013-0
7-0
2
-- Platform : FPGA-generic
-- Platform : FPGA-generic
-- Standard : VHDL'93
-- Standard : VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
...
@@ -168,7 +168,7 @@ architecture behavioral of fd_acam_timestamper is
...
@@ -168,7 +168,7 @@ architecture behavioral of fd_acam_timestamper is
raw_coarse_i
:
in
std_logic_vector
(
c_TIMESTAMP_COARSE_BITS
-5-1
downto
0
);
raw_coarse_i
:
in
std_logic_vector
(
c_TIMESTAMP_COARSE_BITS
-5-1
downto
0
);
raw_frac_i
:
in
std_logic_vector
(
22
downto
0
);
raw_frac_i
:
in
std_logic_vector
(
22
downto
0
);
raw_start_offset_i
:
in
std_logic_vector
(
4
downto
0
);
raw_start_offset_i
:
in
std_logic_vector
(
4
downto
0
);
acam_
subcycl
e_offset_i
:
in
std_logic_vector
(
5
downto
0
);
acam_
timebas
e_offset_i
:
in
std_logic_vector
(
5
downto
0
);
tag_valid_o
:
out
std_logic
;
tag_valid_o
:
out
std_logic
;
tag_utc_o
:
out
std_logic_vector
(
c_TIMESTAMP_UTC_BITS
-1
downto
0
);
tag_utc_o
:
out
std_logic_vector
(
c_TIMESTAMP_UTC_BITS
-1
downto
0
);
tag_coarse_o
:
out
std_logic_vector
(
c_TIMESTAMP_COARSE_BITS
-1
downto
0
);
tag_coarse_o
:
out
std_logic_vector
(
c_TIMESTAMP_COARSE_BITS
-1
downto
0
);
...
@@ -225,7 +225,7 @@ architecture behavioral of fd_acam_timestamper is
...
@@ -225,7 +225,7 @@ architecture behavioral of fd_acam_timestamper is
signal
start_count
:
unsigned
(
4
downto
0
);
signal
start_count
:
unsigned
(
4
downto
0
);
signal
coarse_count
:
unsigned
(
c_TIMESTAMP_COARSE_BITS
-5-1
downto
0
);
signal
coarse_count
:
unsigned
(
c_TIMESTAMP_COARSE_BITS
-5-1
downto
0
);
signal
utc_count
:
unsigned
(
c_TIMESTAMP_UTC_BITS
-1
downto
0
);
signal
utc_count
:
unsigned
(
c_TIMESTAMP_UTC_BITS
-1
downto
0
);
signal
subcycl
e_offset
:
signed
(
5
downto
0
);
signal
timebas
e_offset
:
signed
(
5
downto
0
);
signal
gcr_input_en_d0
:
std_logic
;
signal
gcr_input_en_d0
:
std_logic
;
...
@@ -482,7 +482,7 @@ begin -- behave
...
@@ -482,7 +482,7 @@ begin -- behave
if
rst_n_i
=
'0'
or
regs_i
.
gcr_bypass_o
=
'1'
then
if
rst_n_i
=
'0'
or
regs_i
.
gcr_bypass_o
=
'1'
then
start_count
<=
(
others
=>
'0'
);
start_count
<=
(
others
=>
'0'
);
subcycl
e_offset
<=
(
others
=>
'0'
);
timebas
e_offset
<=
(
others
=>
'0'
);
advance_coarse
<=
'0'
;
advance_coarse
<=
'0'
;
else
else
...
@@ -492,7 +492,7 @@ begin -- behave
...
@@ -492,7 +492,7 @@ begin -- behave
-- between the current start count and the LSBs of the new time value
-- between the current start count and the LSBs of the new time value
-- and correct the timestamps later on.
-- and correct the timestamps later on.
if
(
csync_p1_i
=
'1'
)
then
if
(
csync_p1_i
=
'1'
)
then
subcycl
e_offset
<=
signed
(
'0'
&
csync_coarse_i
(
4
downto
0
))
-
signed
(
'0'
&
start_count
)
-
1
;
timebas
e_offset
<=
signed
(
'0'
&
csync_coarse_i
(
4
downto
0
))
-
signed
(
'0'
&
start_count
)
-
1
;
end
if
;
end
if
;
-- Rising edge on TDC_START? Resynchronize the counter, to go to zero
-- Rising edge on TDC_START? Resynchronize the counter, to go to zero
...
@@ -856,7 +856,7 @@ begin -- behave
...
@@ -856,7 +856,7 @@ begin -- behave
raw_coarse_i
=>
std_logic_vector
(
raw_tag_coarse
),
raw_coarse_i
=>
std_logic_vector
(
raw_tag_coarse
),
raw_frac_i
=>
std_logic_vector
(
raw_tag_frac
),
raw_frac_i
=>
std_logic_vector
(
raw_tag_frac
),
raw_start_offset_i
=>
std_logic_vector
(
raw_tag_start_offset
),
raw_start_offset_i
=>
std_logic_vector
(
raw_tag_start_offset
),
acam_
subcycle_offset_i
=>
std_logic_vector
(
subcycl
e_offset
),
acam_
timebase_offset_i
=>
std_logic_vector
(
timebas
e_offset
),
tag_valid_o
=>
tag_valid_int
,
tag_valid_o
=>
tag_valid_int
,
tag_utc_o
=>
tag_utc_o
,
tag_utc_o
=>
tag_utc_o
,
tag_coarse_o
=>
tag_coarse
,
tag_coarse_o
=>
tag_coarse
,
...
...
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