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FMC DEL 1ns 4cha
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FMC DEL 1ns 4cha
Commits
e9b7dcb8
Commit
e9b7dcb8
authored
Dec 13, 2022
by
Dimitris Lampridis
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hdl: improve top-level names (also used for bitstream filenames)
parent
ec709a5c
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4 changed files
with
19 additions
and
19 deletions
+19
-19
Manifest.py
hdl/syn/spec/Manifest.py
+4
-4
Manifest.py
hdl/syn/svec/Manifest.py
+3
-3
spec_fine_delay_top.vhd
hdl/top/spec/spec_fine_delay_top.vhd
+6
-6
svec_fine_delay_top.vhd
hdl/top/svec/svec_fine_delay_top.vhd
+6
-6
No files found.
hdl/syn/spec/Manifest.py
View file @
e9b7dcb8
...
...
@@ -13,15 +13,15 @@ if locals().get('fetchto', None) is None:
syn_device
=
"xc6slx45t"
syn_grade
=
"-3"
syn_package
=
"fgg484"
syn_project
=
"spec_fine_delay
_top
.xise"
syn_project
=
"spec_fine_delay.xise"
syn_tool
=
"ise"
syn_top
=
"spec_fine_delay
_top
"
syn_top
=
"spec_fine_delay"
spec_base_ucf
=
[
'wr'
,
'onewire'
,
'spi'
]
board
=
"spec"
ctrls
=
[
"bank3_64b_32b"
]
files
=
[
"buildinfo_pkg.vhd"
,
"sourceid_spec_fine_delay_
top_
pkg.vhd"
]
files
=
[
"buildinfo_pkg.vhd"
,
"sourceid_spec_fine_delay_pkg.vhd"
]
modules
=
{
"local"
:
[
"../../top/spec"
]
...
...
@@ -37,7 +37,7 @@ try:
# Assume this module is in fact a git submodule of a main project that
# is in the same directory as general-cores...
exec
(
open
(
fetchto
+
"/general-cores/tools/gen_sourceid.py"
)
.
read
(),
None
,
{
'project'
:
'spec_fine_delay
_top
'
})
None
,
{
'project'
:
'spec_fine_delay'
})
except
Exception
as
e
:
print
(
"Error: cannot generate source id file"
)
raise
...
...
hdl/syn/svec/Manifest.py
View file @
e9b7dcb8
...
...
@@ -9,7 +9,7 @@ action = "synthesis"
syn_device
=
"xc6slx150t"
syn_grade
=
"-3"
syn_package
=
"fgg900"
syn_top
=
"svec_
top
"
syn_top
=
"svec_
fine_delay
"
syn_project
=
"svec_fine_delay.xise"
syn_tool
=
"ise"
...
...
@@ -25,7 +25,7 @@ fetchto = os.path.abspath(fetchto)
files
=
[
"buildinfo_pkg.vhd"
,
"sourceid_svec_fine_delay_
top_
pkg.vhd"
,
"sourceid_svec_fine_delay_pkg.vhd"
,
"svec_fine_delay_top.ucf"
,
"svec-fd0.ucf"
,
"svec-fd1.ucf"
...
...
@@ -47,7 +47,7 @@ try:
# Assume this module is in fact a git submodule of a main project that
# is in the same directory as general-cores...
exec
(
open
(
fetchto
+
"/general-cores/tools/gen_sourceid.py"
)
.
read
(),
None
,
{
'project'
:
'svec_fine_delay
_top
'
})
None
,
{
'project'
:
'svec_fine_delay'
})
except
Exception
as
e
:
print
(
"Error: cannot generate source id file"
)
raise
...
...
hdl/top/spec/spec_fine_delay_top.vhd
View file @
e9b7dcb8
...
...
@@ -8,7 +8,7 @@
-- https://ohwr.org/projects/fmc-delay-1ns-8cha
--------------------------------------------------------------------------------
--
-- unit name: spec_fine_delay
_top
-- unit name: spec_fine_delay
--
-- description: Top entity for Fine Delay reference design.
--
...
...
@@ -38,13 +38,13 @@ use work.wishbone_pkg.all;
use
work
.
wr_board_pkg
.
all
;
use
work
.
wr_fabric_pkg
.
all
;
use
work
.
fine_delay_pkg
.
all
;
use
work
.
sourceid_spec_fine_delay_
top_
pkg
;
use
work
.
sourceid_spec_fine_delay_pkg
;
library
unisim
;
use
unisim
.
vcomponents
.
all
;
entity
spec_fine_delay
_top
is
entity
spec_fine_delay
is
generic
(
g_WRPC_INITF
:
string
:
=
"../../ip_cores/wr-cores/bin/wrpc/wrc_phy8.bram"
;
-- Simulation-mode enable parameter. Set by default (synthesis) to 0, and
...
...
@@ -183,9 +183,9 @@ entity spec_fine_delay_top is
fmc0_scl_b
:
inout
std_logic
;
fmc0_sda_b
:
inout
std_logic
);
end
entity
spec_fine_delay
_top
;
end
entity
spec_fine_delay
;
architecture
arch
of
spec_fine_delay
_top
is
architecture
arch
of
spec_fine_delay
is
component
IBUFDS
is
...
...
@@ -312,7 +312,7 @@ begin -- architecture arch
g_DEVICE_ID
=>
x"574f_0001"
,
-- SPEC + 1xFine Delay
g_VERSION
=>
x"0300_0008"
,
g_CAPABILITIES
=>
x"0000_0000"
,
g_COMMIT_ID
=>
sourceid_spec_fine_delay_
top_
pkg
.
sourceid
)
g_COMMIT_ID
=>
sourceid_spec_fine_delay_pkg
.
sourceid
)
port
map
(
clk_i
=>
clk_sys_62m5
,
rst_n_i
=>
rst_sys_62m5_n
,
...
...
hdl/top/svec/svec_fine_delay_top.vhd
View file @
e9b7dcb8
...
...
@@ -8,7 +8,7 @@
-- https://ohwr.org/projects/fmc-delay-1ns-8cha
--------------------------------------------------------------------------------
--
-- unit name: s
pec_top
-- unit name: s
vec_fine_delay
--
-- description: Top entity for Fine Delay reference design.
--
...
...
@@ -43,12 +43,12 @@ use work.wishbone_pkg.all;
use
work
.
wr_board_pkg
.
all
;
use
work
.
wr_fabric_pkg
.
all
;
use
work
.
fine_delay_pkg
.
all
;
use
work
.
sourceid_svec_fine_delay_
top_
pkg
;
use
work
.
sourceid_svec_fine_delay_pkg
;
library
unisim
;
use
unisim
.
vcomponents
.
all
;
entity
svec_
top
is
entity
svec_
fine_delay
is
generic
(
g_WRPC_INITF
:
string
:
=
"../../ip_cores/wr-cores/bin/wrpc/wrc_phy8.bram"
;
-- Simulation-mode enable parameter. Set by default (synthesis) to 0, and
...
...
@@ -274,9 +274,9 @@ entity svec_top is
fmc1_scl_b
:
inout
std_logic
;
fmc1_sda_b
:
inout
std_logic
);
end
entity
svec_
top
;
end
entity
svec_
fine_delay
;
architecture
arch
of
svec_
top
is
architecture
arch
of
svec_
fine_delay
is
component
fd_ddr_pll
port
(
...
...
@@ -420,7 +420,7 @@ begin -- architecture arch
g_DEVICE_ID
=>
x"574f_0002"
,
-- SVEC + 2xFineDelay
g_VERSION
=>
x"0300_0008"
,
g_CAPABILITIES
=>
x"0000_0000"
,
g_COMMIT_ID
=>
sourceid_svec_fine_delay_
top_
pkg
.
sourceid
)
g_COMMIT_ID
=>
sourceid_svec_fine_delay_pkg
.
sourceid
)
port
map
(
clk_i
=>
clk_sys_62m5
,
rst_n_i
=>
rst_sys_62m5_n
,
...
...
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