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FMC DEL 1ns 4cha
Commit e502cb54 authored by Tomasz Wlostowski's avatar Tomasz Wlostowski
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hdl/include/acam_model.sv
View file @ e502cb54
......@@ -187,7 +187,7 @@ module acam_model
hit = t_stop1 - t_start + rmode_start_offset * 3;
if(g_verbose)$display("acam::hit1 %d", hit);
if(g_verbose)$display("acam::hit1 %d t_stop1 %d t_start %d", hit, t_stop1, t_start);
if(q_hit.num() == 0) begin
#(c_empty_flag_delay);
......
hdl/include/fine_delay_regs.v
View file @ e502cb54
`define ADDR_FD_RSTR 7'h0
`define ADDR_FD_GCR 7'h4
`define ADDR_FD_RSTR 8'h0
`define ADDR_FD_IDR 8'h4
`define ADDR_FD_GCR 8'h8
`define FD_GCR_BYPASS_OFFSET 0
`define FD_GCR_BYPASS 32'h00000001
`define FD_GCR_INPUT_EN_OFFSET 1
`define FD_GCR_INPUT_EN 32'h00000002
`define FD_GCR_CLR_STAT_OFFSET 2
`define FD_GCR_CLR_STAT 32'h00000004
`define ADDR_FD_TAR 7'h8
`define FD_GCR_CSYNC_INT_OFFSET 2
`define FD_GCR_CSYNC_INT 32'h00000004
`define FD_GCR_CSYNC_WR_OFFSET 3
`define FD_GCR_CSYNC_WR 32'h00000008
`define FD_GCR_WR_READY_OFFSET 4
`define FD_GCR_WR_READY 32'h00000010
`define ADDR_FD_TAR 8'hc
`define FD_TAR_DATA_OFFSET 0
`define FD_TAR_DATA 32'h0fffffff
`define FD_TAR_ADDR_OFFSET 28
`define FD_TAR_ADDR 32'hf0000000
`define ADDR_FD_TDCSR 7'hc
`define ADDR_FD_TDCSR 8'h10
`define FD_TDCSR_WRITE_OFFSET 0
`define FD_TDCSR_WRITE 32'h00000001
`define FD_TDCSR_READ_OFFSET 1
......@@ -32,54 +37,156 @@
`define FD_TDCSR_STOP_DIS 32'h00000100
`define FD_TDCSR_STOP_EN_OFFSET 9
`define FD_TDCSR_STOP_EN 32'h00000200
`define ADDR_FD_DCR 7'h10
`define FD_DCR_DLY_SEL_OFFSET 0
`define FD_DCR_DLY_SEL 32'h0000000f
`define FD_DCR_DLY_VAL_OFFSET 4
`define FD_DCR_DLY_VAL 32'h00003ff0
`define ADDR_FD_GPSR 7'h14
`define FD_GPSR_CS_PLL_OFFSET 0
`define FD_GPSR_CS_PLL 32'h00000001
`define FD_GPSR_CS_GPIO_OFFSET 1
`define FD_GPSR_CS_GPIO 32'h00000002
`define FD_GPSR_SCLK_OFFSET 2
`define FD_GPSR_SCLK 32'h00000004
`define FD_GPSR_MOSI_OFFSET 3
`define FD_GPSR_MOSI 32'h00000008
`define ADDR_FD_GPCR 7'h18
`define FD_GPCR_CS_PLL_OFFSET 0
`define FD_GPCR_CS_PLL 32'h00000001
`define FD_GPCR_CS_GPIO_OFFSET 1
`define FD_GPCR_CS_GPIO 32'h00000002
`define FD_GPCR_SCLK_OFFSET 2
`define FD_GPCR_SCLK 32'h00000004
`define FD_GPCR_MOSI_OFFSET 3
`define FD_GPCR_MOSI 32'h00000008
`define ADDR_FD_GPRR 7'h1c
`define FD_GPRR_MISO_OFFSET 0
`define FD_GPRR_MISO 32'h00000001
`define ADDR_FD_IECRAW 7'h20
`define ADDR_FD_IECTAG 7'h24
`define ADDR_FD_IEPD 7'h28
`define ADDR_FD_PGCR 7'h2c
`define FD_PGCR_PERIOD_OFFSET 0
`define FD_PGCR_PERIOD 32'h7fffffff
`define FD_PGCR_ENABLE_OFFSET 31
`define FD_PGCR_ENABLE 32'h80000000
`define ADDR_FD_TSFIFO_R0 7'h30
`define FD_TSFIFO_R0_UTC_OFFSET 0
`define FD_TSFIFO_R0_UTC 32'hffffffff
`define ADDR_FD_TSFIFO_R1 7'h34
`define FD_TSFIFO_R1_COARSE_OFFSET 0
`define FD_TSFIFO_R1_COARSE 32'h0fffffff
`define ADDR_FD_TSFIFO_R2 7'h38
`define FD_TSFIFO_R2_FRAC_OFFSET 0
`define FD_TSFIFO_R2_FRAC 32'h007fffff
`define ADDR_FD_TSFIFO_R3 7'h3c
`define FD_TSFIFO_R3_FRAC_RAW_OFFSET 0
`define FD_TSFIFO_R3_FRAC_RAW 32'h007fffff
`define ADDR_FD_TSFIFO_CSR 7'h40
`define FD_TSFIFO_CSR_FULL_OFFSET 16
`define FD_TSFIFO_CSR_FULL 32'h00010000
`define FD_TSFIFO_CSR_EMPTY_OFFSET 17
`define FD_TSFIFO_CSR_EMPTY 32'h00020000
`define ADDR_FD_ADSFR 8'h14
`define ADDR_FD_ATMCR 8'h18
`define FD_ATMCR_C_THR_OFFSET 0
`define FD_ATMCR_C_THR 32'h0000000f
`define FD_ATMCR_F_THR_OFFSET 4
`define FD_ATMCR_F_THR 32'h07fffff0
`define ADDR_FD_ASOR 8'h1c
`define FD_ASOR_OFFSET_OFFSET 0
`define FD_ASOR_OFFSET 32'h007fffff
`define ADDR_FD_IECRAW 8'h20
`define ADDR_FD_IECTAG 8'h24
`define ADDR_FD_IEPD 8'h28
`define FD_IEPD_RST_STAT_OFFSET 0
`define FD_IEPD_RST_STAT 32'h00000001
`define FD_IEPD_PDELAY_OFFSET 1
`define FD_IEPD_PDELAY 32'h000001fe
`define ADDR_FD_RCRR 8'h2c
`define ADDR_FD_RCFR 8'h30
`define ADDR_FD_TSBCR 8'h34
`define FD_TSBCR_ENABLE_OFFSET 0
`define FD_TSBCR_ENABLE 32'h00000001
`define FD_TSBCR_PURGE_OFFSET 1
`define FD_TSBCR_PURGE 32'h00000002
`define FD_TSBCR_RST_SEQ_OFFSET 2
`define FD_TSBCR_RST_SEQ 32'h00000004
`define FD_TSBCR_FULL_OFFSET 3
`define FD_TSBCR_FULL 32'h00000008
`define FD_TSBCR_EMPTY_OFFSET 4
`define FD_TSBCR_EMPTY 32'h00000010
`define ADDR_FD_TSBR_U 8'h38
`define ADDR_FD_TSBR_C 8'h3c
`define ADDR_FD_TSBR_FID 8'h40
`define FD_TSBR_FID_FINE_OFFSET 0
`define FD_TSBR_FID_FINE 32'h00000fff
`define FD_TSBR_FID_SEQID_OFFSET 16
`define FD_TSBR_FID_SEQID 32'hffff0000
`define ADDR_FD_DCR1 8'h60
`define FD_DCR1_ENABLE_OFFSET 0
`define FD_DCR1_ENABLE 32'h00000001
`define FD_DCR1_MODE_OFFSET 1
`define FD_DCR1_MODE 32'h00000002
`define FD_DCR1_PG_ARM_OFFSET 2
`define FD_DCR1_PG_ARM 32'h00000004
`define FD_DCR1_PG_TRIG_OFFSET 3
`define FD_DCR1_PG_TRIG 32'h00000008
`define FD_DCR1_UPDATE_OFFSET 4
`define FD_DCR1_UPDATE 32'h00000010
`define FD_DCR1_UPD_DONE_OFFSET 5
`define FD_DCR1_UPD_DONE 32'h00000020
`define FD_DCR1_FORCE_CP_OFFSET 6
`define FD_DCR1_FORCE_CP 32'h00000040
`define FD_DCR1_POL_OFFSET 7
`define FD_DCR1_POL 32'h00000080
`define ADDR_FD_FRR1 8'h64
`define ADDR_FD_U_START1 8'h68
`define ADDR_FD_C_START1 8'h6c
`define ADDR_FD_F_START1 8'h70
`define ADDR_FD_U_END1 8'h74
`define ADDR_FD_C_END1 8'h78
`define ADDR_FD_F_END1 8'h7c
`define ADDR_FD_DCR2 8'h80
`define FD_DCR2_ENABLE_OFFSET 0
`define FD_DCR2_ENABLE 32'h00000001
`define FD_DCR2_MODE_OFFSET 1
`define FD_DCR2_MODE 32'h00000002
`define FD_DCR2_PG_ARM_OFFSET 2
`define FD_DCR2_PG_ARM 32'h00000004
`define FD_DCR2_PG_TRIG_OFFSET 3
`define FD_DCR2_PG_TRIG 32'h00000008
`define FD_DCR2_UPDATE_OFFSET 4
`define FD_DCR2_UPDATE 32'h00000010
`define FD_DCR2_UPD_DONE_OFFSET 5
`define FD_DCR2_UPD_DONE 32'h00000020
`define FD_DCR2_FORCE_CP_OFFSET 6
`define FD_DCR2_FORCE_CP 32'h00000040
`define FD_DCR2_POL_OFFSET 7
`define FD_DCR2_POL 32'h00000080
`define ADDR_FD_FRR2 8'h84
`define ADDR_FD_U_START2 8'h88
`define ADDR_FD_C_START2 8'h8c
`define ADDR_FD_F_START2 8'h90
`define ADDR_FD_U_END2 8'h94
`define ADDR_FD_C_END2 8'h98
`define ADDR_FD_F_END2 8'h9c
`define ADDR_FD_DCR3 8'ha0
`define FD_DCR3_ENABLE_OFFSET 0
`define FD_DCR3_ENABLE 32'h00000001
`define FD_DCR3_MODE_OFFSET 1
`define FD_DCR3_MODE 32'h00000002
`define FD_DCR3_PG_ARM_OFFSET 2
`define FD_DCR3_PG_ARM 32'h00000004
`define FD_DCR3_PG_TRIG_OFFSET 3
`define FD_DCR3_PG_TRIG 32'h00000008
`define FD_DCR3_UPDATE_OFFSET 4
`define FD_DCR3_UPDATE 32'h00000010
`define FD_DCR3_UPD_DONE_OFFSET 5
`define FD_DCR3_UPD_DONE 32'h00000020
`define FD_DCR3_FORCE_CP_OFFSET 6
`define FD_DCR3_FORCE_CP 32'h00000040
`define FD_DCR3_POL_OFFSET 7
`define FD_DCR3_POL 32'h00000080
`define ADDR_FD_FRR3 8'ha4
`define ADDR_FD_U_START3 8'ha8
`define ADDR_FD_C_START3 8'hac
`define ADDR_FD_F_START3 8'hb0
`define ADDR_FD_U_END3 8'hb4
`define ADDR_FD_C_END3 8'hb8
`define ADDR_FD_F_END3 8'hbc
`define ADDR_FD_DCR4 8'hc0
`define FD_DCR4_ENABLE_OFFSET 0
`define FD_DCR4_ENABLE 32'h00000001
`define FD_DCR4_MODE_OFFSET 1
`define FD_DCR4_MODE 32'h00000002
`define FD_DCR4_PG_ARM_OFFSET 2
`define FD_DCR4_PG_ARM 32'h00000004
`define FD_DCR4_PG_TRIG_OFFSET 3
`define FD_DCR4_PG_TRIG 32'h00000008
`define FD_DCR4_UPDATE_OFFSET 4
`define FD_DCR4_UPDATE 32'h00000010
`define FD_DCR4_UPD_DONE_OFFSET 5
`define FD_DCR4_UPD_DONE 32'h00000020
`define FD_DCR4_FORCE_CP_OFFSET 6
`define FD_DCR4_FORCE_CP 32'h00000040
`define FD_DCR4_POL_OFFSET 7
`define FD_DCR4_POL 32'h00000080
`define ADDR_FD_FRR4 8'hc4
`define ADDR_FD_U_START4 8'hc8
`define ADDR_FD_C_START4 8'hcc
`define ADDR_FD_F_START4 8'hd0
`define ADDR_FD_U_END4 8'hd4
`define ADDR_FD_C_END4 8'hd8
`define ADDR_FD_F_END4 8'hdc
`define ADDR_FD_EIC_IDR 8'he0
`define FD_EIC_IDR_TS_BUF_NOTEMPTY_OFFSET 0
`define FD_EIC_IDR_TS_BUF_NOTEMPTY 32'h00000001
`define ADDR_FD_EIC_IER 8'he4
`define FD_EIC_IER_TS_BUF_NOTEMPTY_OFFSET 0
`define FD_EIC_IER_TS_BUF_NOTEMPTY 32'h00000001
`define ADDR_FD_EIC_IMR 8'he8
`define FD_EIC_IMR_TS_BUF_NOTEMPTY_OFFSET 0
`define FD_EIC_IMR_TS_BUF_NOTEMPTY 32'h00000001
`define ADDR_FD_EIC_ISR 8'hec
`define FD_EIC_ISR_TS_BUF_NOTEMPTY_OFFSET 0
`define FD_EIC_ISR_TS_BUF_NOTEMPTY 32'h00000001
`define ADDR_FD_RAWFIFO_R0 8'hf0
`define FD_RAWFIFO_R0_FRAC_OFFSET 0
`define FD_RAWFIFO_R0_FRAC 32'h0fffffff
`define ADDR_FD_RAWFIFO_R1 8'hf4
`define FD_RAWFIFO_R1_COARSE_OFFSET 0
`define FD_RAWFIFO_R1_COARSE 32'h0fffffff
`define ADDR_FD_RAWFIFO_CSR 8'hf8
`define FD_RAWFIFO_CSR_EMPTY_OFFSET 17
`define FD_RAWFIFO_CSR_EMPTY 32'h00020000
hdl/include/ideal_timestamper.sv
View file @ e502cb54
`include "timestamp.svh"
module ideal_timestamper
(
input clk_ref_i,
......@@ -5,74 +7,78 @@ module ideal_timestamper
input enable_i,
input trig_a_i,
output reg [22:0] tag_frac_o,
output reg [27:0] tag_coarse_o,
output reg [31:0] tag_utc_o,
output tag_valid_p1_o,
output [27:0] cntr_coarse_o,
output [31:0] cntr_utc_o
input [31:0] csync_utc_i,
input [27:0] csync_coarse_i,
input csync_p1_i
);
parameter real g_frac_resolution = 80.9553ps/3.0;
parameter g_frac_range = 4096;
parameter g_coarse_range = 256;
const time c_frac_step = 8ns / g_frac_range;
reg [27:0] cntr_coarse;
reg [31:0] cntr_utc;
reg [22:0] cntr_frac;
reg [12:0] cntr_frac;
reg tag_valid_p1;
typedef struct {
reg [27:0] coarse;
reg [31:0] utc;
reg [22:0] frac;
} timestamp_t;
timestamp_t ts_queue[$] = '{};
Timestamp ts_queue[$];
always@(posedge clk_ref_i)
if(!rst_n_i)
begin
cntr_coarse <= 0;
cntr_utc <= 0;
cntr_frac <= 0;
tag_valid_p1 <= 0;
ts_queue = '{};
cntr_coarse <= 0;
cntr_utc <= 0;
cntr_frac <= 0;
tag_valid_p1 <= 0;
ts_queue = '{};
end
always@(posedge clk_ref_i)
cntr_frac <= 0;
cntr_frac <= 0;
always@(posedge clk_ref_i)
if(rst_n_i)
begin
if(cntr_coarse == 125000000 - 1) begin
cntr_coarse <= 0;
cntr_utc <= cntr_utc + 1;
if(!rst_n_i) begin
cntr_coarse <= 0;
cntr_utc <= 0;
end else begin
if(csync_p1_i)
begin
cntr_coarse <= csync_coarse_i+1;
cntr_utc <= csync_utc_i;
end else if(cntr_coarse == g_coarse_range) begin
cntr_coarse <= 1;
cntr_utc <= cntr_utc + 1;
end else if(cntr_coarse == g_coarse_range - 1) begin
cntr_coarse <= 0;
cntr_utc <= cntr_utc + 1;
end else
cntr_coarse <= cntr_coarse + 1;
cntr_coarse <= cntr_coarse + 1;
end
initial forever begin
#(g_frac_resolution) cntr_frac <= cntr_frac + 1;
end
initial forever #(c_frac_step) cntr_frac <= cntr_frac + 1;
always@(posedge trig_a_i) begin
if(enable_i)
begin
timestamp_t ts;
ts.frac = cntr_frac;
ts.coarse = cntr_coarse;
ts.utc = cntr_utc;
Timestamp ts;
ts = new (cntr_utc, cntr_coarse, cntr_frac);
ts_queue.push_back(ts);
end
end
function int poll();
return (ts_queue.size() > 0);
endfunction // poll
function Timestamp get();
return ts_queue.pop_front();
endfunction // get
/* -----\/----- EXCLUDED -----\/-----
always@(posedge clk_ref_i)
if(tag_valid_p1)
tag_valid_p1 <= 0;
......@@ -90,5 +96,6 @@ module ideal_timestamper
assign tag_valid_p1_o = tag_valid_p1;
assign cntr_coarse_o = cntr_coarse;
assign cntr_utc_o = cntr_utc;
-----/\----- EXCLUDED -----/\----- */
endmodule // ideal_timestamper
hdl/include/mc100ep195.sv
View file @ e502cb54
......@@ -19,7 +19,7 @@ module mc100ep195
always@(len)
if(len)
if(!len)
cur_dly <= delay;
always@(i)
......
hdl/include/random_pulse_gen.sv
View file @ e502cb54
......@@ -17,7 +17,7 @@ module random_pulse_gen
begin
real delta;
seed = $urandom(seed);
delta = $dist_uniform(seed, g_min_spacing + g_pulse_width, g_max_spacing + g_pulse_width);
delta = $dist_uniform(seed, g_min_spacing - g_pulse_width, g_max_spacing - g_pulse_width);
pulse_o = 1;
#(g_pulse_width);
pulse_o = 0;
......
hdl/include/timestamp.svh 0 → 100644
View file @ e502cb54
`ifndef __TIMESTAMP_SVH
`define __TIMESTAMP_SVH
class Timestamp;
int utc, coarse, frac, coarse_range, seq_id;
function new(int _utc=0 ,int _coarse=0, int _frac=0,int _seq_id = 0, int _coarse_range = 256);
utc = _utc;
coarse = _coarse;
frac = _frac;
coarse_range = _coarse_range;
seq_id = _seq_id;
endfunction // new
function real flatten();
return real'(utc) * real'(coarse_range * 8) + real'(coarse) * 8.0 + (real'(frac)/4096.0 * 8.0);
endfunction // flatten
task unflatten(int x);
int t;
t =x;
frac = x % 4096;
x = x - frac;
x = x/4096;
coarse = x % 256;
x = x - coarse;
x = x/256;
utc = x;
$display("Unflat: %d %d %d %d", t, utc, coarse, frac);
endtask // unflatten
function Timestamp sub(Timestamp b);
endfunction
endclass
`endif // `ifndef __TIMESTAMP_SVH
hdl/rtl/Manifest.py
View file @ e502cb54
files = ["fd_acam_timestamper.vhd",
"fd_cal_pulse_gen.vhd",
"fd_delay_line_driver.vhd",
"fd_wbgen2_pkg.vhd",
"fine_delay_core.vhd",
"fd_ring_buffer.vhd",
"fd_ts_adder.vhd",
"fd_ts_normalizer.vhd",
"fd_reset_generator.vhd",
"fd_csync_generator.vhd",
"fd_timestamper_stat_unit.vhd",
"fd_acam_timestamp_postprocessor.vhd",
"fd_delay_channel_driver.vhd",
"fd_delay_line_arbiter.vhd",
"fd_rearm_generator.vhd",
"fd_wishbone_slave.vhd",
"fine_delay_pkg.vhd",
"fine_delay_wb.vhd"]
"fine_delay_core.vhd"];
fetchto = "../ip_cores"
modules = {
"git" : [
"git@ohwr.org:hdl-core-lib/wr-cores.git",
"git@ohwr.org:hdl-core-lib/general-cores.git" ],
"svn" : [ "http://svn.ohwr.org/gn4124-core/branches/hdlmake-compliant/rtl" ]
}
"git" : [
"git@ohwr.org:hdl-core-lib/wr-cores.git",
"git@ohwr.org:hdl-core-lib/general-cores.git" ],
"svn" : [ "http://svn.ohwr.org/gn4124-core/branches/hdlmake-compliant/rtl" ]
};
hdl/rtl/fd_acam_timestamp_postprocessor.vhd
View file @ e502cb54
-------------------------------------------------------------------------------
-- Title : ACAM TDX-GPX timestamp postprocessor
-- Project : Fine Delay Core (FmcDelay1ns4cha)
-------------------------------------------------------------------------------
-- File : fd_acam_timestamp_postprocessor.vhd
-- Author : Tomasz Wlostowski
-- Company : CERN
-- Created : 2011-08-29
-- Last update: 2011-09-07
-- Platform : FPGA-generic
-- Standard : VHDL'93
-------------------------------------------------------------------------------
-- Description: Merges the coarse timestamp produced with the internal FPGA
-- counter with the fractional part obtained from the ACAM TDC, generating a final
-- UTC timestamp used for further processing.
-------------------------------------------------------------------------------
--
-- Copyright (c) 2011 CERN / BE-CO-HT
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
-- Public License as published by the Free Software Foundation;
-- either version 2.1 of the License, or (at your option) any
-- later version.
--
-- This source is distributed in the hope that it will be
-- useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
-- PURPOSE. See the GNU Lesser General Public License for more
-- details.
--
-- You should have received a copy of the GNU Lesser General
-- Public License along with this source; if not, download it
-- from http://www.gnu.org/licenses/lgpl-2.1.html
--
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2011-08-29 1.0 twlostow Created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.fd_wbgen2_pkg.all;
entity fd_acam_timestamp_postprocessor is
generic(
-- number of the bits in the fractional part
g_frac_bits : integer := 12);
port(
clk_ref_i : in std_logic;
rst_n_i : in std_logic;
-- Timestamp input, from the ACAM FSM
raw_valid_i : in std_logic;
raw_utc_i : in std_logic_vector(31 downto 0);
raw_coarse_i : in std_logic_vector(23 downto 0);
raw_frac_i : in std_logic_vector(22 downto 0);
---------------------------------------------------------------------------
-- Timestamp input, from the ACAM FS
---------------------------------------------------------------------------
raw_valid_i : in std_logic;
raw_utc_i : in std_logic_vector(31 downto 0);
-- "start number" (value of coarse counter, counting at every start pulse of the
-- TDC, i.e. 125 MHz / 16 = 7.8215 MHz)
raw_coarse_i : in std_logic_vector(23 downto 0);
-- raw fractional timestamp generated by ACAM
raw_frac_i : in std_logic_vector(22 downto 0);
-- coarse offset (in 125 MHz clock cycles) from the last ACAM's start pulse to the
-- input pulse (0..15)
raw_start_offset_i : in std_logic_vector(3 downto 0);
-- Offset between the actual timescale and the ACAM start signal generated
-- by the AD9516 PLL
-- Offset between the actual timescale and the ACAM fixed start signal generated
-- by the AD9516 PLL. Used to align the timestamps to the externally
-- provided time base (e.g. by White Rabbit).
acam_subcycle_offset_i : in std_logic_vector(4 downto 0);
---------------------------------------------------------------------------
-- Post-processed timestamp. WARNING! DE-NORMALIZED!
---------------------------------------------------------------------------
tag_valid_o : out std_logic;
tag_utc_o : out std_logic_vector(31 downto 0);
tag_coarse_o : out std_logic_vector(27 downto 0);
tag_frac_o : out std_logic_vector(g_frac_bits-1 downto 0);
regs_b : t_fd_registers
-- Wishbone regs
regs_i : in t_fd_out_registers
);
end fd_acam_timestamp_postprocessor;
architecture behavioral of fd_acam_timestamp_postprocessor is
-- number of the fractional bits to ignore in the rescaled ACAM's fractional
-- timestamp
constant c_SCALER_SHIFT : integer := 12;
signal pp_pipe : std_logic_vector(3 downto 0);
signal post_tag_coarse : unsigned(27 downto 0);
signal post_tag_frac : unsigned(g_frac_bits-1 downto 0);
signal post_tag_utc : unsigned(31 downto 0);
signal post_frac_multiplied : signed(c_SCALER_SHIFT + g_frac_bits + 8 downto 0);
signal post_frac_start_adj : signed(22 downto 0);
signal post_tag_coarse : unsigned(27 downto 0);
signal post_tag_frac : unsigned(g_frac_bits-1 downto 0);
signal post_tag_utc : unsigned(31 downto 0);
signal post_frac_multiplied : signed(c_SCALER_SHIFT + g_frac_bits + 8 downto 0);
signal post_frac_multiplied_d0 : signed(c_SCALER_SHIFT + g_frac_bits + 8 downto 0);
signal post_frac_start_adj : signed(22 downto 0);
begin -- behavioral
p_postprocess_tags : process(clk_ref_i)
begin
if rising_edge(clk_ref_i) then
......@@ -64,26 +124,31 @@ begin -- behavioral
pp_pipe(0) <= raw_valid_i;
post_frac_start_adj <= signed(raw_frac_i) - signed(regs_b.asor_offset_o);
post_frac_start_adj <= signed(raw_frac_i) - signed(regs_i.asor_offset_o);
post_tag_coarse(3 downto 0) <= (others => '0');
post_tag_utc <= unsigned(raw_utc_i);
-- pipeline stage 2:
-- - check for the "wraparound" condition and adjust the coarse start counter
-- - check for the "wraparound" condition and adjust the coarse start counter.
-- Wraparound occurs when the ACAM's hasn't yet accounted for the next start pulse
-- (resulting with a value of the fractional timestamp close to the upper
-- bound), but the FPGA counter had already "noticed" the next start. This
-- happens because of different routing delays and jitter.
pp_pipe(1) <= pp_pipe(0);
if (unsigned(raw_start_offset_i) <= unsigned(regs_b.atmcr_c_thr_o)) and (post_frac_start_adj > signed(regs_b.atmcr_f_thr_o)) then
if (unsigned(raw_start_offset_i) <= unsigned(regs_i.atmcr_c_thr_o)) and (post_frac_start_adj > signed(regs_i.atmcr_f_thr_o)) then
post_tag_coarse(post_tag_coarse'left downto 4) <= unsigned(raw_coarse_i) - 1;
else
post_tag_coarse(post_tag_coarse'left downto 4) <= unsigned(raw_coarse_i);
end if;
-- pipeline stage 3:
-- rescale the fractional part to our internal time base
-- rescale the fractional part to our internal time base
pp_pipe(2) <= pp_pipe(1);
post_frac_multiplied <= resize(signed(post_frac_start_adj) * signed(regs_b.adsfr_o), post_frac_multiplied'length);
pp_pipe(2) <= pp_pipe(1);
post_frac_multiplied <= resize(signed(post_frac_start_adj) * signed(regs_i.adsfr_o), post_frac_multiplied'length);
-- post_frac_multiplied_d0 <= post_frac_multiplied;
-- pipeline stage 4:
-- - split the rescaled fractional part into the (mod 4096) tag_frac_o and add
......@@ -94,7 +159,7 @@ begin -- behavioral
tag_utc_o <= std_logic_vector(post_tag_utc);
tag_coarse_o <= std_logic_vector(
signed(post_tag_coarse) -- index of start pulse (mod 16 = 0)
+ signed(acam_subcycle_offset_i) -- start-to-timescale offset
+ signed(acam_subcycle_offset_i) -- start-to-timescale offset
+ signed(post_frac_multiplied(post_frac_multiplied'left downto c_SCALER_SHIFT + g_frac_bits)));
-- extra coarse counts from ACAM's frac part after rescaling
......
hdl/rtl/fd_acam_timestamper.vhd
View file @ e502cb54
......@@ -6,26 +6,25 @@
-- Author : Tomasz Wlostowski
-- Company : CERN
-- Created : 2011-08-24
-- Last update: 2011-08-31
-- Last update: 2011-09-09
-- Platform : FPGA-generic
-- Standard : VHDL'93
-------------------------------------------------------------------------------
-- Description: A complete sub-nanosecond pulse timestamper based on ACAM's
-- TDC-GPX chip.
-- Description: A complete sub-nanosecond pulse timestamper using ACAM's
-- TDC-GPX chip for fine delay measurement and a simple counter to capture the
-- coarse part. See comments inside the RTL code for the details.
-------------------------------------------------------------------------------
-- Copyright (c) 2011 CERN / BE-CO-HT
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2011-08-24 1.0 slayer Created
-- Date Version Author Description
-- 2011-08-24 1.0 twlostow Created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all; -- for real types, used in
-- precalculation of scalefactors
use work.fd_wbgen2_pkg.all; -- for Wishbone regs
......@@ -34,9 +33,11 @@ library work;
entity fd_acam_timestamper is
generic(
-- minimum input pulse width in clk_ref_i cycles
g_min_pulse_width : natural := 3; -- clk_ref_i frequency in Hz
g_min_pulse_width : natural := 3;
-- clk_ref_i frequency in Hz
g_clk_ref_freq : integer := 125000000;
g_frac_bits : integer := 13
-- size of the fractional (< 8 ns) part of the timestamp
g_frac_bits : integer := 12
);
port (
......@@ -48,8 +49,7 @@ entity fd_acam_timestamper is
clk_ref_i : in std_logic;
-- reset, active LOW
rst_n_i : in std_logic;
rst_n_i : in std_logic;
-- Inverted ACAM trigger input
trig_a_n_i : in std_logic;
......@@ -124,48 +124,24 @@ entity fd_acam_timestamper is
-- csync_utc_i.
csync_p1_i : in std_logic;
-- Indication of the TDC start period
tdc_start_p1_o : out std_logic;
---------------------------------------------------------------------------
-- Wishbone registers
---------------------------------------------------------------------------
regs_b : inout t_fd_registers
regs_i : in t_fd_out_registers;
regs_o : out t_fd_in_registers;
dbg_o : out std_logic_vector(3 downto 0)
);
end fd_acam_timestamper;
architecture behavioral of fd_acam_timestamper is
component fd_ts_adder
generic (
g_frac_bits : integer;
g_coarse_bits : integer;
g_utc_bits : integer;
g_coarse_range : integer);
port (
clk_i : in std_logic;
rst_n_i : in std_logic;
valid_i : in std_logic;
a_utc_i : in std_logic_vector(g_utc_bits-1 downto 0);
a_coarse_i : in std_logic_vector(g_coarse_bits-1 downto 0);
a_frac_i : in std_logic_vector(g_frac_bits-1 downto 0);
b_utc_i : in std_logic_vector(g_utc_bits-1 downto 0);
b_coarse_i : in std_logic_vector(g_coarse_bits-1 downto 0);
b_frac_i : in std_logic_vector(g_frac_bits-1 downto 0);
valid_o : out std_logic;
q_utc_o : out std_logic_vector(g_utc_bits-1 downto 0);
q_coarse_o : out std_logic_vector(g_coarse_bits-1 downto 0);
q_frac_o : out std_logic_vector(g_frac_bits-1 downto 0));
end component;
component fd_timestamper_stat_unit
port (
clk_ref_i : in std_logic;
rst_n_i : in std_logic;
trig_pulse_i : in std_logic;
raw_tag_valid_i : in std_logic;
regs_b : inout t_fd_registers);
end component;
component fd_acam_timestamp_postprocessor
generic (
g_frac_bits : integer);
......@@ -182,7 +158,17 @@ architecture behavioral of fd_acam_timestamper is
tag_utc_o : out std_logic_vector(31 downto 0);
tag_coarse_o : out std_logic_vector(27 downto 0);
tag_frac_o : out std_logic_vector(g_frac_bits-1 downto 0);
regs_b : t_fd_registers);
regs_i : in t_fd_out_registers);
end component;
component fd_timestamper_stat_unit
port (
clk_ref_i : in std_logic;
rst_n_i : in std_logic;
trig_pulse_i : in std_logic;
raw_tag_valid_i : in std_logic;
regs_i : in t_fd_out_registers;
regs_o : out t_fd_in_registers);
end component;
constant c_ACAM_TIMEOUT : integer := 60;
......@@ -207,9 +193,10 @@ architecture behavioral of fd_acam_timestamper is
signal advance_coarse : std_logic;
-- delay/sync chains
signal tdc_start_d : std_logic_vector(2 downto 0);
signal trig_d : std_logic_vector(2 downto 0);
signal acam_ef_d : std_logic_vector(1 downto 0);
signal tdc_start_d : std_logic_vector(2 downto 0);
signal trig_d : std_logic_vector(2 downto 0);
signal acam_ef_d : std_logic_vector(1 downto 0);
signal tag_enable_d : std_logic_vector(2 downto 0);
signal trig_pulse : std_logic;
......@@ -219,6 +206,8 @@ architecture behavioral of fd_acam_timestamper is
signal utc_count : unsigned(31 downto 0);
signal subcycle_offset : signed(4 downto 0);
signal gcr_input_en_d0 : std_logic;
-- raw time tag (unprocessed)
signal raw_tag_valid : std_logic;
signal raw_tag_coarse : unsigned(23 downto 0);
......@@ -241,11 +230,14 @@ architecture behavioral of fd_acam_timestamper is
signal dbg_utc : unsigned(31 downto 0);
signal dbg_coarse : unsigned(27 downto 0);
signal regs_out_int : t_fd_in_registers;
signal regs_out_stat : t_fd_in_registers;
signal tag_valid_int : std_logic;
begin -- behave
regs_b <= c_fd_registers_init_value;
-- Process: p_sync_trigger
-- Inputs: trig_a_n_i, tag_enable
-- Outputs: trig_pulse, trig_d
......@@ -258,10 +250,21 @@ begin -- behave
p_sync_trigger : process(clk_ref_i)
begin
if rising_edge(clk_ref_i) then
trig_d(0) <= trig_a_n_i or (not tag_enable);
trig_d(1) <= not trig_d(0) and tag_enable;
trig_d(2) <= trig_d(1) and tag_enable;
trig_pulse <= (trig_d(1) and not trig_d(2)) and tag_enable;
if(rst_n_i = '0') then
trig_d <= (others => '0');
trig_pulse <= '0';
tag_enable_d <= (others => '0');
else
trig_d(0) <= trig_a_n_i or (not tag_enable);
trig_d(1) <= not trig_d(0) and tag_enable_d(0);
trig_d(2) <= trig_d(1) and tag_enable_d(1);
trig_pulse <= (trig_d(1) and not trig_d(2)) and tag_enable_d(2);
tag_enable_d(0) <= tag_enable;
tag_enable_d(1) <= tag_enable_d(0);
tag_enable_d(2) <= tag_enable_d(1);
end if;
end if;
end process;
......@@ -283,17 +286,17 @@ begin -- behave
else
-- the host wrote '1' to stop_dis bit in TDCSR - disable stop input
if(regs_b.tdcsr_stop_dis_o = '1') then
if(regs_i.tdcsr_stop_dis_o = '1') then
host_stop_dis <= '1';
-- the host wrote '1' to stop_en bit - enable stop input
elsif(regs_b.tdcsr_stop_en_o = '1') then
elsif(regs_i.tdcsr_stop_en_o = '1') then
host_stop_dis <= '0';
end if;
-- the same for start disable signal
if(regs_b.tdcsr_start_dis_o = '1') then
if(regs_i.tdcsr_start_dis_o = '1') then
host_start_dis <= '1';
elsif(regs_b.tdcsr_start_en_o = '1') then
elsif(regs_i.tdcsr_start_en_o = '1') then
host_start_dis <= '0';
end if;
end if;
......@@ -316,7 +319,7 @@ begin -- behave
acam_stop_dis_o <= '1';
else
if(regs_b.gcr_bypass_o = '1') then -- the TDC is controlled by the host
if(regs_i.gcr_bypass_o = '1') then -- the TDC is controlled by the host
acam_stop_dis_o <= host_stop_dis;
else
......@@ -324,7 +327,7 @@ begin -- behave
-- - the trigger input is enabled by the host
-- - timestamping has not been disabled by the delay unit
-- - we have generated at least one valid TDC start pulse
if(regs_b.gcr_input_en_o = '0' or tag_enable = '0' or start_ok = '0') then
if(regs_i.gcr_input_en_o = '0' or tag_enable = '0' or start_ok = '0') then
acam_stop_dis_o <= '1';
else
acam_stop_dis_o <= '0';
......@@ -376,7 +379,7 @@ begin -- behave
begin
if rising_edge(clk_ref_i) then
if rst_n_i = '0' or regs_b.gcr_bypass_o = '1' then
if rst_n_i = '0' or regs_i.gcr_bypass_o = '1' then
start_count <= (others => '0');
subcycle_offset <= (others => '0');
advance_coarse <= '0';
......@@ -400,6 +403,19 @@ begin -- behave
end if;
end process;
p_gen_tdc_start_output : process(clk_ref_i)
begin
if rising_edge(clk_ref_i) then
if rst_n_i = '0' then
tdc_start_p1_o <= '0';
elsif(start_count = x"e") then
tdc_start_p1_o <= '1';
else
tdc_start_p1_o <= '0';
end if;
end if;
end process;
p_gen_acam_start_dis : process(clk_ref_i)
begin
if rising_edge(clk_ref_i) then
......@@ -407,7 +423,7 @@ begin -- behave
start_ok_sreg <= (others => '0');
acam_start_dis_o <= '1';
else
if(regs_b.gcr_bypass_o = '1' or regs_b.gcr_input_en_o = '0') then
if(regs_i.gcr_bypass_o = '1' or regs_i.gcr_input_en_o = '0') then
acam_start_dis_o <= host_start_dis;
start_ok_sreg <= (others => '0');
else
......@@ -425,7 +441,7 @@ begin -- behave
p_coarse_counter : process(clk_ref_i)
begin
if rising_edge(clk_ref_i) then
if rst_n_i = '0' or regs_b.gcr_bypass_o = '1' then
if rst_n_i = '0' or regs_i.gcr_bypass_o = '1' then
coarse_count <= (others => '0');
else
......@@ -472,8 +488,8 @@ begin -- behave
if(rst_n_i = '0') then
acam_wdata <= (others => '0');
else
if(regs_b.tar_data_load_o = '1') then
acam_wdata <= regs_b.tar_data_o;
if(regs_i.tar_data_load_o = '1') then
acam_wdata <= regs_i.tar_data_o;
end if;
end if;
end if;
......@@ -490,7 +506,7 @@ begin -- behave
if(rst_n_i = '0') then
afsm_state <= IDLE;
regs_b.tar_data_i <= (others => '0');
regs_out_int.tar_data_i <= (others => '0');
acam_d_oe_o <= '0';
acam_d_o <= (others => '0');
......@@ -509,25 +525,30 @@ begin -- behave
raw_tag_frac <= (others => '0');
tag_enable <= '0';
gcr_input_en_d0 <= '0';
else
gcr_input_en_d0 <= regs_i.gcr_input_en_o;
case afsm_state is
when IDLE =>
raw_tag_valid <= '0';
-- TDC controlled by the host
if(regs_b.gcr_bypass_o = '1') then
if(regs_i.gcr_bypass_o = '1') then
acam_reset_int <= '0';
tag_enable <= '0';
if(regs_b.tdcsr_write_o = '1') then
if(regs_i.tdcsr_write_o = '1') then
afsm_state <= W_DATA_ADDR;
elsif(regs_b.tdcsr_read_o = '1') then
elsif(regs_i.tdcsr_read_o = '1') then
afsm_state <= R_ADDR;
end if;
-- TDC working in R-Mode and handled by the FD logic
elsif(regs_b.gcr_input_en_o = '1') then
elsif(regs_i.gcr_input_en_o = '1') then
acam_reset_int <= '0';
acam_a_o <= x"8"; -- permamently select FIFO1 register
......@@ -535,7 +556,7 @@ begin -- behave
acam_rd_n_o <= '1';
acam_wr_n_o <= '1';
if(tag_rearm_p1_i = '1') then
if(tag_rearm_p1_i = '1' or gcr_input_en_d0 = '1') then
tag_enable <= '1';
end if;
......@@ -571,12 +592,12 @@ begin -- behave
-- something arrived into the ACAM FIFO. Note that here we're using a
-- synchronized version of the signal, as it can go up anytime (the processing
-- delay of the ACAM is not constant). This worsens the overall timestamping
-- latency, but ensures the whole FSM will work correctly.
-- latency, but ensures that the whole FSM will work correctly.
if(acam_ef_d(1) = '0')then -- FIFO not empty
-- check the pulse width. If its too low, purge all timestamps from the FIFO
-- (the pulse might have been as well a series of short pulses, which FPGA
-- (the "pulse" might have been as well a series of short pulses, which FPGA
-- didn't notice but the TDC did)
if(width_check_mask /= c_ones(width_check_mask'left downto 0)) then
......@@ -590,7 +611,7 @@ begin -- behave
end if;
-- if the FIFO stays empty for too long after the input event, something must have
-- gone horriby wrong (a glitch?). There we have a timeout counter to make sure
-- gone horribly wrong (a glitch?). There we have a timeout counter to make sure
-- the FSM won't get stuck.
else
timeout_counter <= timeout_counter + 1;
......@@ -653,7 +674,7 @@ begin -- behave
when W_DATA_ADDR =>
acam_d_o <= acam_wdata;
acam_a_o <= regs_b.tar_addr_o;
acam_a_o <= regs_i.tar_addr_o;
acam_d_oe_o <= '1';
afsm_state <= W_PULSE;
......@@ -668,9 +689,10 @@ begin -- behave
afsm_state <= IDLE;
when R_ADDR =>
acam_a_o <= regs_b.tar_addr_o;
acam_a_o <= regs_i.tar_addr_o;
acam_d_oe_o <= '0';
afsm_state <= R_PULSE;
when R_PULSE =>
acam_cs_n_o <= '0';
acam_rd_n_o <= '0';
......@@ -680,10 +702,10 @@ begin -- behave
afsm_state <= R_READ;
when R_READ =>
acam_cs_n_o <= '1';
acam_rd_n_o <= '1';
regs_b.tar_data_i <= acam_d_i;
afsm_state <= IDLE;
acam_cs_n_o <= '1';
acam_rd_n_o <= '1';
regs_out_int.tar_data_i <= acam_d_i;
afsm_state <= IDLE;
when others => null;
end case;
......@@ -691,6 +713,10 @@ begin -- behave
end if;
end process;
dbg_o(0) <= raw_tag_valid;
dbg_o(1) <= trig_d(2);
dbg_o(2) <= tag_valid_int;
acam_alutrigger_o <= acam_reset_int;
U_Stat_Unit : fd_timestamper_stat_unit
......@@ -699,7 +725,8 @@ begin -- behave
rst_n_i => rst_n_i,
trig_pulse_i => trig_pulse,
raw_tag_valid_i => raw_tag_valid,
regs_b => regs_b);
regs_i => regs_i,
regs_o => regs_out_stat);
U_Timestamp_Postprocessor : fd_acam_timestamp_postprocessor
generic map (
......@@ -713,13 +740,20 @@ begin -- behave
raw_frac_i => std_logic_vector(raw_tag_frac),
raw_start_offset_i => std_logic_vector(raw_tag_start_offset),
acam_subcycle_offset_i => std_logic_vector(subcycle_offset),
tag_valid_o => tag_valid_o,
tag_valid_o => tag_valid_int,
tag_utc_o => tag_utc_o,
tag_coarse_o => tag_coarse_o,
tag_frac_o => tag_frac_o,
regs_b => regs_b);
regs_i => regs_i);
regs_o <= regs_out_stat or regs_out_int; -- combine the two stucts
regs_out_int.rawfifo_wr_req_i <= raw_tag_valid and not regs_i.rawfifo_wr_full_o;
regs_out_int.rawfifo_frac_i(22 downto 0) <= std_logic_vector(raw_tag_frac);
regs_out_int.rawfifo_frac_i(27 downto 23) <= (others => '0');
regs_out_int.rawfifo_coarse_i <= std_logic_vector(raw_tag_coarse) & std_logic_vector(raw_tag_start_offset);
tag_valid_o <= tag_valid_int;
end behavioral;
hdl/rtl/fd_cal_pulse_gen.vhd deleted 100644 → 0
View file @ c864d026
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity fd_cal_pulse_gen is
port(
clk_sys_i : in std_logic;
rst_n_i : in std_logic;
pulse_o : out std_logic;
pgcr_enable_i : in std_logic;
pgcr_period_i : in std_logic_vector(30 downto 0)
);
end fd_cal_pulse_gen;
architecture behavioral of fd_cal_pulse_gen is
signal counter : unsigned(30 downto 0);
signal pulse_int : std_logic;
begin -- behavioral
process(clk_sys_i)
begin
if rising_edge(clk_sys_i) then
if rst_n_i = '0' or pgcr_enable_i = '0' then
pulse_int <= '0';
counter <= to_unsigned(1, counter'length);
else
if(counter = unsigned(pgcr_period_i)) then
counter <= to_unsigned(1, counter'length);
pulse_int <= not pulse_int;
else
counter <= counter + 1;
end if;
pulse_o <= pulse_int;
end if;
end if;
end process;
end behavioral;
hdl/rtl/fd_csync_generator.vhd
View file @ e502cb54
-------------------------------------------------------------------------------
-- Title : Counter Sync signal generator
-- Project : Fine Delay FMC (fmc-delay-1ns-4cha)
-------------------------------------------------------------------------------
-- File : fd_csync_generator.vhd
-- Author : Tomasz Wlostowski
-- Company : CERN
-- Created : 2011-08-24
-- Last update: 2011-09-09
-- Platform : FPGA-generic
-- Standard : VHDL'93
-------------------------------------------------------------------------------
-- Description: Generates the internal time base used to synchronize the TDC
-- and the delayed pulse generators to an internal or WR-provided timescale.
-------------------------------------------------------------------------------
-- Copyright (c) 2011 CERN / BE-CO-HT
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2011-08-24 1.0 twlostow Created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
......@@ -7,27 +29,32 @@ use work.fd_wbgen2_pkg.all;
entity fd_csync_generator is
generic (
g_coarse_range : integer;
g_frac_bits : integer);
-- coarse counter range (0..g_coarse_range-1)
g_coarse_range : integer);
port(
clk_ref_i : in std_logic;
rst_n_i : in std_logic;
-- White Rabbit Counter sync input
-- when HI, wr_utc_i and wr_coarse_i contain a valid time value and
-- clk_ref_i is in-phase with the remote WR master
wr_time_valid_i : in std_logic;
wr_utc_i : in std_logic_vector(31 downto 0);
wr_coarse_i : in std_logic_vector(27 downto 0);
-- CSYNC Output
-- Counter sync output. HI Pulse = load internal counter with values from
-- csync_utc_o and csync_coarse_o.
csync_p1_o : out std_logic;
csync_utc_o : out std_logic_vector(31 downto 0);
csync_coarse_o : out std_logic_vector(27 downto 0);
regs_b : inout t_fd_registers);
-- Wishbone regs
regs_i : in t_fd_out_registers;
regs_o : out t_fd_in_registers);
end fd_csync_generator;
architecture behavioral of fd_csync_generator is
constant c_ADDER_PIPELINE_DELAY : integer := 4;
......@@ -64,8 +91,6 @@ architecture behavioral of fd_csync_generator is
begin -- behavioral
regs_b <= c_fd_registers_init_value;
U_Timescale_Adjust : fd_ts_adder
generic map (
g_frac_bits => 2,
......@@ -87,7 +112,7 @@ begin -- behavioral
q_coarse_o => csync_coarse_o,
q_frac_o => open);
regs_b.gcr_wr_ready_i <= wr_time_valid_i;
regs_o.gcr_wr_ready_i <= wr_time_valid_i;
process(clk_ref_i)
begin
......@@ -96,21 +121,21 @@ begin -- behavioral
coarse <= (others => '0');
utc <= (others => '0');
else
if(regs_b.gcr_csync_wr_o = '1' and wr_time_valid_i = '1') then
if(regs_i.gcr_csync_wr_o = '1' and wr_time_valid_i = '1') then
utc <= unsigned(wr_utc_i);
coarse <= unsigned(wr_coarse_i) + 1;
csync_int <= '1';
elsif(coarse = g_coarse_range) then -- unlike, but may happen after WR csync
coarse <= to_unsigned(1, coarse'length);
utc <= utc + 1;
csync_int <= regs_b.gcr_csync_int_o;
csync_int <= regs_i.gcr_csync_int_o;
elsif(coarse = g_coarse_range-1) then
coarse <= (others => '0');
utc <= utc + 1;
csync_int <= regs_b.gcr_csync_int_o;
csync_int <= regs_i.gcr_csync_int_o;
else
coarse <= coarse + 1;
csync_int <= regs_b.gcr_csync_int_o;
csync_int <= regs_i.gcr_csync_int_o;
end if;
end if;
end if;
......
hdl/rtl/fd_delay_channel_driver.vhd 0 → 100644
View file @ e502cb54
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.fine_delay_pkg.all;
entity fd_delay_channel_driver is
generic(
g_frac_bits : integer;
g_coarse_range : integer);
port(
clk_ref_i : in std_logic;
rst_n_i : in std_logic;
-- time base synchronization
csync_p1_i : in std_logic;
csync_utc_i : in std_logic_vector(31 downto 0);
csync_coarse_i : in std_logic_vector(27 downto 0);
tdc_start_p1_i: in std_logic;
rearm_p1_o : out std_logic;
tag_valid_i : in std_logic;
tag_utc_i : in std_logic_vector(31 downto 0);
tag_coarse_i : in std_logic_vector(27 downto 0);
tag_frac_i : in std_logic_vector(g_frac_bits-1 downto 0);
delay_pulse_o : out std_logic;
delay_value_o : out std_logic_vector(9 downto 0);
delay_load_o : out std_logic;
delay_load_done_i : in std_logic;
dcr_mode_i : in std_logic;
dcr_enable_i : in std_logic;
dcr_pg_arm_i : in std_logic;
dcr_pg_arm_o : out std_logic;
dcr_pg_arm_load_i : in std_logic;
dcr_pg_trig_o : out std_logic;
dcr_update_i : in std_logic;
dcr_upd_done_o : out std_logic;
dcr_force_cp_i : in std_logic;
dcr_pol_i : in std_logic;
frr_i : in std_logic_vector(9 downto 0);
u_start_i : in std_logic_vector(31 downto 0);
c_start_i : in std_logic_vector(27 downto 0);
f_start_i : in std_logic_vector(g_frac_bits-1 downto 0);
u_end_i : in std_logic_vector(31 downto 0);
c_end_i : in std_logic_vector(27 downto 0);
f_end_i : in std_logic_vector(g_frac_bits-1 downto 0)
);
end fd_delay_channel_driver;
architecture behavioral of fd_delay_channel_driver is
component fd_ts_adder
generic (
g_frac_bits : integer;
g_coarse_bits : integer;
g_utc_bits : integer;
g_coarse_range : integer);
port (
clk_i : in std_logic;
rst_n_i : in std_logic;
valid_i : in std_logic;
a_utc_i : in std_logic_vector(g_utc_bits-1 downto 0);
a_coarse_i : in std_logic_vector(g_coarse_bits-1 downto 0);
a_frac_i : in std_logic_vector(g_frac_bits-1 downto 0);
b_utc_i : in std_logic_vector(g_utc_bits-1 downto 0);
b_coarse_i : in std_logic_vector(g_coarse_bits-1 downto 0);
b_frac_i : in std_logic_vector(g_frac_bits-1 downto 0);
valid_o : out std_logic;
q_utc_o : out std_logic_vector(g_utc_bits-1 downto 0);
q_coarse_o : out std_logic_vector(g_coarse_bits-1 downto 0);
q_frac_o : out std_logic_vector(g_frac_bits-1 downto 0));
end component;
signal cntr_utc : unsigned(31 downto 0);
signal cntr_coarse : unsigned(27 downto 0);
signal u_start_int : std_logic_vector(31 downto 0);
signal c_start_int : std_logic_vector(27 downto 0);
signal f_start_int : std_logic_vector(g_frac_bits-1 downto 0);
signal u_end_int : std_logic_vector(31 downto 0);
signal c_end_int : std_logic_vector(27 downto 0);
signal f_end_int : std_logic_vector(g_frac_bits-1 downto 0);
signal st_coarse : std_logic_vector(27 downto 0);
signal st_frac : std_logic_vector(g_frac_bits-1 downto 0);
signal st_utc : std_logic_vector(31 downto 0);
signal end_coarse : std_logic_vector(27 downto 0);
signal end_frac : std_logic_vector(g_frac_bits-1 downto 0);
signal end_utc : std_logic_vector(31 downto 0);
signal st_end_valid : std_logic;
signal st_delay_setpoint : unsigned(9 downto 0);
signal end_delay_setpoint : unsigned(9 downto 0);
signal pg_hit_start_stage0, pg_hit_end_stage0 : std_logic_vector(1 downto 0);
signal dly_hit_start_stage0, dly_hit_end_stage0 : std_logic_vector(1 downto 0);
signal hit_start, hit_end : std_logic;
signal hit_start_d0 : std_logic;
signal pulse_pending : std_logic;
constant c_MODE_DELAY : std_logic := '0';
constant c_MODE_PULSE_GEN : std_logic := '1';
type t_fine_output_state is (IDLE, WAIT_ARB_START, WAIT_START_PULSE, WAIT_ARB_END, WAIT_PULSE_END, WAIT_ARB_START_CP, WAIT_PULSE_CP);
signal state : t_fine_output_state;
begin
U_Calc_Pulse_Start : fd_ts_adder
generic map (
g_frac_bits => g_frac_bits,
g_coarse_bits => 28,
g_utc_bits => 32,
g_coarse_range => g_coarse_range)
port map (
clk_i => clk_ref_i,
rst_n_i => rst_n_i,
valid_i => tag_valid_i,
a_utc_i => tag_utc_i,
a_coarse_i => tag_coarse_i,
a_frac_i => tag_frac_i,
b_utc_i => u_start_int,
b_coarse_i => c_start_int,
b_frac_i => f_start_int,
valid_o => st_end_valid,
q_utc_o => st_utc,
q_coarse_o => st_coarse,
q_frac_o => st_frac);
U_Calc_Pulse_End : fd_ts_adder
generic map (
g_frac_bits => g_frac_bits,
g_coarse_bits => 28,
g_utc_bits => 32,
g_coarse_range => g_coarse_range)
port map (
clk_i => clk_ref_i,
rst_n_i => rst_n_i,
valid_i => tag_valid_i,
a_utc_i => tag_utc_i,
a_coarse_i => tag_coarse_i,
a_frac_i => tag_frac_i,
b_utc_i => u_end_int,
b_coarse_i => c_end_int,
b_frac_i => f_end_int,
valid_o => open,
q_utc_o => end_utc,
q_coarse_o => end_coarse,
q_frac_o => end_frac);
st_delay_setpoint <= resize((unsigned(st_frac) * unsigned(frr_i)) srl g_frac_bits, 10);
end_delay_setpoint <= resize((unsigned(end_frac) * unsigned(frr_i)) srl g_frac_bits, 10);
dcr_upd_done_o <= '1';
p_update_start_end_regs : process(clk_ref_i)
begin
if rising_edge(clk_ref_i) then
if rst_n_i = '0' then
u_start_int <= (others => '0');
c_start_int <= (others => '0');
f_start_int <= (others => '0');
u_end_int <= (others => '0');
c_end_int <= (others => '0');
f_end_int <= (others => '0');
else
if(dcr_update_i = '1') then
u_start_int <= u_start_i;
c_start_int <= c_start_i;
f_start_int <= f_start_i;
u_end_int <= u_end_i;
c_end_int <= c_end_i;
f_end_int <= f_end_i;
end if;
end if;
end if;
end process;
p_timebase_counter : process(clk_ref_i)
begin
if rising_edge(clk_ref_i) then
if rst_n_i = '0' then
cntr_utc <= (others => '0');
cntr_coarse <= (others => '0');
else
if(csync_p1_i = '1')then
cntr_utc <= unsigned(csync_utc_i);
cntr_coarse <= unsigned(csync_coarse_i);
elsif(cntr_coarse = g_coarse_range-1) then
cntr_coarse <= (others => '0');
cntr_utc <= cntr_utc + 1;
else
cntr_coarse <= cntr_coarse + 1;
end if;
end if;
end if;
end process;
-- Delay mode - uses the adjusted trigger timestamp
dly_hit_start_stage0(0) <= '1' when (cntr_coarse = unsigned(st_coarse)) else '0';
dly_hit_start_stage0(1) <= '1' when (cntr_utc = unsigned(st_utc)) else '0';
-- Pulse generator mode - uses the values from u_start directly
pg_hit_start_stage0(0) <= '1' when (cntr_coarse = unsigned(c_start_int)) else '0';
pg_hit_start_stage0(1) <= '1' when (cntr_utc = unsigned(u_start_int)) else '0';
dly_hit_end_stage0(0) <= '1' when (cntr_coarse = unsigned(end_coarse)) else '0';
dly_hit_end_stage0(1) <= '1' when (cntr_utc = unsigned(end_utc)) else '0';
pg_hit_end_stage0(0) <= '1' when (cntr_coarse = unsigned(c_end_int)) else '0';
pg_hit_end_stage0(1) <= '1' when (cntr_utc = unsigned(u_end_int)) else '0';
p_match_hit_stage1 : process(clk_ref_i)
begin
if rising_edge(clk_ref_i) then
if rst_n_i = '0' or dcr_enable_i = '0' then
hit_end <= '0';
hit_start <= '0';
else
if(dcr_mode_i = c_MODE_DELAY) then
hit_start <= dly_hit_start_stage0(0) and dly_hit_start_stage0(1) and pulse_pending;
hit_end <= dly_hit_end_stage0(0) and dly_hit_end_stage0(1) and pulse_pending;
elsif(dcr_mode_i = c_MODE_PULSE_GEN) then
hit_start <= pg_hit_start_stage0(0) and pg_hit_start_stage0(1) and pulse_pending;
hit_end <= pg_hit_end_stage0(0) and pg_hit_end_stage0(1) and pulse_pending;
end if;
end if;
end if;
end process;
p_gen_pulse : process(clk_ref_i)
begin
if rising_edge(clk_ref_i) then
if rst_n_i = '0' then
delay_pulse_o <= '0';
pulse_pending <= '0';
else
if(dcr_enable_i = '0') then
if(state = WAIT_PULSE_CP) then
delay_pulse_o <= tdc_start_p1_i;
else
delay_pulse_o <= not dcr_pol_i;
end if;
pulse_pending <= '0';
else
if(tag_valid_i = '1') then
pulse_pending <= '1';
delay_pulse_o <= not dcr_pol_i;
elsif(hit_start = '1') then
delay_pulse_o <= dcr_pol_i;
elsif (hit_end = '1') then
delay_pulse_o <= not dcr_pol_i;
pulse_pending <= '0';
elsif (pulse_pending = '0') then
delay_pulse_o <= not dcr_pol_i;
end if;
end if;
end if;
end if;
end process;
p_fine_fsm : process(clk_ref_i)
begin
if rising_edge(clk_ref_i) then
if rst_n_i = '0' then
state <= IDLE;
delay_load_o <= '0';
delay_value_o <= (others => '0');
rearm_p1_o <= '0';
hit_start_d0 <= '0';
else
hit_start_d0 <= hit_start;
case state is
when IDLE =>
rearm_p1_o <= '0';
if (st_end_valid = '1' and dcr_enable_i = '1') then
delay_value_o <= std_logic_vector(st_delay_setpoint);
delay_load_o <= '1';
state <= WAIT_ARB_START;
elsif(dcr_force_cp_i = '1') then
delay_value_o <= frr_i;
delay_load_o <= '1';
state <= WAIT_ARB_START_CP;
end if;
when WAIT_ARB_START =>
if(delay_load_done_i = '1') then
state <= WAIT_START_PULSE;
delay_load_o <= '0';
end if;
when WAIT_ARB_START_CP =>
if(delay_load_done_i = '1') then
state <= WAIT_PULSE_CP;
delay_load_o <= '0';
end if;
when WAIT_PULSE_CP =>
if(tdc_start_p1_i = '1') then
state <= IDLE;
end if;
when WAIT_START_PULSE =>
if (hit_start_d0 = '1') then
state <= WAIT_ARB_END;
delay_value_o <= std_logic_vector(end_delay_setpoint);
delay_load_o <= '1';
end if;
when WAIT_ARB_END =>
if(delay_load_done_i = '1') then
state <= WAIT_PULSE_END;
delay_load_o <= '0';
end if;
when WAIT_PULSE_END =>
if(hit_end = '1') then
rearm_p1_o <= '1';
state <= IDLE;
end if;
end case;
end if;
end if;
end process;
end behavioral;
hdl/rtl/fd_delay_line_arbiter.vhd 0 → 100644
View file @ e502cb54
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity fd_delay_line_arbiter is
port (
clk_ref_i : in std_logic;
rst_n_i : in std_logic;
load_i : in std_logic_vector(3 downto 0);
done_o : out std_logic_vector(3 downto 0);
delay_val0_i : in std_logic_vector(9 downto 0);
delay_val1_i : in std_logic_vector(9 downto 0);
delay_val2_i : in std_logic_vector(9 downto 0);
delay_val3_i : in std_logic_vector(9 downto 0);
delay_val_o : out std_logic_vector(9 downto 0);
delay_len_o : out std_logic_vector(3 downto 0)
);
end fd_delay_line_arbiter;
architecture behavioral of fd_delay_line_arbiter is
signal arb_sreg : std_logic_vector(4*2 - 1 downto 0);
type t_dly_array is array (integer range <>) of std_logic_vector(9 downto 0);
signal done_reg : std_logic_vector(3 downto 0);
signal delay_vec : t_dly_array(0 to 3);
signal delay_len_reg : std_logic_vector(3 downto 0);
signal delay_val_reg : std_logic_vector(9 downto 0);
begin -- behavioral
delay_vec(0) <= delay_val0_i;
delay_vec(1) <= delay_val1_i;
delay_vec(2) <= delay_val2_i;
delay_vec(3) <= delay_val3_i;
p_arbitrate : process(clk_ref_i)
begin
if rising_edge(clk_ref_i) then
if rst_n_i = '0' then
delay_len_reg <= (others => '1');
delay_val_reg <= (others => '0');
-- done_reg <= (others => '0');
arb_sreg <= std_logic_vector(to_unsigned(1, arb_sreg'length));
else
arb_sreg <= arb_sreg(arb_sreg'left-1 downto 0) & arb_sreg(arb_sreg'left);
for i in 0 to 3 loop
if(arb_sreg(2*i) = '1' and load_i(i) = '1') then
delay_val_reg <= delay_vec(i);
delay_len_reg(i) <= '0';
end if;
if(arb_sreg(2*i+1) = '1' and load_i(i) = '1') then
delay_val_reg <= delay_vec(i);
delay_len_reg(i) <= '1';
end if;
end loop; -- i in 0 to 3
-- done_o <= done_reg;
delay_len_o <= delay_len_reg;
delay_val_o <= delay_val_reg;
end if;
end if;
end process;
gen_done: for i in 0 to 3 generate
done_o(i) <= arb_sreg(2*i+1) and load_i(i);
end generate gen_done;
end behavioral;
hdl/rtl/fd_delay_line_driver.vhd deleted 100644 → 0
View file @ c864d026
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.fine_delay_pkg.all;
entity delay_line_driver is
port(
clk_ref_i : in std_logic;
rst_n_i : in std_logic;
-- time base synchronization
csync_time_i : in t_fd_timestamp;
csync_p1_i : in std_logic;
ch_start_i : in t_fd_timestamp_array;
ch_length_i : in t_fd_timestamp_array;
ch_load_p1_i : in std_logic_vector(c_fd_num_outputs-1 downto 0);
ch_polarity_i : in std_logic_vector(c_fd_num_outputs-1 downto 0);
ch_ready_o : out std_logic_vector(c_fd_num_outputs-1 downto 0);
delay_bus_o : out std_logic_vector(9 downto 0);
delay_len_o : out std_logic_vector(c_fd_num_outputs-1 downto 0);
delay_pulse_o : out std_logic_vector(c_fd_num_outputs-1 downto 0)
);
end delay_line_driver;
architecture behavioral of delay_line_driver is
signal t : t_fd_timestamp;
type t_adjustment_fsm_state is(A_IDLE, A_FIX_START, A_FIX_END, A_WAIT_ARM);
type t_channel is record
t_start: t_fd_timestamp;
t_stop: t_fd_timestamp;
t_length: t_fd_timestamp;
adj_state: t_adjustment_fsm_state;
armed: std_logic;
dly_adjusted: std_logic;
done: std_logic;
issued_start: std_logic;
end record;
type t_channel_array is array(0 to c_fd_num_outputs-1) of t_channel;
signal C : t_channel_array;
begin -- behavioral
p_timebase_counter : process(clk_ref_i)
begin
if rising_edge(clk_ref_i) then
if rst_n_i = '0' then
t.secs <= (others => '0');
t.cycles <= (others => '0');
t.fine <= (others => '0');
else
if(csync_p1_i = '1') then
t <= csync_time_i;
elsif(t.cycles = c_fd_refclk_freq - 1) then
t.secs <= t.secs + 1;
t.cycles <= (others => '0');
else
t.cycles <= t.cycles + 1;
end if;
end if;
end if;
end process;
gen_channels : for i in 0 to c_fd_num_outputs-1 generate
p_load_adjust_start_stop : process(clk_ref_i)
begin
if rising_edge(clk_ref_i) then
if rst_n_i = '0' then
C(i).t_start.cycles <= (others => '0');
C(i).t_start.secs <= (others => '0');
C(i).t_start.fine <= (others => '0');
C(i).armed <= '0';
else
case C(i).adj_state is
when A_IDLE =>
if ch_load_p1_i(i) = '1' then
C(i).t_start.fine <= ch_start_i(i).fine;
C(i).t_start.cycles <= ch_start_i(i).cycles - 2; -- 2 cycles in advance
C(i).t_start.secs <= ch_start_i(i).secs;
C(i).t_length <= ch_length_i(i);
C(i).armed <= '1';
C(i).adj_state <= A_FIX_START;
end if;
when A_FIX_START =>
-- calculate the end-of-pulse timestamp
C(i).t_stop.fine <= C(i).t_start.fine + C(i).t_length.fine;
C(i).t_stop.cycles <= C(i).t_start.cycles + C(i).t_length.cycles;
C(i).t_stop.secs <= C(i).t_start.secs + C(i).t_length.secs;
-- unwind start-of-pulse timestamp
if(C(i).t_start.cycles(27) = '1') then
C(i).t_start.secs <= C(i).t_start.secs + 1;
C(i).t_start.cycles <= C(i).t_start.cycles + c_fd_refclk_freq;
end if;
when others => null;
end case;
end if;
end if;
end process;
end generate gen_channels;
end behavioral;
hdl/rtl/fd_gpio.vhd deleted 100644 → 0
View file @ c864d026
library ieee;
use ieee.std_logic_1164.all;
use work.fd_wbgen2_pkg.all;
entity fd_gpio is
port (
clk_sys_i : in std_logic;
rst_n_i : in std_logic;
-- chip select for VCTCXO DAC
spi_cs_dac_n_o : out std_logic;
-- chip select for AD9516 PLL
spi_cs_pll_n_o : out std_logic;
-- chip select for MCP23S17 GPIO
spi_cs_gpio_n_o : out std_logic;
-- these are obvious
spi_sclk_o : out std_logic;
spi_mosi_o : out std_logic;
spi_miso_i : in std_logic;
regs_b : inout t_fd_registers
);
end fd_gpio;
architecture rtl of fd_gpio is
begin -- rtl
regs_b <= c_fd_registers_init_value;
p_gpio_loads : process(clk_sys_i)
begin
if rising_edge(clk_sys_i) then
if (rst_n_i = '0') then
spi_cs_dac_n_o <= '1';
spi_cs_pll_n_o <= '1';
spi_cs_gpio_n_o <= '1';
spi_sclk_o <= '0';
spi_mosi_o <= '0';
regs_b.gprr_miso_i <= '0';
else
if(regs_b.gpsr_cs_pll_wr_o = '1' and regs_b.gpsr_cs_pll_o = '1') then
spi_cs_pll_n_o <= '1';
elsif (regs_b.gpcr_cs_pll_wr_o = '1' and regs_b.gpcr_cs_pll_o = '1') then
spi_cs_pll_n_o <= '0';
end if;
if(regs_b.gpsr_cs_gpio_wr_o = '1' and regs_b.gpsr_cs_gpio_o = '1') then
spi_cs_gpio_n_o <= '1';
elsif (regs_b.gpcr_cs_gpio_wr_o = '1' and regs_b.gpcr_cs_gpio_o = '1') then
spi_cs_gpio_n_o <= '0';
end if;
if(regs_b.gpsr_mosi_wr_o = '1' and regs_b.gpsr_mosi_o = '1') then
spi_mosi_o <= '1';
elsif (regs_b.gpcr_mosi_wr_o = '1' and regs_b.gpcr_mosi_o = '1') then
spi_mosi_o <= '0';
end if;
if(regs_b.gpsr_sclk_wr_o = '1' and regs_b.gpsr_sclk_o = '1') then
spi_sclk_o <= '1';
elsif (regs_b.gpcr_sclk_wr_o = '1' and regs_b.gpcr_sclk_o = '1') then
spi_sclk_o <= '0';
end if;
regs_b.gprr_miso_i <= spi_miso_i;
end if;
end if;
end process;
end rtl;
hdl/rtl/fd_rearm_generator.vhd 0 → 100644
View file @ e502cb54
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity fd_rearm_generator is
port (
clk_ref_i : in std_logic;
rst_n_i : in std_logic;
tag_valid_i : in std_logic;
rearm_i : in std_logic_vector(3 downto 0);
dcr_enable_i : in std_logic_vector(3 downto 0);
dcr_mode_i : in std_logic_vector(3 downto 0);
rearm_p1_o : out std_logic
);
end fd_rearm_generator;
architecture behavioral of fd_rearm_generator is
signal rearm_ch : std_logic_vector(3 downto 0);
begin -- behavioral
p_rearm : process(clk_ref_i)
begin
if rising_edge(clk_ref_i) then
if rst_n_i = '0' then
rearm_ch <= (others => '0');
rearm_p1_o <= '0';
else
if(rearm_ch = "1111") then
rearm_ch <= (others => '0');
rearm_p1_o <= '1';
elsif(tag_valid_i = '1')then
for i in 0 to 3 loop
rearm_ch(i) <= (not dcr_enable_i(i)) or dcr_mode_i(i);
end loop; -- i
rearm_p1_o <= '0';
else
rearm_p1_o <= '0';
for i in 0 to 3 loop
if(dcr_enable_i(i) = '1' and rearm_i(i) = '1') then
rearm_ch(i) <= '1';
end if;
end loop; -- i
end if;
end if;
end if;
end process;
end behavioral;
hdl/rtl/fd_reset_generator.vhd
View file @ e502cb54
......@@ -13,7 +13,7 @@ entity fd_reset_generator is
rst_n_sys_o : out std_logic;
rst_n_ref_o : out std_logic;
regs_b : inout t_fd_registers);
regs_i : in t_fd_out_registers);
end fd_reset_generator;
......@@ -28,8 +28,6 @@ architecture behavioral of fd_reset_generator is
begin -- behavioral
regs_b <= c_fd_registers_init_value;
p_soft_reset : process(clk_sys_i)
begin
......@@ -37,7 +35,7 @@ begin -- behavioral
if(rst_n_i = '0') then
rstn_host_sysclk <= '0';
else
if(regs_b.rstr_wr_o = '1' and regs_b.rstr_o = c_RSTR_TRIGGER_VALUE) then
if(regs_i.rstr_wr_o = '1' and regs_i.rstr_o = c_RSTR_TRIGGER_VALUE) then
rstn_host_sysclk <= '0';
else
rstn_host_sysclk <= '1';
......
hdl/rtl/fd_ring_buffer.vhd
View file @ e502cb54
......@@ -25,9 +25,11 @@ entity fd_ring_buffer is
tag_coarse_i : in std_logic_vector(27 downto 0);
tag_frac_i : in std_logic_vector(g_frac_bits-1 downto 0);
advance_rbuf_i : in std_logic;
buf_irq_o : out std_logic;
regs_b : inout t_fd_registers
advance_rbuf_i : in std_logic;
buf_irq_o : out std_logic;
regs_i : in t_fd_out_registers;
regs_o : out t_fd_in_registers
);
......@@ -88,12 +90,11 @@ architecture behavioral of fd_ring_buffer is
begin -- behavioral
regs_b <= c_fd_registers_init_value;
p_count_seq_id : process(clk_ref_i)
begin
if rising_edge(clk_ref_i) then
if rst_n_ref_i = '0' or regs_b.tsbcr_rst_seq_o = '1' then
if rst_n_ref_i = '0' or regs_i.tsbcr_rst_seq_o = '1' then
cur_seq_id <= (others => '0');
elsif(tag_valid_i = '1') then
cur_seq_id <= cur_seq_id + 1;
......@@ -152,28 +153,27 @@ begin -- behavioral
buf_full <= '1' when (buf_wr_ptr + 1 = buf_rd_ptr) else '0';
buf_empty <= '1' when (buf_wr_ptr = buf_rd_ptr) else '0';
buf_write <= regs_b.tsbcr_enable_o and fifo_read_d0;
buf_write <= regs_i.tsbcr_enable_o and fifo_read_d0;
buf_ram_out <= f_unpack_timestamp(buf_rd_data);
buf_irq_o <= not buf_empty;
-- drive WB registers
regs_b.tsbcr_empty_i <= buf_empty;
regs_b.tsbcr_full_i <= buf_full;
regs_o.tsbcr_empty_i <= buf_empty;
regs_o.tsbcr_full_i <= buf_full;
p_buffer_control : process(clk_sys_i)
begin
if rising_edge(clk_sys_i) then
if rst_n_sys_i = '0' or regs_b.tsbcr_purge_o = '1' then
if rst_n_sys_i = '0' or regs_i.tsbcr_purge_o = '1' then
buf_rd_ptr <= (others => '0');
buf_wr_ptr <= (others => '0');
buf_write <= '0';
fifo_read_d0 <= '0';
else
fifo_read_d0 <= fifo_read;
update_regs <= advance_rbuf_i and not (buf_write and buf_full);
--update_regs <= advance_rbuf_i and not (buf_write and buf_full);
if(buf_write = '1') then
buf_wr_ptr <= buf_wr_ptr + 1;
......@@ -183,16 +183,17 @@ begin -- behavioral
buf_rd_ptr <= buf_rd_ptr + 1;
end if;
if(update_regs = '1') then
regs_b.tsbr_u_i <= buf_ram_out.utc;
regs_b.tsbr_c_i <= buf_ram_out.coarse;
regs_b.tsbr_fid_fine_i <= buf_ram_out.frac;
regs_b.tsbr_fid_seqid_i <= buf_ram_out.seq_id;
end if;
----if(update_regs = '1') then
----end if;
end if;
end if;
end process;
regs_o.tsbr_u_i <= buf_ram_out.utc;
regs_o.tsbr_c_i <= buf_ram_out.coarse;
regs_o.tsbr_fid_fine_i <= buf_ram_out.frac;
regs_o.tsbr_fid_seqid_i <= buf_ram_out.seq_id;
end behavioral;
hdl/rtl/fd_spi_master.vhd 0 → 100644
View file @ e502cb54
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.fd_wbgen2_pkg.all;
use work.gencores_pkg.all;
entity fd_spi_master is
port (
clk_sys_i : in std_logic;
rst_n_i : in std_logic;
-- chip select for VCTCXO DAC
spi_cs_dac_n_o : out std_logic;
-- chip select for AD9516 PLL
spi_cs_pll_n_o : out std_logic;
-- chip select for MCP23S17 GPIO
spi_cs_gpio_n_o : out std_logic;
-- these are obvious
spi_sclk_o : out std_logic;
spi_mosi_o : out std_logic;
spi_miso_i : in std_logic;
regs_i : in t_fd_out_registers;
regs_o : out t_fd_in_registers
);
end fd_spi_master;
architecture behavioral of fd_spi_master is
signal busy : std_logic;
signal divider : unsigned(11 downto 0);
signal dataSh : std_logic_vector(23 downto 0);
signal bitCounter : std_logic_vector(25 downto 0);
signal endSendingData : std_logic;
signal sendingData : std_logic;
signal iDacClk : std_logic;
signal iValidValue : std_logic;
signal divider_muxed : std_logic;
signal cs_sel_dac : std_logic;
signal cs_sel_gpio : std_logic;
signal cs_sel_pll : std_logic;
signal data_in_reg : std_logic_vector(23 downto 0);
signal data_out_reg : std_logic_vector(23 downto 0);
begin -- rtl
divider_muxed <= divider(1); -- sclk = clk_i/64
iValidValue <= regs_i.scr_start_o;
process(clk_sys_i, rst_n_i)
begin
if rising_edge(clk_sys_i) then
if (rst_n_i = '0') then
data_in_reg <= (others => '0');
elsif(regs_i.scr_data_load_o = '1') then
data_in_reg <= regs_i.scr_data_o;
end if;
end if;
end process;
process(clk_sys_i, rst_n_i)
begin
if rising_edge(clk_sys_i) then
if rst_n_i = '0' then
sendingData <= '0';
else
if iValidValue = '1' and sendingData = '0' then
sendingData <= '1';
elsif endSendingData = '1' then
sendingData <= '0';
end if;
end if;
end if;
end process;
process(clk_sys_i)
begin
if rising_edge(clk_sys_i) then
if iValidValue = '1' then
divider <= (others => '0');
elsif sendingData = '1' then
if(divider_muxed = '1') then
divider <= (others => '0');
else
divider <= divider + 1;
end if;
elsif endSendingData = '1' then
divider <= (others => '0');
end if;
end if;
end process;
process(clk_sys_i, rst_n_i)
begin
if rising_edge(clk_sys_i) then
if rst_n_i = '0' then
iDacClk <= '1'; -- 0
else
if iValidValue = '1' then
iDacClk <= '1'; -- 0
elsif divider_muxed = '1' then
iDacClk <= not(iDacClk);
elsif endSendingData = '1' then
iDacClk <= '1'; -- 0
end if;
end if;
end if;
end process;
process(clk_sys_i, rst_n_i)
begin
if rising_edge(clk_sys_i) then
if rst_n_i = '0' then
dataSh <= (others => '0');
else
if iValidValue = '1' and sendingData = '0' then
cs_sel_dac <= regs_i.scr_sel_dac_o;
cs_sel_gpio <= regs_i.scr_sel_gpio_o;
cs_sel_pll <= regs_i.scr_sel_pll_o;
dataSh <= data_in_reg;
elsif sendingData = '1' and divider_muxed = '1' and iDacClk = '0' then
dataSh(0) <= spi_miso_i; --dataSh(dataSh'left);
dataSh(dataSh'left downto 1) <= dataSh(dataSh'left - 1 downto 0);
end if;
end if;
end if;
end process;
process(clk_sys_i)
begin
if rising_edge(clk_sys_i) then
if iValidValue = '1' and sendingData = '0' then
bitCounter(0) <= '1';
bitCounter(bitCounter'left downto 1) <= (others => '0');
elsif sendingData = '1' and to_integer(divider) = 0 and iDacClk = '1' then
bitCounter(0) <= '0';
bitCounter(bitCounter'left downto 1) <= bitCounter(bitCounter'left - 1 downto 0);
end if;
end if;
end process;
endSendingData <= bitCounter(bitCounter'left);
regs_o.scr_ready_i <= not SendingData;
regs_o.scr_data_i <= dataSh;
spi_mosi_o <= dataSh(dataSh'left);
spi_cs_pll_n_o <= not(sendingData) or (not cs_sel_pll);
spi_cs_dac_n_o <= not(sendingData) or (not cs_sel_dac);
spi_cs_gpio_n_o <= not(sendingData) or (not cs_sel_gpio);
p_drive_sclk : process(iDacClk, regs_i)
begin
if(regs_i.scr_cpol_o = '0') then
spi_sclk_o <= (iDacClk);
else
spi_sclk_o <= not (iDacClk);
end if;
end process;
end behavioral;
hdl/rtl/fd_timestamper_stat_unit.vhd
View file @ e502cb54
......@@ -13,7 +13,8 @@ entity fd_timestamper_stat_unit is
trig_pulse_i : in std_logic;
raw_tag_valid_i : in std_logic;
regs_b : inout t_fd_registers);
regs_i : in t_fd_out_registers;
regs_o : out t_fd_in_registers);
end fd_timestamper_stat_unit;
......@@ -31,14 +32,15 @@ architecture behavioral of fd_timestamper_stat_unit is
begin -- behavioral
p_count_events : process(clk_ref_i)
begin
if rising_edge(clk_ref_i) then
if (rst_n_i = '0' or regs_b.gcr_input_en_o = '0' or regs_b.iepd_rst_stat_o = '1') then
if (rst_n_i = '0' or regs_i.gcr_input_en_o = '0' or regs_i.iepd_rst_stat_o = '1') then
event_count_raw <= (others => '0');
event_count_tagged <= (others => '0');
else
if(trig_pulse_i= '1') then
if(trig_pulse_i = '1') then
event_count_raw <= event_count_raw + 1;
end if;
......@@ -49,13 +51,13 @@ begin -- behavioral
end if;
end process;
regs_b.iecraw_i <= std_logic_vector(event_count_raw);
regs_b.iectag_i <= std_logic_vector(event_count_tagged);
regs_o.iecraw_i <= std_logic_vector(event_count_raw);
regs_o.iectag_i <= std_logic_vector(event_count_tagged);
p_measure_processing_delay : process(clk_ref_i)
begin
if rising_edge(clk_ref_i) then
if rst_n_i = '0' or regs_b.gcr_input_en_o = '0' or regs_b.iepd_rst_stat_o = '1' then
if rst_n_i = '0' or regs_i.gcr_input_en_o = '0' or regs_i.iepd_rst_stat_o = '1' then
cur_pdelay <= (others => '0');
worst_pdelay <= (others => '0');
pd_state <= PD_WAIT_TRIGGER;
......@@ -88,6 +90,6 @@ begin -- behavioral
end if;
end process;
regs_b.iepd_pdelay_i <= std_logic_vector(worst_pdelay);
regs_o.iepd_pdelay_i <= std_logic_vector(worst_pdelay);
end behavioral;
hdl/rtl/fd_ts_adder.vhd
View file @ e502cb54
......@@ -6,13 +6,15 @@
-- Author : Tomasz Wlostowski
-- Company : CERN
-- Created : 2011-08-29
-- Last update: 2011-08-29
-- Last update: 2011-09-05
-- Platform : FPGA-generic
-- Standard : VHDL'93
-------------------------------------------------------------------------------
-- Description: Pipelined timestamp adder with re-normalization of the result.
-- Adds a to b, producing normalized timestamp q. Input timestamps must obey
-- the following constraints:
-- Adds a to b, producing normalized timestamp q. A timestmap is normalized when
-- the 0 <= frac < 2**g_frac_bits, 0 <= coarse <= g_coarse_range-1 and utc >= 0.
-- For correct operation of renormalizer, input timestamps must meet the
-- following constraints:
-- 1. 0 <= (a/b)_frac_i <= 2**g_frac_bits-1
-- 2. -g_coarse_range+1 <= (a_coarse_i + b_coarse_i) <= 3*g_coarse_range-1
-------------------------------------------------------------------------------
......@@ -48,7 +50,7 @@ use ieee.numeric_std.all;
entity fd_ts_adder is
generic
(
-- sizes of the respective bitfields
-- sizes of the respective bitfields of the input/output timestamps
g_frac_bits : integer := 12;
g_coarse_bits : integer := 28;
g_utc_bits : integer := 32;
......@@ -63,6 +65,8 @@ entity fd_ts_adder is
valid_i : in std_logic; -- when HI, a_* and b_* contain valid timestamps
-- Input timestamps
a_utc_i : in std_logic_vector(g_utc_bits-1 downto 0);
a_coarse_i : in std_logic_vector(g_coarse_bits-1 downto 0);
a_frac_i : in std_logic_vector(g_frac_bits-1 downto 0);
......@@ -71,6 +75,7 @@ entity fd_ts_adder is
b_coarse_i : in std_logic_vector(g_coarse_bits-1 downto 0);
b_frac_i : in std_logic_vector(g_frac_bits-1 downto 0);
-- Normalized sum output (valid when valid_o == 1)
valid_o : out std_logic;
q_utc_o : out std_logic_vector(g_utc_bits-1 downto 0);
q_coarse_o : out std_logic_vector(g_coarse_bits-1 downto 0);
......@@ -99,7 +104,7 @@ architecture rtl of fd_ts_adder is
begin -- rtl
-- Pipeline stage 0: just add the two timestamps
-- Pipeline stage 0: just add the two timestamps field by field
p_stage0 : process(clk_i)
begin
if rising_edge(clk_i) then
......@@ -212,6 +217,7 @@ begin -- rtl
end if;
end process;
-- clip the extra bits and output the result
valid_o <= pipe(c_NUM_PIPELINE_STAGES-1);
q_utc_o <= std_logic_vector(sums(c_NUM_PIPELINE_STAGES-1).utc(g_utc_bits-1 downto 0));
q_coarse_o <= std_logic_vector(sums(c_NUM_PIPELINE_STAGES-1).coarse(g_coarse_bits-1 downto 0));
......
hdl/rtl/fd_wbgen2_pkg.vhd
View file @ e502cb54
......@@ -3,7 +3,7 @@
---------------------------------------------------------------------------------------
-- File : fd_wbgen2_pkg.vhd
-- Author : auto-generated by wbgen2 from fd_wishbone_slave.wb
-- Created : Wed Aug 31 11:09:47 2011
-- Created : Wed Sep 7 17:10:37 2011
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE fd_wishbone_slave.wb
......@@ -16,261 +16,295 @@ use ieee.numeric_std.all;
use work.wbgen2_pkg.all;
package fd_wbgen2_pkg is
type t_fd_registers is record
rstr_o : std_logic_vector(31 downto 0);
rstr_wr_o : std_logic;
gcr_bypass_o : std_logic;
gcr_input_en_o : std_logic;
gcr_csync_int_o : std_logic;
gcr_csync_wr_o : std_logic;
-- Input registers (user design -> WB slave)
type t_fd_in_registers is record
gcr_wr_ready_i : std_logic;
tar_data_o : std_logic_vector(27 downto 0);
tar_data_i : std_logic_vector(27 downto 0);
tar_data_load_o : std_logic;
tar_addr_o : std_logic_vector(3 downto 0);
tdcsr_write_o : std_logic;
tdcsr_read_o : std_logic;
tdcsr_err_i : std_logic;
tdcsr_int_i : std_logic;
tdcsr_load_i : std_logic;
tdcsr_empty_i : std_logic;
tdcsr_start_dis_o : std_logic;
tdcsr_start_en_o : std_logic;
tdcsr_stop_dis_o : std_logic;
tdcsr_stop_en_o : std_logic;
adsfr_o : std_logic_vector(17 downto 0);
atmcr_c_thr_o : std_logic_vector(3 downto 0);
atmcr_f_thr_o : std_logic_vector(22 downto 0);
asor_offset_o : std_logic_vector(22 downto 0);
gpsr_cs_pll_o : std_logic;
gpsr_cs_pll_wr_o : std_logic;
gpsr_cs_gpio_o : std_logic;
gpsr_cs_gpio_wr_o : std_logic;
gpsr_sclk_o : std_logic;
gpsr_sclk_wr_o : std_logic;
gpsr_mosi_o : std_logic;
gpsr_mosi_wr_o : std_logic;
gpcr_cs_pll_o : std_logic;
gpcr_cs_pll_wr_o : std_logic;
gpcr_cs_gpio_o : std_logic;
gpcr_cs_gpio_wr_o : std_logic;
gpcr_sclk_o : std_logic;
gpcr_sclk_wr_o : std_logic;
gpcr_mosi_o : std_logic;
gpcr_mosi_wr_o : std_logic;
gprr_miso_i : std_logic;
iecraw_i : std_logic_vector(31 downto 0);
iectag_i : std_logic_vector(31 downto 0);
iepd_rst_stat_o : std_logic;
iepd_pdelay_i : std_logic_vector(7 downto 0);
vtr_dac_val_o : std_logic_vector(15 downto 0);
vtr_dac_val_wr_o : std_logic;
vtr_dac_rdy_i : std_logic;
tsbcr_enable_o : std_logic;
tsbcr_purge_o : std_logic;
tsbcr_rst_seq_o : std_logic;
rcrr_i : std_logic_vector(31 downto 0);
rcfr_i : std_logic_vector(31 downto 0);
tsbcr_full_i : std_logic;
tsbcr_empty_i : std_logic;
tsbr_u_i : std_logic_vector(31 downto 0);
tsbr_c_i : std_logic_vector(27 downto 0);
tsbr_fid_fine_i : std_logic_vector(11 downto 0);
tsbr_fid_seqid_i : std_logic_vector(15 downto 0);
dcr1_mode_dly_o : std_logic;
dcr1_mode_pg_o : std_logic;
dcr1_pg_arm_o : std_logic;
rawfifo_wr_req_i : std_logic;
rawfifo_frac_i : std_logic_vector(27 downto 0);
rawfifo_coarse_i : std_logic_vector(27 downto 0);
dcr1_pg_arm_i : std_logic;
dcr1_pg_arm_load_o : std_logic;
dcr1_pg_trig_i : std_logic;
dcr1_update_o : std_logic;
dcr1_upd_done_i : std_logic;
dcr1_force_cp_o : std_logic;
dcr1_pol_o : std_logic;
frr1_o : std_logic_vector(9 downto 0);
u_start1_o : std_logic_vector(31 downto 0);
c_start1_o : std_logic_vector(27 downto 0);
f_start1_o : std_logic_vector(9 downto 0);
u_end1_o : std_logic_vector(31 downto 0);
c_end1_o : std_logic_vector(27 downto 0);
f_end1_o : std_logic_vector(9 downto 0);
dcr2_mode_dly_o : std_logic;
dcr2_mode_pg_o : std_logic;
dcr2_pg_arm_o : std_logic;
dcr2_pg_arm_i : std_logic;
dcr2_pg_arm_load_o : std_logic;
dcr2_pg_trig_i : std_logic;
dcr2_update_o : std_logic;
dcr2_upd_done_i : std_logic;
dcr2_force_cp_o : std_logic;
dcr2_pol_o : std_logic;
frr2_o : std_logic_vector(9 downto 0);
u_start2_o : std_logic_vector(31 downto 0);
c_start2_o : std_logic_vector(27 downto 0);
f_start2_o : std_logic_vector(9 downto 0);
u_end2_o : std_logic_vector(31 downto 0);
c_end2_o : std_logic_vector(27 downto 0);
f_end2_o : std_logic_vector(9 downto 0);
dcr3_mode_dly_o : std_logic;
dcr3_mode_pg_o : std_logic;
dcr3_pg_arm_o : std_logic;
dcr3_pg_arm_i : std_logic;
dcr3_pg_arm_load_o : std_logic;
dcr3_pg_trig_i : std_logic;
dcr3_update_o : std_logic;
dcr3_upd_done_i : std_logic;
dcr3_force_cp_o : std_logic;
dcr3_pol_o : std_logic;
frr3_o : std_logic_vector(9 downto 0);
u_start3_o : std_logic_vector(31 downto 0);
c_start3_o : std_logic_vector(27 downto 0);
f_start3_o : std_logic_vector(9 downto 0);
u_end3_o : std_logic_vector(31 downto 0);
c_end3_o : std_logic_vector(27 downto 0);
f_end3_o : std_logic_vector(9 downto 0);
dcr4_mode_dly_o : std_logic;
dcr4_mode_pg_o : std_logic;
dcr4_pg_arm_o : std_logic;
dcr4_pg_arm_i : std_logic;
dcr4_pg_arm_load_o : std_logic;
dcr4_pg_trig_i : std_logic;
dcr4_update_o : std_logic;
dcr4_upd_done_i : std_logic;
dcr4_force_cp_o : std_logic;
dcr4_pol_o : std_logic;
frr4_o : std_logic_vector(9 downto 0);
u_start4_o : std_logic_vector(31 downto 0);
c_start4_o : std_logic_vector(27 downto 0);
f_start4_o : std_logic_vector(9 downto 0);
u_end4_o : std_logic_vector(31 downto 0);
c_end4_o : std_logic_vector(27 downto 0);
f_end4_o : std_logic_vector(9 downto 0);
end record;
constant c_fd_registers_init_value: t_fd_registers := (
rstr_o => (others => 'Z'),
rstr_wr_o => 'Z',
gcr_bypass_o => 'Z',
gcr_input_en_o => 'Z',
gcr_csync_int_o => 'Z',
gcr_csync_wr_o => 'Z',
gcr_wr_ready_i => 'Z',
tar_data_o => (others => 'Z'),
tar_data_i => (others => 'Z'),
tar_data_load_o => 'Z',
tar_addr_o => (others => 'Z'),
tdcsr_write_o => 'Z',
tdcsr_read_o => 'Z',
tdcsr_err_i => 'Z',
tdcsr_int_i => 'Z',
tdcsr_load_i => 'Z',
tdcsr_empty_i => 'Z',
tdcsr_start_dis_o => 'Z',
tdcsr_start_en_o => 'Z',
tdcsr_stop_dis_o => 'Z',
tdcsr_stop_en_o => 'Z',
adsfr_o => (others => 'Z'),
atmcr_c_thr_o => (others => 'Z'),
atmcr_f_thr_o => (others => 'Z'),
asor_offset_o => (others => 'Z'),
gpsr_cs_pll_o => 'Z',
gpsr_cs_pll_wr_o => 'Z',
gpsr_cs_gpio_o => 'Z',
gpsr_cs_gpio_wr_o => 'Z',
gpsr_sclk_o => 'Z',
gpsr_sclk_wr_o => 'Z',
gpsr_mosi_o => 'Z',
gpsr_mosi_wr_o => 'Z',
gpcr_cs_pll_o => 'Z',
gpcr_cs_pll_wr_o => 'Z',
gpcr_cs_gpio_o => 'Z',
gpcr_cs_gpio_wr_o => 'Z',
gpcr_sclk_o => 'Z',
gpcr_sclk_wr_o => 'Z',
gpcr_mosi_o => 'Z',
gpcr_mosi_wr_o => 'Z',
gprr_miso_i => 'Z',
iecraw_i => (others => 'Z'),
iectag_i => (others => 'Z'),
iepd_rst_stat_o => 'Z',
iepd_pdelay_i => (others => 'Z'),
vtr_dac_val_o => (others => 'Z'),
vtr_dac_val_wr_o => 'Z',
vtr_dac_rdy_i => 'Z',
tsbcr_enable_o => 'Z',
tsbcr_purge_o => 'Z',
tsbcr_rst_seq_o => 'Z',
tsbcr_full_i => 'Z',
tsbcr_empty_i => 'Z',
tsbr_u_i => (others => 'Z'),
tsbr_c_i => (others => 'Z'),
tsbr_fid_fine_i => (others => 'Z'),
tsbr_fid_seqid_i => (others => 'Z'),
dcr1_mode_dly_o => 'Z',
dcr1_mode_pg_o => 'Z',
dcr1_pg_arm_o => 'Z',
dcr1_pg_arm_i => 'Z',
dcr1_pg_arm_load_o => 'Z',
dcr1_pg_trig_i => 'Z',
dcr1_update_o => 'Z',
dcr1_upd_done_i => 'Z',
dcr1_force_cp_o => 'Z',
dcr1_pol_o => 'Z',
frr1_o => (others => 'Z'),
u_start1_o => (others => 'Z'),
c_start1_o => (others => 'Z'),
f_start1_o => (others => 'Z'),
u_end1_o => (others => 'Z'),
c_end1_o => (others => 'Z'),
f_end1_o => (others => 'Z'),
dcr2_mode_dly_o => 'Z',
dcr2_mode_pg_o => 'Z',
dcr2_pg_arm_o => 'Z',
dcr2_pg_arm_i => 'Z',
dcr2_pg_arm_load_o => 'Z',
dcr2_pg_trig_i => 'Z',
dcr2_update_o => 'Z',
dcr2_upd_done_i => 'Z',
dcr2_force_cp_o => 'Z',
dcr2_pol_o => 'Z',
frr2_o => (others => 'Z'),
u_start2_o => (others => 'Z'),
c_start2_o => (others => 'Z'),
f_start2_o => (others => 'Z'),
u_end2_o => (others => 'Z'),
c_end2_o => (others => 'Z'),
f_end2_o => (others => 'Z'),
dcr3_mode_dly_o => 'Z',
dcr3_mode_pg_o => 'Z',
dcr3_pg_arm_o => 'Z',
dcr3_pg_arm_i => 'Z',
dcr3_pg_arm_load_o => 'Z',
dcr3_pg_trig_i => 'Z',
dcr3_update_o => 'Z',
dcr3_upd_done_i => 'Z',
dcr3_force_cp_o => 'Z',
dcr3_pol_o => 'Z',
frr3_o => (others => 'Z'),
u_start3_o => (others => 'Z'),
c_start3_o => (others => 'Z'),
f_start3_o => (others => 'Z'),
u_end3_o => (others => 'Z'),
c_end3_o => (others => 'Z'),
f_end3_o => (others => 'Z'),
dcr4_mode_dly_o => 'Z',
dcr4_mode_pg_o => 'Z',
dcr4_pg_arm_o => 'Z',
dcr4_pg_arm_i => 'Z',
dcr4_pg_arm_load_o => 'Z',
dcr4_pg_trig_i => 'Z',
dcr4_update_o => 'Z',
dcr4_upd_done_i => 'Z',
dcr4_force_cp_o => 'Z',
dcr4_pol_o => 'Z',
frr4_o => (others => 'Z'),
u_start4_o => (others => 'Z'),
c_start4_o => (others => 'Z'),
f_start4_o => (others => 'Z'),
u_end4_o => (others => 'Z'),
c_end4_o => (others => 'Z'),
f_end4_o => (others => 'Z')
);
constant c_fd_in_registers_init_value: t_fd_in_registers := (
gcr_wr_ready_i => '0',
tar_data_i => (others => '0'),
tdcsr_err_i => '0',
tdcsr_int_i => '0',
tdcsr_load_i => '0',
tdcsr_empty_i => '0',
iecraw_i => (others => '0'),
iectag_i => (others => '0'),
iepd_pdelay_i => (others => '0'),
rcrr_i => (others => '0'),
rcfr_i => (others => '0'),
tsbcr_full_i => '0',
tsbcr_empty_i => '0',
tsbr_u_i => (others => '0'),
tsbr_c_i => (others => '0'),
tsbr_fid_fine_i => (others => '0'),
tsbr_fid_seqid_i => (others => '0'),
rawfifo_wr_req_i => '0',
rawfifo_frac_i => (others => '0'),
rawfifo_coarse_i => (others => '0'),
dcr1_pg_arm_i => '0',
dcr1_pg_trig_i => '0',
dcr1_upd_done_i => '0',
dcr2_pg_arm_i => '0',
dcr2_pg_trig_i => '0',
dcr2_upd_done_i => '0',
dcr3_pg_arm_i => '0',
dcr3_pg_trig_i => '0',
dcr3_upd_done_i => '0',
dcr4_pg_arm_i => '0',
dcr4_pg_trig_i => '0',
dcr4_upd_done_i => '0'
);
-- Output registers (WB slave -> user design)
type t_fd_out_registers is record
rstr_o : std_logic_vector(31 downto 0);
rstr_wr_o : std_logic;
gcr_bypass_o : std_logic;
gcr_input_en_o : std_logic;
gcr_csync_int_o : std_logic;
gcr_csync_wr_o : std_logic;
tar_data_o : std_logic_vector(27 downto 0);
tar_data_load_o : std_logic;
tar_addr_o : std_logic_vector(3 downto 0);
tdcsr_write_o : std_logic;
tdcsr_read_o : std_logic;
tdcsr_start_dis_o : std_logic;
tdcsr_start_en_o : std_logic;
tdcsr_stop_dis_o : std_logic;
tdcsr_stop_en_o : std_logic;
adsfr_o : std_logic_vector(17 downto 0);
atmcr_c_thr_o : std_logic_vector(3 downto 0);
atmcr_f_thr_o : std_logic_vector(22 downto 0);
asor_offset_o : std_logic_vector(22 downto 0);
iepd_rst_stat_o : std_logic;
tsbcr_enable_o : std_logic;
tsbcr_purge_o : std_logic;
tsbcr_rst_seq_o : std_logic;
rawfifo_wr_full_o : std_logic;
dcr1_enable_o : std_logic;
dcr1_mode_o : std_logic;
dcr1_pg_arm_o : std_logic;
dcr1_pg_arm_load_o : std_logic;
dcr1_update_o : std_logic;
dcr1_force_cp_o : std_logic;
dcr1_pol_o : std_logic;
frr1_o : std_logic_vector(9 downto 0);
u_start1_o : std_logic_vector(31 downto 0);
c_start1_o : std_logic_vector(27 downto 0);
f_start1_o : std_logic_vector(11 downto 0);
u_end1_o : std_logic_vector(31 downto 0);
c_end1_o : std_logic_vector(27 downto 0);
f_end1_o : std_logic_vector(11 downto 0);
dcr2_enable_o : std_logic;
dcr2_mode_o : std_logic;
dcr2_pg_arm_o : std_logic;
dcr2_pg_arm_load_o : std_logic;
dcr2_update_o : std_logic;
dcr2_force_cp_o : std_logic;
dcr2_pol_o : std_logic;
frr2_o : std_logic_vector(9 downto 0);
u_start2_o : std_logic_vector(31 downto 0);
c_start2_o : std_logic_vector(27 downto 0);
f_start2_o : std_logic_vector(11 downto 0);
u_end2_o : std_logic_vector(31 downto 0);
c_end2_o : std_logic_vector(27 downto 0);
f_end2_o : std_logic_vector(11 downto 0);
dcr3_enable_o : std_logic;
dcr3_mode_o : std_logic;
dcr3_pg_arm_o : std_logic;
dcr3_pg_arm_load_o : std_logic;
dcr3_update_o : std_logic;
dcr3_force_cp_o : std_logic;
dcr3_pol_o : std_logic;
frr3_o : std_logic_vector(9 downto 0);
u_start3_o : std_logic_vector(31 downto 0);
c_start3_o : std_logic_vector(27 downto 0);
f_start3_o : std_logic_vector(11 downto 0);
u_end3_o : std_logic_vector(31 downto 0);
c_end3_o : std_logic_vector(27 downto 0);
f_end3_o : std_logic_vector(11 downto 0);
dcr4_enable_o : std_logic;
dcr4_mode_o : std_logic;
dcr4_pg_arm_o : std_logic;
dcr4_pg_arm_load_o : std_logic;
dcr4_update_o : std_logic;
dcr4_force_cp_o : std_logic;
dcr4_pol_o : std_logic;
frr4_o : std_logic_vector(9 downto 0);
u_start4_o : std_logic_vector(31 downto 0);
c_start4_o : std_logic_vector(27 downto 0);
f_start4_o : std_logic_vector(11 downto 0);
u_end4_o : std_logic_vector(31 downto 0);
c_end4_o : std_logic_vector(27 downto 0);
f_end4_o : std_logic_vector(11 downto 0);
end record;
constant c_fd_out_registers_init_value: t_fd_out_registers := (
rstr_o => (others => '0'),
rstr_wr_o => '0',
gcr_bypass_o => '0',
gcr_input_en_o => '0',
gcr_csync_int_o => '0',
gcr_csync_wr_o => '0',
tar_data_o => (others => '0'),
tar_data_load_o => '0',
tar_addr_o => (others => '0'),
tdcsr_write_o => '0',
tdcsr_read_o => '0',
tdcsr_start_dis_o => '0',
tdcsr_start_en_o => '0',
tdcsr_stop_dis_o => '0',
tdcsr_stop_en_o => '0',
adsfr_o => (others => '0'),
atmcr_c_thr_o => (others => '0'),
atmcr_f_thr_o => (others => '0'),
asor_offset_o => (others => '0'),
iepd_rst_stat_o => '0',
tsbcr_enable_o => '0',
tsbcr_purge_o => '0',
tsbcr_rst_seq_o => '0',
rawfifo_wr_full_o => '0',
dcr1_enable_o => '0',
dcr1_mode_o => '0',
dcr1_pg_arm_o => '0',
dcr1_pg_arm_load_o => '0',
dcr1_update_o => '0',
dcr1_force_cp_o => '0',
dcr1_pol_o => '0',
frr1_o => (others => '0'),
u_start1_o => (others => '0'),
c_start1_o => (others => '0'),
f_start1_o => (others => '0'),
u_end1_o => (others => '0'),
c_end1_o => (others => '0'),
f_end1_o => (others => '0'),
dcr2_enable_o => '0',
dcr2_mode_o => '0',
dcr2_pg_arm_o => '0',
dcr2_pg_arm_load_o => '0',
dcr2_update_o => '0',
dcr2_force_cp_o => '0',
dcr2_pol_o => '0',
frr2_o => (others => '0'),
u_start2_o => (others => '0'),
c_start2_o => (others => '0'),
f_start2_o => (others => '0'),
u_end2_o => (others => '0'),
c_end2_o => (others => '0'),
f_end2_o => (others => '0'),
dcr3_enable_o => '0',
dcr3_mode_o => '0',
dcr3_pg_arm_o => '0',
dcr3_pg_arm_load_o => '0',
dcr3_update_o => '0',
dcr3_force_cp_o => '0',
dcr3_pol_o => '0',
frr3_o => (others => '0'),
u_start3_o => (others => '0'),
c_start3_o => (others => '0'),
f_start3_o => (others => '0'),
u_end3_o => (others => '0'),
c_end3_o => (others => '0'),
f_end3_o => (others => '0'),
dcr4_enable_o => '0',
dcr4_mode_o => '0',
dcr4_pg_arm_o => '0',
dcr4_pg_arm_load_o => '0',
dcr4_update_o => '0',
dcr4_force_cp_o => '0',
dcr4_pol_o => '0',
frr4_o => (others => '0'),
u_start4_o => (others => '0'),
c_start4_o => (others => '0'),
f_start4_o => (others => '0'),
u_end4_o => (others => '0'),
c_end4_o => (others => '0'),
f_end4_o => (others => '0')
);
function "or" (left, right: t_fd_in_registers) return t_fd_in_registers;
function f_x_to_zero (x:std_logic) return std_logic;
end package;
package body fd_wbgen2_pkg is
function f_x_to_zero (x:std_logic) return std_logic is
begin
if(x = 'X' or x = 'U') then
return '0';
else
return x;
end if;
end function;
function "or" (left, right: t_fd_in_registers) return t_fd_in_registers is
variable tmp: t_fd_in_registers;
begin
tmp.gcr_wr_ready_i := left.gcr_wr_ready_i or right.gcr_wr_ready_i;
tmp.tar_data_i := left.tar_data_i or right.tar_data_i;
tmp.tdcsr_err_i := left.tdcsr_err_i or right.tdcsr_err_i;
tmp.tdcsr_int_i := left.tdcsr_int_i or right.tdcsr_int_i;
tmp.tdcsr_load_i := left.tdcsr_load_i or right.tdcsr_load_i;
tmp.tdcsr_empty_i := left.tdcsr_empty_i or right.tdcsr_empty_i;
tmp.iecraw_i := left.iecraw_i or right.iecraw_i;
tmp.iectag_i := left.iectag_i or right.iectag_i;
tmp.iepd_pdelay_i := left.iepd_pdelay_i or right.iepd_pdelay_i;
tmp.rcrr_i := left.rcrr_i or right.rcrr_i;
tmp.rcfr_i := left.rcfr_i or right.rcfr_i;
tmp.tsbcr_full_i := left.tsbcr_full_i or right.tsbcr_full_i;
tmp.tsbcr_empty_i := left.tsbcr_empty_i or right.tsbcr_empty_i;
tmp.tsbr_u_i := left.tsbr_u_i or right.tsbr_u_i;
tmp.tsbr_c_i := left.tsbr_c_i or right.tsbr_c_i;
tmp.tsbr_fid_fine_i := left.tsbr_fid_fine_i or right.tsbr_fid_fine_i;
tmp.tsbr_fid_seqid_i := left.tsbr_fid_seqid_i or right.tsbr_fid_seqid_i;
tmp.rawfifo_wr_req_i := left.rawfifo_wr_req_i or right.rawfifo_wr_req_i;
tmp.rawfifo_frac_i := left.rawfifo_frac_i or right.rawfifo_frac_i;
tmp.rawfifo_coarse_i := left.rawfifo_coarse_i or right.rawfifo_coarse_i;
tmp.dcr1_pg_arm_i := left.dcr1_pg_arm_i or right.dcr1_pg_arm_i;
tmp.dcr1_pg_trig_i := left.dcr1_pg_trig_i or right.dcr1_pg_trig_i;
tmp.dcr1_upd_done_i := left.dcr1_upd_done_i or right.dcr1_upd_done_i;
tmp.dcr2_pg_arm_i := left.dcr2_pg_arm_i or right.dcr2_pg_arm_i;
tmp.dcr2_pg_trig_i := left.dcr2_pg_trig_i or right.dcr2_pg_trig_i;
tmp.dcr2_upd_done_i := left.dcr2_upd_done_i or right.dcr2_upd_done_i;
tmp.dcr3_pg_arm_i := left.dcr3_pg_arm_i or right.dcr3_pg_arm_i;
tmp.dcr3_pg_trig_i := left.dcr3_pg_trig_i or right.dcr3_pg_trig_i;
tmp.dcr3_upd_done_i := left.dcr3_upd_done_i or right.dcr3_upd_done_i;
tmp.dcr4_pg_arm_i := left.dcr4_pg_arm_i or right.dcr4_pg_arm_i;
tmp.dcr4_pg_trig_i := left.dcr4_pg_trig_i or right.dcr4_pg_trig_i;
tmp.dcr4_upd_done_i := left.dcr4_upd_done_i or right.dcr4_upd_done_i;
return tmp;
end function;
end package body;
hdl/rtl/fd_wishbone_slave.vhd
View file @ e502cb54
This source diff could not be displayed because it is too large. You can view the blob instead.
hdl/rtl/fd_wishbone_slave.wb
View file @ e502cb54
......@@ -18,6 +18,21 @@ peripheral {
};
};
reg {
name = "ID Register";
prefix = "IDR";
field {
name = "ID Magic Value";
description = "Always 0xf19ede1a";
size = 32;
type = CONSTANT;
value = 0xf19ede1a;
};
};
reg {
name = "Global Control Register";
prefix = "GCR";
......@@ -246,85 +261,6 @@ peripheral {
};
};
reg {
name = "GPIO set register";
prefix = "GPSR";
field {
name = "SPI PLL chip select";
prefix = "cs_pll";
type = PASS_THROUGH;
size = 1;
};
field {
name = "SPI GPIO chip select";
prefix = "cs_gpio";
type = PASS_THROUGH;
size = 1;
};
field {
name = "SPI SCLK";
prefix = "sclk";
type = PASS_THROUGH;
size = 1;
};
field {
name = "SPI MOSI";
prefix = "mosi";
type = PASS_THROUGH;
size = 1;
};
};
reg {
name = "GPIO clear register";
prefix = "GPCR";
field {
name = "SPI PLL chip select";
prefix = "cs_pll";
type = PASS_THROUGH;
size = 1;
};
field {
name = "SPI GPIO chip select";
prefix = "cs_gpio";
type = PASS_THROUGH;
size = 1;
};
field {
name = "SPI SCLK";
prefix = "sclk";
type = PASS_THROUGH;
size = 1;
};
field {
name = "SPI MOSI";
prefix = "mosi";
type = PASS_THROUGH;
size = 1;
};
};
reg {
name = "GPIO Readback Register";
prefix = "GPRR";
field {
name = "SPI MISO";
prefix = "miso";
type = BIT;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "Raw Input Events Counter Register ";
prefix = "IECRAW";
......@@ -381,30 +317,107 @@ peripheral {
};
};
-- reg {
-- name = "SPI Control Register";
-- prefix = "SCR";
-- description = "Single control register for the SPI Controller, allowing for single-cycle (non-waiting) updates of the DAC, GPIO & PLL.";
-- field {
-- name = "Data";
-- prefix = "DATA";
-- size = 24;
-- description = "Data to be read/written from/to the SPI bus";
-- type = SLV;
-- load = LOAD_EXT;
-- access_dev = READ_WRITE;
-- access_bus = READ_WRITE;
-- };
-- field {
-- name = "Select DAC";
-- prefix = "SEL_DAC";
-- type = BIT;
-- description = "write 1: selects the DAC as the target peripheral of the transfer";
-- access_bus = READ_WRITE;
-- access_dev = READ_ONLY;
-- };
-- field {
-- name = "Select PLL";
-- prefix = "SEL_PLL";
-- type = BIT;
-- description = "write 1: selects the AD9516 PLL as the target peripheral of the transfer";
-- access_bus = READ_WRITE;
-- access_dev = READ_ONLY;
-- };
-- field {
-- name = "Select GPIO";
-- prefix = "SEL_GPIO";
-- type = BIT;
-- description = "write 1: selects the MCP23S17 GPIO as the target peripheral of the transfer";
-- access_bus = READ_WRITE;
-- access_dev = READ_ONLY;
-- };
-- field {
-- name = "Ready flag";
-- prefix = "READY";
-- type = BIT;
-- description = "read 0: SPI controller is busy performing a transfer\
-- read 1: SPI controller has finished its previous transfer. Read-back data is available in the DATA field";
-- access_bus = READ_ONLY;
-- access_dev = WRITE_ONLY;
-- };
-- field {
-- name = "Clock Polarity";
-- description = "0: SPI clock is not inverted\
-- 1: SPI clock is inverted";
-- prefix = "CPOL";
-- type = BIT;
-- access_bus = READ_WRITE;
-- access_dev = READ_ONLY;
-- };
-- field {
-- name = "Transfer Start";
-- prefix = "START";
-- type = MONOSTABLE;
-- description = "write 1: Starts transfer to the selected peripheral\
-- write 0: no effect";
-- };
-- };
reg {
name = "VCXO Tuning Register";
prefix = "VTR";
description = "Register controlling the DAC which produces the tuning voltage for the clock oscillator. Used by White Rabbit Core.\
<b>Warning:</b> Since the DAC shares its physical connection with the PLL and the GPIO expander, it's forbidden to access any of these chips while updating the DAC";
name = "Reference Clock Rate Register";
prefix = "RCRR";
description = "Provides the momentary value of the internal clock rate counter. Can be used in conjunction with the DAC to roughly syntonize the card's reference clock with a clock coming from an external master installed in the same host (e.g. a CTRV/CTRP) in a software-only way.";
field {
name = "DAC Value";
description = " Value to be written to the DAC. Scaled to 0..3 V";
prefix = "DAC_VAL";
size = 16;
type = PASS_THROUGH;
};
name = "Rate";
type = SLV;
size = 32;
clock = "clk_ref_i";
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
}
};
reg {
name = "Reference Clock Frequency Register";
prefix = "RCFR";
description = "Current frequency of the reference clock. Used for testing/calibration purposes.";
field {
name = "DAC Ready";
description = "1: DAC is ready to accept another control word\
0: DAC update in progress";
prefix = "DAC_RDY";
type = BIT;
align = 31;
name = "Frequency";
type = SLV;
size = 32;
clock = "clk_ref_i";
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
access_dev = WRITE_ONLY;
}
};
reg {
......@@ -419,7 +432,6 @@ peripheral {
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
ack_read = "advance_rbuf_o";
};
field {
......@@ -505,6 +517,33 @@ peripheral {
type = SLV;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
ack_read = "advance_rbuf_o";
};
};
fifo_reg {
direction = CORE_TO_BUS;
size = 256;
prefix = "RAWFIFO";
name = "RAW FIFO";
flags_bus = {FIFO_EMPTY};
flags_dev = {FIFO_FULL};
clock = "clk_ref_i";
field {
name = "RawFrac";
prefix = "FRAC";
size = 28;
type = SLV;
};
field {
name = "RawCoarse";
prefix = "COARSE";
size = 28;
type = SLV;
};
};
};
......@@ -516,22 +555,25 @@ channel_template = {
align = 8;
field {
name = "Delay mode select";
prefix = "MODE_DLY";
description = "write 1: Channel will work as a delay generator, producing delayed copies of pulses comming to the trigger input\
write 0: no effect\
<b>Warning:</b> MODE_DLY bit can be safely set only when the TDC and the delay logic are disabled (i.e. when GCR.BYPASS = 1)";
type = MONOSTABLE;
name = "Enable channel";
prefix = "ENABLE";
description = "0: channel is disabled\
1: channel is enabled";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
clock = "clk_ref_i";
};
field {
name = "Pulse Generator mode select";
prefix = "MODE_PG";
description = "write 1: Channel will work as a programmable pulse generator - producing a pulse which begins at UTC time [U_START, C_START, F_START] and ends at [U_END, C_END, F_END].\
write 0: no effect\
<b>Warning:</b> MODE_PG bit can be safely set only when the TDC and the delay logic are disabled (i.e. when GCR.BYPASS = 1)";
type = MONOSTABLE;
name = "Delay mode select";
prefix = "MODE";
description = "0: Channel will work as a delay generator, producing delayed copies of pulses comming to the trigger input\
1: Channel will work as a programmable pulse generator - producing a pulse which begins at UTC time [U_START, C_START, F_START] and ends at [U_END, C_END, F_END].\
<b>Warning:</b> MODE_DLY bit can be safely set only when the TDC and the delay logic are disabled (i.e. when GCR.BYPASS = 1)";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
clock = "clk_ref_i";
};
......@@ -597,7 +639,7 @@ clock = "clk_ref_i";
name = "Output Polarity";
prefix = "POL";
description = "1: output is active HIGH\
0: output is active LOW";
0: output is active LOW";
clock = "clk_ref_i";
type = BIT;
access_bus = READ_WRITE;
......@@ -656,11 +698,11 @@ clock = "clk_ref_i";
reg {
name = "Pulse start time / offset (sub-cycle fine part, channel %d)";
prefix = "F_START%d";
description = "Sub-clock cycle part of the pulse start absolute time (when in PG mode) / offset from trigger (when in delay mode). Expressed as a number of delay line taps. Acceptable range: 0 to 1023.";
description = "Sub-clock cycle part of the pulse start absolute time (when in PG mode) / offset from trigger (when in delay mode). Scales linearly to <0..8 ns>: 0 = 0 ps, 4095 = 7999 ps.";
field {
name = "Fine delay taps";
size = 10;
name = "Fractional part";
size = 12;
type = SLV;
clock = "clk_ref_i";
access_bus = READ_WRITE;
......@@ -672,7 +714,7 @@ clock = "clk_ref_i";
reg {
name = "Pulse end time / offset (UTC part, channel %d)";
prefix = "U_END%d";
description = "UTC part of the pulse start absolute time (when in PG mode) / offset from trigger (when in delay mode).";
description = "UTC part of the pulse end absolute time (when in PG mode) / offset from trigger (when in delay mode).";
field {
name = "UTC seconds";
......@@ -687,7 +729,7 @@ clock = "clk_ref_i";
reg {
name = "Pulse end time / offset (8 ns cycles, channel %d)";
prefix = "C_END%d";
description = "Sub-second part of the pulse start absolute time (when in PG mode) / offset from trigger (when in delay mode). Expressed as a number of 125 MHz clock cycles. Acceptable range: 0 to 124999999.";
description = "Sub-second part of the pulse end absolute time (when in PG mode) / offset from trigger (when in delay mode). Expressed as a number of 125 MHz clock cycles. Acceptable range: 0 to 124999999.";
field {
name = "Refclk cycles";
......@@ -702,11 +744,11 @@ clock = "clk_ref_i";
reg {
name = "Pulse end time / offset (sub-cycle fine part, channel %d)";
prefix = "F_END%d";
description = "Sub-clock cycle part of the pulse start absolute time (when in PG mode) / offset from trigger (when in delay mode). Expressed as a number of delay line taps. Acceptable range: 0 to 1023.";
description = "Sub-clock cycle part of the pulse end absolute time (when in PG mode) / offset from trigger (when in delay mode). Scales linearly to <0..8 ns>: 0 = 0 ps, 4095 = 7999 ps.";
field {
name = "Fine delay taps";
size = 10;
name = "Fractional part";
size = 12;
type = SLV;
clock = "clk_ref_i";
access_bus = READ_WRITE;
......
hdl/rtl/fine_delay_core.vhd
View file @ e502cb54
......@@ -3,6 +3,8 @@ use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.fd_wbgen2_pkg.all;
use work.gencores_pkg.all;
use work.wishbone_pkg.all;
entity fine_delay_core is
port(
......@@ -29,6 +31,8 @@ entity fine_delay_core is
-- TDC start signal (copy)
tdc_start_i : in std_logic;
led_trig_o : out std_logic;
---------------------------------------------------------------------------
-- ACAM TDC-GPX signals (all asynchronous)
---------------------------------------------------------------------------
......@@ -98,11 +102,18 @@ entity fine_delay_core is
wr_coarse_i : in std_logic_vector(27 downto 0);
wr_utc_i : in std_logic_vector(31 downto 0);
---------------------------------------------------------------------------
-- Temeperature sensor (1-wire)
---------------------------------------------------------------------------
owr_en_o : out std_logic;
owr_i : in std_logic;
---------------------------------------------------------------------------
-- Wishbone (classic)
---------------------------------------------------------------------------
wb_adr_i : in std_logic_vector(5 downto 0);
wb_adr_i : in std_logic_vector(7 downto 0);
wb_dat_i : in std_logic_vector(31 downto 0);
wb_dat_o : out std_logic_vector(31 downto 0);
wb_cyc_i : in std_logic;
......@@ -118,99 +129,164 @@ architecture rtl of fine_delay_core is
constant c_TIMESTAMP_FRAC_BITS : integer := 12;
constant c_RING_BUFFER_SIZE_LOG2 : integer := 8;
constant c_REF_CLK_FREQ : integer := 256;
constant c_REF_CLK_FREQ : integer := 125000000;
component fd_reset_generator
component fd_ts_normalizer
generic (
g_frac_bits : integer;
g_coarse_bits : integer;
g_utc_bits : integer;
g_coarse_range : integer);
port (
clk_sys_i : in std_logic;
clk_ref_i : in std_logic;
rst_n_i : in std_logic;
rst_n_sys_o : out std_logic;
rst_n_ref_o : out std_logic;
regs_b : inout t_fd_registers);
clk_i : in std_logic;
rst_n_i : in std_logic;
valid_i : in std_logic;
utc_i : in std_logic_vector(g_utc_bits-1 downto 0);
coarse_i : in std_logic_vector(g_coarse_bits-1 downto 0);
frac_i : in std_logic_vector(g_frac_bits-1 downto 0);
valid_o : out std_logic;
utc_o : out std_logic_vector(g_utc_bits-1 downto 0);
coarse_o : out std_logic_vector(g_coarse_bits-1 downto 0);
frac_o : out std_logic_vector(g_frac_bits-1 downto 0));
end component;
component fd_gpio
component fd_reset_generator
port (
clk_sys_i : in std_logic;
rst_n_i : in std_logic;
spi_cs_dac_n_o : out std_logic;
spi_cs_pll_n_o : out std_logic;
spi_cs_gpio_n_o : out std_logic;
spi_sclk_o : out std_logic;
spi_mosi_o : out std_logic;
spi_miso_i : in std_logic;
regs_b : inout t_fd_registers);
clk_sys_i : in std_logic;
clk_ref_i : in std_logic;
rst_n_i : in std_logic;
rst_n_sys_o : out std_logic;
rst_n_ref_o : out std_logic;
regs_i : in t_fd_out_registers);
end component;
component fd_wishbone_slave
port (
rst_n_i : in std_logic;
wb_clk_i : in std_logic;
wb_addr_i : in std_logic_vector(5 downto 0);
wb_data_i : in std_logic_vector(31 downto 0);
wb_data_o : out std_logic_vector(31 downto 0);
wb_cyc_i : in std_logic;
wb_sel_i : in std_logic_vector(3 downto 0);
wb_stb_i : in std_logic;
wb_we_i : in std_logic;
wb_ack_o : out std_logic;
wb_irq_o : out std_logic;
clk_ref_i : in std_logic;
advance_rbuf_o : out std_logic;
irq_ts_buf_notempty_i : in std_logic;
regs_b : inout t_fd_registers);
end component;
component fd_acam_timestamper
generic (
g_min_pulse_width : natural;
g_clk_ref_freq : integer;
g_frac_bits : integer);
g_frac_bits : integer);
port (
clk_ref_i : in std_logic;
rst_n_i : in std_logic;
trig_a_n_i : in std_logic;
tdc_start_i : in std_logic;
acam_d_o : out std_logic_vector(27 downto 0);
acam_d_i : in std_logic_vector(27 downto 0);
acam_d_oe_o : out std_logic;
acam_a_o : out std_logic_vector(3 downto 0);
acam_cs_n_o : out std_logic;
acam_rd_n_o : out std_logic;
acam_wr_n_o : out std_logic;
acam_ef_i : in std_logic;
acam_stop_dis_o : out std_logic;
acam_start_dis_o : out std_logic;
acam_alutrigger_o : out std_logic;
tag_frac_o : out std_logic_vector(g_frac_bits-1 downto 0);
tag_coarse_o : out std_logic_vector(27 downto 0);
tag_utc_o : out std_logic_vector(31 downto 0);
tag_rearm_p1_i : in std_logic;
tag_valid_o : out std_logic;
csync_coarse_i : in std_logic_vector(27 downto 0);
csync_utc_i : in std_logic_vector(31 downto 0);
csync_p1_i : in std_logic;
regs_b : inout t_fd_registers);
clk_ref_i : in std_logic;
rst_n_i : in std_logic;
trig_a_n_i : in std_logic;
tdc_start_i : in std_logic;
acam_d_o : out std_logic_vector(27 downto 0);
acam_d_i : in std_logic_vector(27 downto 0);
acam_d_oe_o : out std_logic;
acam_a_o : out std_logic_vector(3 downto 0);
acam_cs_n_o : out std_logic;
acam_rd_n_o : out std_logic;
acam_wr_n_o : out std_logic;
acam_ef_i : in std_logic;
acam_stop_dis_o : out std_logic;
acam_start_dis_o : out std_logic;
acam_alutrigger_o : out std_logic;
tag_frac_o : out std_logic_vector(g_frac_bits-1 downto 0);
tag_coarse_o : out std_logic_vector(27 downto 0);
tag_utc_o : out std_logic_vector(31 downto 0);
tag_rearm_p1_i : in std_logic;
tag_valid_o : out std_logic;
csync_coarse_i : in std_logic_vector(27 downto 0);
csync_utc_i : in std_logic_vector(31 downto 0);
csync_p1_i : in std_logic;
tdc_start_p1_o : out std_logic;
regs_i : in t_fd_out_registers;
regs_o : out t_fd_in_registers := c_fd_in_registers_init_value;
dbg_o : out std_logic_vector(3 downto 0));
end component;
component fd_wishbone_slave
port (
rst_n_i : in std_logic;
wb_clk_i : in std_logic;
wb_addr_i : in std_logic_vector(5 downto 0);
wb_data_i : in std_logic_vector(31 downto 0);
wb_data_o : out std_logic_vector(31 downto 0);
wb_cyc_i : in std_logic;
wb_sel_i : in std_logic_vector(3 downto 0);
wb_stb_i : in std_logic;
wb_we_i : in std_logic;
wb_ack_o : out std_logic;
wb_irq_o : out std_logic;
clk_ref_i : in std_logic;
irq_ts_buf_notempty_i : in std_logic;
advance_rbuf_o : out std_logic;
regs_i : in t_fd_in_registers;
regs_o : out t_fd_out_registers);
end component;
component fd_csync_generator
generic (
g_coarse_range : integer;
g_frac_bits : integer);
g_coarse_range : integer);
port (
clk_ref_i : in std_logic;
rst_n_i : in std_logic;
wr_time_valid_i : in std_logic;
wr_utc_i : in std_logic_vector(31 downto 0);
wr_coarse_i : in std_logic_vector(27 downto 0);
csync_p1_o : out std_logic;
csync_utc_o : out std_logic_vector(31 downto 0);
csync_coarse_o : out std_logic_vector(27 downto 0);
regs_i : in t_fd_out_registers;
regs_o : out t_fd_in_registers := c_fd_in_registers_init_value);
end component;
component fd_delay_channel_driver
generic (
g_frac_bits : integer;
g_coarse_range : integer);
port (
clk_ref_i : in std_logic;
rst_n_i : in std_logic;
csync_p1_i : in std_logic;
csync_utc_i : in std_logic_vector(31 downto 0);
csync_coarse_i : in std_logic_vector(27 downto 0);
tdc_start_p1_i : in std_logic;
rearm_p1_o : out std_logic;
tag_valid_i : in std_logic;
tag_utc_i : in std_logic_vector(31 downto 0);
tag_coarse_i : in std_logic_vector(27 downto 0);
tag_frac_i : in std_logic_vector(g_frac_bits-1 downto 0);
delay_pulse_o : out std_logic;
delay_value_o : out std_logic_vector(9 downto 0);
delay_load_o : out std_logic;
delay_load_done_i : in std_logic;
dcr_mode_i : in std_logic;
dcr_enable_i : in std_logic;
dcr_pg_arm_i : in std_logic;
dcr_pg_arm_o : out std_logic;
dcr_pg_arm_load_i : in std_logic;
dcr_pg_trig_o : out std_logic;
dcr_update_i : in std_logic;
dcr_upd_done_o : out std_logic;
dcr_force_cp_i : in std_logic;
dcr_pol_i : in std_logic;
frr_i : in std_logic_vector(9 downto 0);
u_start_i : in std_logic_vector(31 downto 0);
c_start_i : in std_logic_vector(27 downto 0);
f_start_i : in std_logic_vector(g_frac_bits-1 downto 0);
u_end_i : in std_logic_vector(31 downto 0);
c_end_i : in std_logic_vector(27 downto 0);
f_end_i : in std_logic_vector(g_frac_bits-1 downto 0));
end component;
component fd_delay_line_arbiter
port (
clk_ref_i : in std_logic;
rst_n_i : in std_logic;
wr_time_valid_i : in std_logic;
wr_utc_i : in std_logic_vector(31 downto 0);
wr_coarse_i : in std_logic_vector(27 downto 0);
csync_p1_o : out std_logic;
csync_utc_o : out std_logic_vector(31 downto 0);
csync_coarse_o : out std_logic_vector(27 downto 0);
regs_b : inout t_fd_registers);
clk_ref_i : in std_logic;
rst_n_i : in std_logic;
load_i : in std_logic_vector(3 downto 0);
done_o : out std_logic_vector(3 downto 0);
delay_val0_i : in std_logic_vector(9 downto 0);
delay_val1_i : in std_logic_vector(9 downto 0);
delay_val2_i : in std_logic_vector(9 downto 0);
delay_val3_i : in std_logic_vector(9 downto 0);
delay_val_o : out std_logic_vector(9 downto 0);
delay_len_o : out std_logic_vector(3 downto 0));
end component;
component fd_ring_buffer
......@@ -218,17 +294,29 @@ architecture rtl of fine_delay_core is
g_size_log2 : integer;
g_frac_bits : integer);
port (
rst_n_sys_i : in std_logic;
rst_n_ref_i : in std_logic;
clk_ref_i : in std_logic;
clk_sys_i : in std_logic;
tag_valid_i : in std_logic;
tag_utc_i : in std_logic_vector(31 downto 0);
tag_coarse_i : in std_logic_vector(27 downto 0);
tag_frac_i : in std_logic_vector(g_frac_bits-1 downto 0);
advance_rbuf_i : in std_logic;
buf_irq_o : out std_logic;
regs_b : inout t_fd_registers);
rst_n_sys_i : in std_logic;
rst_n_ref_i : in std_logic;
clk_ref_i : in std_logic;
clk_sys_i : in std_logic;
tag_valid_i : in std_logic;
tag_utc_i : in std_logic_vector(31 downto 0);
tag_coarse_i : in std_logic_vector(27 downto 0);
tag_frac_i : in std_logic_vector(g_frac_bits-1 downto 0);
advance_rbuf_i : in std_logic;
buf_irq_o : out std_logic;
regs_i : in t_fd_out_registers;
regs_o : out t_fd_in_registers := c_fd_in_registers_init_value);
end component;
component fd_rearm_generator
port (
clk_ref_i : in std_logic;
rst_n_i : in std_logic;
tag_valid_i : in std_logic;
rearm_i : in std_logic_vector(3 downto 0);
dcr_enable_i : in std_logic_vector(3 downto 0);
dcr_mode_i : in std_logic_vector(3 downto 0);
rearm_p1_o : out std_logic);
end component;
signal tag_frac : std_logic_vector(c_TIMESTAMP_FRAC_BITS-1 downto 0);
......@@ -236,19 +324,79 @@ architecture rtl of fine_delay_core is
signal tag_utc : std_logic_vector(31 downto 0);
signal tag_valid : std_logic;
signal rbuf_frac : std_logic_vector(c_TIMESTAMP_FRAC_BITS-1 downto 0);
signal rbuf_coarse : std_logic_vector(27 downto 0);
signal rbuf_utc : std_logic_vector(31 downto 0);
signal rbuf_valid : std_logic;
signal master_csync_p1 : std_logic;
signal master_csync_utc : std_logic_vector(31 downto 0);
signal master_csync_coarse : std_logic_vector(27 downto 0);
signal rst_n_sys, rst_n_ref : std_logic;
signal regs : t_fd_registers := c_fd_registers_init_value;
signal advance_rbuf : std_logic;
signal rbuf_irq : std_logic;
type t_dly_array is array (integer range <>) of std_logic_vector(9 downto 0);
signal tdc_rearm_p1 : std_logic;
signal tdc_start_p1 : std_logic;
signal dcr_enable_vec : std_logic_vector(3 downto 0);
signal dcr_mode_vec : std_logic_vector(3 downto 0);
signal chx_rearm : std_logic_vector(3 downto 0);
signal chx_delay_pulse : std_logic_vector(3 downto 0);
signal chx_delay_value : t_dly_array(0 to 3);
signal chx_delay_load : std_logic_vector(3 downto 0);
signal chx_delay_load_done : std_logic_vector(3 downto 0);
signal fan_out : t_wishbone_master_out_array(0 to 2);
signal fan_in : t_wishbone_master_in_array(0 to 2);
signal wb_in : t_wishbone_slave_in;
signal wb_out : t_wishbone_slave_out;
signal regs_fromwb : t_fd_out_registers;
signal regs_towb_csync : t_fd_in_registers;
signal regs_towb_tsu : t_fd_in_registers;
signal regs_towb_rbuf : t_fd_in_registers;
signal regs_towb_local : t_fd_in_registers := c_fd_in_registers_init_value;
signal regs_towb : t_fd_in_registers;
signal spi_cs_vec : std_logic_vector(7 downto 0);
signal owr_en_int : std_logic_vector(0 downto 0);
signal owr_int : std_logic_vector(0 downto 0);
signal dbg : std_logic_vector(3 downto 0);
begin -- rtl
wb_in.adr(7 downto 0) <= wb_adr_i;
wb_in.cyc <= wb_cyc_i;
wb_in.stb <= wb_stb_i;
wb_in.we <= wb_we_i;
wb_in.dat <= wb_dat_i;
wb_in.sel <= "1111";
wb_ack_o <= wb_out.ack;
wb_dat_o <= wb_out.dat;
U_WB_Fanout : xwb_bus_fanout
generic map (
g_num_outputs => 3,
g_bits_per_slave => 6)
port map (
clk_sys_i => clk_sys_i,
rst_n_i => rst_n_i,
slave_i => wb_in,
slave_o => wb_out,
master_i => fan_in,
master_o => fan_out);
U_Reset_Generator : fd_reset_generator
port map (
clk_sys_i => clk_sys_i,
......@@ -256,12 +404,11 @@ begin -- rtl
rst_n_i => rst_n_i,
rst_n_sys_o => rst_n_sys,
rst_n_ref_o => rst_n_ref,
regs_b => regs);
regs_i => regs_fromwb);
U_Csync_generator : fd_csync_generator
generic map (
g_coarse_range => c_REF_CLK_FREQ,
g_frac_bits => c_TIMESTAMP_FRAC_BITS)
g_coarse_range => c_REF_CLK_FREQ)
port map (
clk_ref_i => clk_ref_i,
rst_n_i => rst_n_ref,
......@@ -271,35 +418,63 @@ begin -- rtl
csync_p1_o => master_csync_p1,
csync_utc_o => master_csync_utc,
csync_coarse_o => master_csync_coarse,
regs_b => regs);
regs_i => regs_fromwb,
regs_o => regs_towb_csync);
U_GPIO : fd_gpio
U_SPI_Master : xwb_spi
generic map (
g_interface_mode => CLASSIC)
port map (
clk_sys_i => clk_sys_i,
rst_n_i => rst_n_sys,
spi_cs_dac_n_o => spi_cs_dac_n_o,
spi_cs_pll_n_o => spi_cs_pll_n_o,
spi_cs_gpio_n_o => spi_cs_gpio_n_o,
spi_sclk_o => spi_sclk_o,
spi_mosi_o => spi_mosi_o,
spi_miso_i => spi_miso_i,
regs_b => regs);
U_Wishbon_Slave : fd_wishbone_slave
clk_sys_i => clk_sys_i,
rst_n_i => rst_n_i,
slave_i => fan_out(1),
slave_o => fan_in(1),
pad_cs_o => spi_cs_vec,
pad_sclk_o => spi_sclk_o,
pad_mosi_o => spi_mosi_o,
pad_miso_i => spi_miso_i);
spi_cs_dac_n_o <= spi_cs_vec(0);
spi_cs_pll_n_o <= spi_cs_vec(1);
spi_cs_gpio_n_o <= spi_cs_vec(2);
U_Onewire : xwb_onewire_master
generic map (
g_interface_mode => CLASSIC,
g_num_ports => 1)
port map (
clk_sys_i => clk_sys_i,
rst_n_i => rst_n_i,
slave_i => fan_out(2),
slave_o => fan_in(2),
desc_o => open,
owr_pwren_o => open,
owr_en_o => owr_en_int,
owr_i => owr_int);
owr_en_o <= owr_en_int(0);
owr_int(0) <= owr_i;
regs_towb <= regs_towb_csync or regs_towb_tsu or regs_towb_rbuf or regs_towb_local;
U_Wishbone_Slave : fd_wishbone_slave
port map (
rst_n_i => rst_n_i,
wb_clk_i => clk_sys_i,
wb_addr_i => wb_adr_i(5 downto 0),
wb_data_i => wb_dat_i,
wb_data_o => wb_dat_o,
wb_cyc_i => wb_cyc_i,
wb_addr_i => fan_out(0).adr(5 downto 0),
wb_data_i => fan_out(0).dat,
wb_data_o => fan_in(0).dat,
wb_cyc_i => fan_out(0).cyc,
wb_sel_i => "1111",
wb_stb_i => wb_stb_i,
wb_we_i => wb_we_i,
wb_ack_o => wb_ack_o,
wb_stb_i => fan_out(0).stb,
wb_we_i => fan_out(0).we,
wb_ack_o => fan_in(0).ack,
clk_ref_i => clk_ref_i,
regs_b => regs,
regs_o => regs_fromwb,
regs_i => regs_towb,
irq_ts_buf_notempty_i => rbuf_irq,
advance_rbuf_o => advance_rbuf
);
......@@ -333,14 +508,35 @@ begin -- rtl
tag_utc_o => tag_utc,
tag_valid_o => tag_valid,
tag_rearm_p1_i => '1',
tag_rearm_p1_i => tdc_rearm_p1,
csync_coarse_i => master_csync_coarse,
csync_utc_i => master_csync_utc,
csync_p1_i => master_csync_p1,
regs_b => regs
);
tdc_start_p1_o => tdc_start_p1,
regs_i => regs_fromwb,
regs_o => regs_towb_tsu,
dbg_o => dbg);
U_Normalize_for_rbuf : fd_ts_normalizer
generic map (
g_frac_bits => c_TIMESTAMP_FRAC_BITS,
g_coarse_bits => 28,
g_utc_bits => 32,
g_coarse_range => c_REF_CLK_FREQ)
port map (
clk_i => clk_ref_i,
rst_n_i => rst_n_ref,
valid_i => tag_valid,
utc_i => tag_utc,
coarse_i => tag_coarse,
frac_i => tag_frac,
valid_o => rbuf_valid,
utc_o => rbuf_utc,
coarse_o => rbuf_coarse,
frac_o => rbuf_frac);
U_Ring_Buffer : fd_ring_buffer
generic map (
......@@ -352,17 +548,228 @@ begin -- rtl
clk_ref_i => clk_ref_i,
clk_sys_i => clk_sys_i,
tag_valid_i => tag_valid,
tag_utc_i => tag_utc,
tag_coarse_i => tag_coarse,
tag_frac_i => tag_frac,
tag_valid_i => rbuf_valid,
tag_utc_i => rbuf_utc,
tag_coarse_i => rbuf_coarse,
tag_frac_i => rbuf_frac,
advance_rbuf_i => advance_rbuf,
buf_irq_o => rbuf_irq,
regs_b => regs);
regs_i => regs_fromwb,
regs_o => regs_towb_rbuf);
U_Delay_Channel_1 : fd_delay_channel_driver
generic map (
g_frac_bits => c_TIMESTAMP_FRAC_BITS,
g_coarse_range => c_REF_CLK_FREQ)
port map (
clk_ref_i => clk_ref_i,
rst_n_i => rst_n_ref,
csync_p1_i => master_csync_p1,
csync_utc_i => master_csync_utc,
csync_coarse_i => master_csync_coarse,
rearm_p1_o => chx_rearm(0),
tdc_start_p1_i => tdc_start_p1,
tag_valid_i => tag_valid,
tag_utc_i => tag_utc,
tag_coarse_i => tag_coarse,
tag_frac_i => tag_frac,
delay_pulse_o => chx_delay_pulse(0),
delay_value_o => chx_delay_value(0),
delay_load_o => chx_delay_load(0),
delay_load_done_i => chx_delay_load_done(0),
dcr_mode_i => regs_fromwb.dcr1_mode_o,
dcr_enable_i => regs_fromwb.dcr1_enable_o,
dcr_pg_arm_i => regs_fromwb.dcr1_pg_arm_o,
dcr_pg_arm_o => regs_towb_local.dcr1_pg_arm_i,
dcr_pg_arm_load_i => regs_fromwb.dcr1_pg_arm_load_o,
dcr_pg_trig_o => regs_towb_local.dcr1_pg_trig_i,
dcr_update_i => regs_fromwb.dcr1_update_o,
dcr_upd_done_o => regs_towb_local.dcr1_upd_done_i,
dcr_force_cp_i => regs_fromwb.dcr1_force_cp_o,
dcr_pol_i => regs_fromwb.dcr1_pol_o,
frr_i => regs_fromwb.frr1_o,
u_start_i => regs_fromwb.u_start1_o,
c_start_i => regs_fromwb.c_start1_o,
f_start_i => regs_fromwb.f_start1_o,
u_end_i => regs_fromwb.u_end1_o,
c_end_i => regs_fromwb.c_end1_o,
f_end_i => regs_fromwb.f_end1_o);
--chx_delay_pulse(1) <= dbg(0);
--chx_delay_pulse(2) <= dbg(1);
--chx_delay_pulse(3) <= dbg(2);
U_Delay_Channel_2 : fd_delay_channel_driver
generic map (
g_frac_bits => c_TIMESTAMP_FRAC_BITS,
g_coarse_range => c_REF_CLK_FREQ)
port map (
clk_ref_i => clk_ref_i,
rst_n_i => rst_n_ref,
csync_p1_i => master_csync_p1,
csync_utc_i => master_csync_utc,
csync_coarse_i => master_csync_coarse,
rearm_p1_o => chx_rearm(1),
tdc_start_p1_i => tdc_start_p1,
tag_valid_i => tag_valid,
tag_utc_i => tag_utc,
tag_coarse_i => tag_coarse,
tag_frac_i => tag_frac,
delay_pulse_o => chx_delay_pulse(1),
delay_value_o => chx_delay_value(1),
delay_load_o => chx_delay_load(1),
delay_load_done_i => chx_delay_load_done(1),
dcr_mode_i => regs_fromwb.dcr2_mode_o,
dcr_enable_i => regs_fromwb.dcr2_enable_o,
dcr_pg_arm_i => regs_fromwb.dcr2_pg_arm_o,
dcr_pg_arm_o => regs_towb_local.dcr2_pg_arm_i,
dcr_pg_arm_load_i => regs_fromwb.dcr2_pg_arm_load_o,
dcr_pg_trig_o => regs_towb_local.dcr2_pg_trig_i,
dcr_update_i => regs_fromwb.dcr2_update_o,
dcr_upd_done_o => regs_towb_local.dcr2_upd_done_i,
dcr_force_cp_i => regs_fromwb.dcr2_force_cp_o,
dcr_pol_i => regs_fromwb.dcr2_pol_o,
frr_i => regs_fromwb.frr2_o,
u_start_i => regs_fromwb.u_start2_o,
c_start_i => regs_fromwb.c_start2_o,
f_start_i => regs_fromwb.f_start2_o,
u_end_i => regs_fromwb.u_end2_o,
c_end_i => regs_fromwb.c_end2_o,
f_end_i => regs_fromwb.f_end2_o);
U_Delay_Channel_3 : fd_delay_channel_driver
generic map (
g_frac_bits => c_TIMESTAMP_FRAC_BITS,
g_coarse_range => c_REF_CLK_FREQ)
port map (
clk_ref_i => clk_ref_i,
rst_n_i => rst_n_ref,
csync_p1_i => master_csync_p1,
csync_utc_i => master_csync_utc,
csync_coarse_i => master_csync_coarse,
rearm_p1_o => chx_rearm(2),
tdc_start_p1_i => tdc_start_p1,
tag_valid_i => tag_valid,
tag_utc_i => tag_utc,
tag_coarse_i => tag_coarse,
tag_frac_i => tag_frac,
delay_pulse_o => chx_delay_pulse(2),
delay_value_o => chx_delay_value(2),
delay_load_o => chx_delay_load(2),
delay_load_done_i => chx_delay_load_done(2),
dcr_mode_i => regs_fromwb.dcr3_mode_o,
dcr_enable_i => regs_fromwb.dcr3_enable_o,
dcr_pg_arm_i => regs_fromwb.dcr3_pg_arm_o,
dcr_pg_arm_o => regs_towb_local.dcr3_pg_arm_i,
dcr_pg_arm_load_i => regs_fromwb.dcr3_pg_arm_load_o,
dcr_pg_trig_o => regs_towb_local.dcr3_pg_trig_i,
dcr_update_i => regs_fromwb.dcr3_update_o,
dcr_upd_done_o => regs_towb_local.dcr3_upd_done_i,
dcr_force_cp_i => regs_fromwb.dcr3_force_cp_o,
dcr_pol_i => regs_fromwb.dcr3_pol_o,
frr_i => regs_fromwb.frr3_o,
u_start_i => regs_fromwb.u_start3_o,
c_start_i => regs_fromwb.c_start3_o,
f_start_i => regs_fromwb.f_start3_o,
u_end_i => regs_fromwb.u_end3_o,
c_end_i => regs_fromwb.c_end3_o,
f_end_i => regs_fromwb.f_end3_o);
U_Delay_Channel_4 : fd_delay_channel_driver
generic map (
g_frac_bits => c_TIMESTAMP_FRAC_BITS,
g_coarse_range => c_REF_CLK_FREQ)
port map (
clk_ref_i => clk_ref_i,
rst_n_i => rst_n_ref,
csync_p1_i => master_csync_p1,
csync_utc_i => master_csync_utc,
csync_coarse_i => master_csync_coarse,
rearm_p1_o => chx_rearm(3),
tdc_start_p1_i => tdc_start_p1,
tag_valid_i => tag_valid,
tag_utc_i => tag_utc,
tag_coarse_i => tag_coarse,
tag_frac_i => tag_frac,
delay_pulse_o => chx_delay_pulse(3),
delay_value_o => chx_delay_value(3),
delay_load_o => chx_delay_load(3),
delay_load_done_i => chx_delay_load_done(3),
dcr_mode_i => regs_fromwb.dcr4_mode_o,
dcr_enable_i => regs_fromwb.dcr4_enable_o,
dcr_pg_arm_i => regs_fromwb.dcr4_pg_arm_o,
dcr_pg_arm_o => regs_towb_local.dcr4_pg_arm_i,
dcr_pg_arm_load_i => regs_fromwb.dcr4_pg_arm_load_o,
dcr_pg_trig_o => regs_towb_local.dcr4_pg_trig_i,
dcr_update_i => regs_fromwb.dcr4_update_o,
dcr_upd_done_o => regs_towb_local.dcr4_upd_done_i,
dcr_force_cp_i => regs_fromwb.dcr4_force_cp_o,
dcr_pol_i => regs_fromwb.dcr4_pol_o,
frr_i => regs_fromwb.frr4_o,
u_start_i => regs_fromwb.u_start4_o,
c_start_i => regs_fromwb.c_start4_o,
f_start_i => regs_fromwb.f_start4_o,
u_end_i => regs_fromwb.u_end4_o,
c_end_i => regs_fromwb.c_end4_o,
f_end_i => regs_fromwb.f_end4_o);
U_Delay_Line_Arbiter : fd_delay_line_arbiter
port map (
clk_ref_i => clk_ref_i,
rst_n_i => rst_n_ref,
load_i => chx_delay_load,
done_o => chx_delay_load_done,
delay_val0_i => chx_delay_value(0),
delay_val1_i => chx_delay_value(1),
delay_val2_i => chx_delay_value(2),
delay_val3_i => chx_delay_value(3),
delay_val_o => delay_val_o,
delay_len_o => delay_len_o);
dcr_enable_vec(0) <= regs_fromwb.dcr1_enable_o;
dcr_enable_vec(1) <= regs_fromwb.dcr2_enable_o;
dcr_enable_vec(2) <= regs_fromwb.dcr3_enable_o;
dcr_enable_vec(3) <= regs_fromwb.dcr4_enable_o;
dcr_mode_vec(0) <= regs_fromwb.dcr1_mode_o;
dcr_mode_vec(1) <= regs_fromwb.dcr2_mode_o;
dcr_mode_vec(2) <= regs_fromwb.dcr3_mode_o;
dcr_mode_vec(3) <= regs_fromwb.dcr4_mode_o;
U_Rearm_TDC : fd_rearm_generator
port map (
clk_ref_i => clk_ref_i,
rst_n_i => rst_n_ref,
tag_valid_i => tag_valid,
rearm_i => chx_rearm,
dcr_enable_i => dcr_enable_vec,
dcr_mode_i => dcr_mode_vec,
rearm_p1_o => tdc_rearm_p1);
U_LED_Driver : gc_extend_pulse
generic map (
g_width => 10000000)
port map (
clk_i => clk_ref_i,
rst_n_i => rst_n_ref,
pulse_i => tag_valid,
extended_o => led_trig_o);
trig_cal_o <= '0';
regs_towb_local.tdcsr_load_i <= '0';
regs_towb_local.tdcsr_empty_i <= acam_emptyf_i;
delay_pulse_o <= chx_delay_pulse;
trig_cal_o <= '0';
regs.tdcsr_load_i <= '0';
regs.tdcsr_empty_i <= acam_emptyf_i;
end rtl;
hdl/syn/spec_1_1/Manifest.py
View file @ e502cb54
......@@ -7,6 +7,6 @@ syn_device = "xc6slx45t"
syn_grade = "-3"
syn_package = "fgg484"
syn_top = "spec_top"
syn_project = "finedelay_spec_1_1.xise"
syn_project = "spec_fine_delay.xise"
modules = { "local" : [ "../../top/spec_1_1" ] }
hdl/syn/spec_1_1/spec_fine_delay.xise 0 → 100644
View file @ e502cb54
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
<project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
<header>
<!-- ISE source project file created by Project Navigator. -->
<!-- -->
<!-- This file contains project source information including a list of -->
<!-- project source files, project and process properties. This file, -->
<!-- along with the project source files, is sufficient to open and -->
<!-- implement in ISE Project Navigator. -->
<!-- -->
<!-- Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved. -->
</header>
<autoManagedFiles>
<!-- The following files are identified by `include statements in verilog -->
<!-- source files and are automatically managed by Project Navigator. -->
<!-- -->
<!-- Do not hand-edit this section, as it will be overwritten when the -->
<!-- project is analyzed based on files automatically identified as -->
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<property xil_pn:name="AES Key (Hex String) spartan6" xil_pn:value="" xil_pn:valueState="default"/>
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<property xil_pn:name="Delay Values To Be Read from SDF" xil_pn:value="Setup Time" xil_pn:valueState="default"/>
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<property xil_pn:name="Mask Pins for Multi-Pin Wake-Up Suspend Mode spartan6" xil_pn:value="0x00" xil_pn:valueState="default"/>
<property xil_pn:name="Max Fanout" xil_pn:value="100000" xil_pn:valueState="default"/>
<property xil_pn:name="Maximum Compression" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Maximum Number of Lines in Report" xil_pn:value="1000" xil_pn:valueState="default"/>
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<property xil_pn:name="MultiBoot: Starting Address for Golden Configuration spartan6" xil_pn:value="0x00000000" xil_pn:valueState="default"/>
<property xil_pn:name="MultiBoot: Starting Address for Next Configuration spartan6" xil_pn:value="0x00000000" xil_pn:valueState="default"/>
<property xil_pn:name="MultiBoot: Use New Mode for Next Configuration spartan6" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="MultiBoot: User-Defined Register for Failsafe Scheme spartan6" xil_pn:value="0x0000" xil_pn:valueState="default"/>
<property xil_pn:name="Netlist Hierarchy" xil_pn:value="As Optimized" xil_pn:valueState="default"/>
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<property xil_pn:name="Number of Clock Buffers" xil_pn:value="16" xil_pn:valueState="default"/>
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<property xil_pn:name="Number of Paths in Error/Verbose Report Post Trace" xil_pn:value="3" xil_pn:valueState="default"/>
<property xil_pn:name="Optimization Effort spartan6" xil_pn:value="Normal" xil_pn:valueState="default"/>
<property xil_pn:name="Optimization Goal" xil_pn:value="Speed" xil_pn:valueState="default"/>
<property xil_pn:name="Optimize Instantiated Primitives" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Other Bitgen Command Line Options spartan6" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Compiler Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Compiler Options Map" xil_pn:value="" xil_pn:valueState="default"/>
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<property xil_pn:name="Other Compiler Options Translate" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Compxlib Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Map Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other NETGEN Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Ngdbuild Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Place &amp; Route Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Simulator Commands Behavioral" xil_pn:value="" xil_pn:valueState="default"/>
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<property xil_pn:name="Other XPWR Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other XST Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Output Extended Identifiers" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Output File Name" xil_pn:value="spec_top" xil_pn:valueState="default"/>
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<property xil_pn:name="Package" xil_pn:value="fgg484" xil_pn:valueState="default"/>
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<property xil_pn:name="Place MultiBoot Settings into Bitstream spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
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<property xil_pn:name="Property Specification in Project File" xil_pn:value="Store all values" xil_pn:valueState="default"/>
<property xil_pn:name="RAM Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
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<property xil_pn:name="Rename Top Level Architecture To" xil_pn:value="Structure" xil_pn:valueState="default"/>
<property xil_pn:name="Rename Top Level Entity to" xil_pn:value="" xil_pn:valueState="default"/>
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<property xil_pn:name="Report Paths by Endpoint" xil_pn:value="3" xil_pn:valueState="default"/>
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<property xil_pn:name="Run Design Rules Checker (DRC)" xil_pn:value="false" xil_pn:valueState="non-default"/>
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<property xil_pn:name="Safe Implementation" xil_pn:value="No" xil_pn:valueState="default"/>
<property xil_pn:name="Security" xil_pn:value="Enable Readback and Reconfiguration" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="" xil_pn:valueState="default"/>
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<property xil_pn:name="Selected Simulation Source Node" xil_pn:value="UUT" xil_pn:valueState="default"/>
<property xil_pn:name="Set SPI Configuration Bus Width spartan6" xil_pn:value="1" xil_pn:valueState="default"/>
<property xil_pn:name="Setup External Master Clock Division spartan6" xil_pn:value="1" xil_pn:valueState="default"/>
<property xil_pn:name="Shift Register Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
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<property xil_pn:name="Show All Models" xil_pn:value="false" xil_pn:valueState="default"/>
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<property xil_pn:name="Speed Grade" xil_pn:value="-3" xil_pn:valueState="default"/>
<property xil_pn:name="Starting Placer Cost Table (1-100) Map spartan6" xil_pn:value="1" xil_pn:valueState="default"/>
<property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/>
<property xil_pn:name="Target Simulator" xil_pn:value="Please Specify" xil_pn:valueState="default"/>
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<property xil_pn:name="Top-Level Module Name in Output Netlist" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Top-Level Source Type" xil_pn:value="HDL" xil_pn:valueState="default"/>
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<property xil_pn:name="Unused IOB Pins" xil_pn:value="Float" xil_pn:valueState="non-default"/>
<property xil_pn:name="Use 64-bit PlanAhead on 64-bit Systems" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Use Clock Enable" xil_pn:value="Auto" xil_pn:valueState="default"/>
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<property xil_pn:name="Use Custom Simulation Command File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/>
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<property xil_pn:name="Use Custom Waveform Configuration File Behav" xil_pn:value="false" xil_pn:valueState="default"/>
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<property xil_pn:name="Use DSP Block spartan6" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Use LOC Constraints" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Use RLOC Constraints" xil_pn:value="Yes" xil_pn:valueState="default"/>
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<property xil_pn:name="Use Synthesis Constraints File" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="User Browsed Strategy Files" xil_pn:value="/opt/Xilinx/13.1/ISE_DS/ISE/data/default.xds" xil_pn:valueState="non-default"/>
<property xil_pn:name="UserID Code (8 Digit Hexadecimal)" xil_pn:value="0xFFFFFFFF" xil_pn:valueState="default"/>
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<property xil_pn:name="VHDL Source Analysis Standard" xil_pn:value="VHDL-93" xil_pn:valueState="default"/>
<property xil_pn:name="Value Range Check" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Verilog Macros" xil_pn:value="" xil_pn:valueState="default"/>
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<property xil_pn:name="Wakeup Clock spartan6" xil_pn:value="Startup Clock" xil_pn:valueState="default"/>
<property xil_pn:name="Watchdog Timer Value spartan6" xil_pn:value="0xFFFF" xil_pn:valueState="default"/>
<property xil_pn:name="Working Directory" xil_pn:value="." xil_pn:valueState="non-default"/>
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<property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="spartan6" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_FPGAConfiguration" xil_pn:value="FPGAConfiguration" xil_pn:valueState="default"/>
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<property xil_pn:name="PROP_PostSynthSimTop" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_PostXlateSimTop" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_PreSynthesis" xil_pn:value="PreSynthesis" xil_pn:valueState="default"/>
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<library xil_pn:name="blk_mem_gen_v4_1"/>
<library xil_pn:name="fifo_generator_v6_1"/>
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<file xil_pn:name="../../top/spec_1_1/spec_top.ucf" xil_pn:type="FILE_UCF">
<association xil_pn:name="Implementation" xil_pn:seqID="1"/>
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<file xil_pn:name="../../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_v4_1_defaults.vhd" xil_pn:type="FILE_VHDL">
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<association xil_pn:name="Implementation" xil_pn:seqID="175"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_dual_pi_controller.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="176"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_serial_dac.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="177"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_sync_ffs.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="178"/>
</file>
<file xil_pn:name="../../rtl/fd_ring_buffer.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="179"/>
</file>
<file xil_pn:name="../../top/spec_1_1/spec_top.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="180"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/genrams/xilinx/generic_async_fifo.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="181"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/genrams/xilinx/generic_dpram.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="182"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/genrams/xilinx/generic_spram.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="183"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/genrams/xilinx/generic_sync_fifo.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="184"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_onewire_master/wb_onewire_master.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="185"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_onewire_master/xwb_onewire_master.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="186"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_onewire_master/sockit_owm.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="Implementation" xil_pn:seqID="187"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/i2c_master_bit_ctrl.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="188"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/i2c_master_byte_ctrl.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="189"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/i2c_master_top.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="190"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/wb_i2c_master.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="191"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/xwb_i2c_master.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="192"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_bus_fanout/xwb_bus_fanout.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="193"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_conmax/wb_conmax_pri_dec.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="194"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_conmax/wb_conmax_pri_enc.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="195"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_conmax/wb_conmax_arb.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="196"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_conmax/wb_conmax_msel.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="197"/>
</file>
<file xil_pn:name="../../ip_cores/wr-cores/modules/wrc_core/wr_core.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="198"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_conmax/wb_conmax_slave_if.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="199"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_conmax/wb_conmax_master_if.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="200"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_conmax/wb_conmax_rf.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="201"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_conmax/wb_conmax_top.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="202"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="203"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_gpio_port/xwb_gpio_port.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="204"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_simple_timer/wb_tics.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="205"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_uart/uart_async_rx.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="206"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_uart/uart_async_tx.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="207"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_uart/uart_baud_gen.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="208"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_uart/uart_wb_slave.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="209"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_uart/wb_simple_uart.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="210"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_vic/vic_prio_enc.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="211"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_vic/wb_vic.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="212"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_spi/spi_clgen.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="Implementation" xil_pn:seqID="213"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_spi/spi_shift.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="Implementation" xil_pn:seqID="214"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_spi/spi_top.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="Implementation" xil_pn:seqID="215"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_spi/wb_spi.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="216"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_spi/xwb_spi.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="217"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_virtual_uart/wb_virtual_uart.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="218"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_virtual_uart/wb_virtual_uart_slave.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="219"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_dpssram.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="220"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_eic.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="221"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_fifo_async.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="222"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_fifo_sync.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="223"/>
</file>
<file xil_pn:name="../../rtl/fd_wishbone_slave.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="224"/>
</file>
<file xil_pn:name="../../ip_cores/gn4124-core/branches/hdlmake-compliant/rtl/spartan6/gn4124_core.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="225"/>
</file>
<file xil_pn:name="../../ip_cores/gn4124-core/branches/hdlmake-compliant/rtl/dma_controller.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="226"/>
</file>
<file xil_pn:name="../../ip_cores/gn4124-core/branches/hdlmake-compliant/rtl/spartan6/l2p_ser.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="227"/>
</file>
<file xil_pn:name="../../ip_cores/gn4124-core/branches/hdlmake-compliant/rtl/spartan6/p2l_des.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="228"/>
</file>
<file xil_pn:name="../../ip_cores/gn4124-core/branches/hdlmake-compliant/rtl/spartan6/serdes_1_to_n_clk_pll_s2_diff.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="229"/>
</file>
<file xil_pn:name="../../ip_cores/gn4124-core/branches/hdlmake-compliant/rtl/spartan6/serdes_1_to_n_data_s2_se.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="230"/>
</file>
<file xil_pn:name="../../ip_cores/gn4124-core/branches/hdlmake-compliant/rtl/spartan6/serdes_n_to_1_s2_diff.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="231"/>
</file>
<file xil_pn:name="../../ip_cores/gn4124-core/branches/hdlmake-compliant/rtl/spartan6/serdes_n_to_1_s2_se.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="232"/>
</file>
</files>
<bindings/>
<version xil_pn:ise_version="13.1" xil_pn:schema_version="2"/>
</project>
hdl/testbench/top/main.sv
View file @ e502cb54
......@@ -6,6 +6,7 @@
`include "jittery_delay.sv"
`include "fine_delay_regs.v"
`include "ideal_timestamper.sv"
`include "mc100ep195.sv"
`include "simdrv_defs.svh"
`include "wb/if_wb_master.svh"
......@@ -18,7 +19,7 @@ module clock_reset_gen
output clk_ref_o,
output clk_tdc_o,
output reg rst_n_o);
parameter real g_ref_period = 8ns;
parameter real g_sys_period = 16.31ns;
parameter real g_ref_jitter = 10ps;
......@@ -72,9 +73,15 @@ module clock_reset_gen
endmodule // clock_reset_gen
const int SPI_PLL = 0;
const int SPI_GPIO = 1;
const int SPI_DAC = 2;
class CSimDrv_FineDelay;
protected CBusAccessor m_acc;
protected Timestamp ts_queue[$];
const real c_acam_bin = 27.012; // [ps]
const real c_ref_period = 8000; // [ps]
const int c_frac_bits = 12;
......@@ -99,10 +106,12 @@ class CSimDrv_FineDelay;
m_acc.write(`ADDR_FD_TDCSR, `FD_TDCSR_READ);
#(500ns);
m_acc.read(`ADDR_FD_TAR, rval);
value = rval;
value = rval;
endtask // acam_read
task csync_int();
m_acc.write(`ADDR_FD_GCR, `FD_GCR_CSYNC_INT);
endtask // csync_int
......@@ -110,20 +119,86 @@ class CSimDrv_FineDelay;
task csync_wr();
m_acc.write(`ADDR_FD_GCR, `FD_GCR_CSYNC_WR);
endtask // csync_wr
task rbuf_update();
Timestamp ts;
uint64_t utc, coarse, seq_frac, stat;
m_acc.read(`ADDR_FD_TSBCR, stat);
// $display("TSBCR %x\n", stat);
if((stat & `FD_TSBCR_EMPTY) == 0) begin
m_acc.read(`ADDR_FD_TSBR_U, utc);
m_acc.read(`ADDR_FD_TSBR_C, coarse);
m_acc.read(`ADDR_FD_TSBR_FID, seq_frac);
ts = new (0,0,0);
ts.utc = utc;
ts.coarse = coarse & 'hfffffff;
ts.seq_id = (seq_frac >> 16) & 'hffff;
ts.frac = seq_frac & 'hfff;
ts_queue.push_back(ts);
end
endtask // rbuf_read
function int poll();
return (ts_queue.size() > 0);
endfunction // poll
function Timestamp get();
return ts_queue.pop_front();
endfunction // get
task config_output(int channel, int polarity, int delay_ps, int duration_ps);
uint64_t dcr;
Timestamp t_start, t_end;
t_start = new;
t_start.unflatten(int'(real'(delay_ps) * 4096.0 / 8000.0));
t_end = new;
t_end.unflatten(int'(real'(delay_ps + duration_ps) * 4096.0 / 8000.0));
m_acc.write('h20 * channel + `ADDR_FD_FRR1, 800);
m_acc.write('h20 * channel + `ADDR_FD_U_START1, t_start.utc);
m_acc.write('h20 * channel + `ADDR_FD_C_START1, t_start.coarse);
m_acc.write('h20 * channel + `ADDR_FD_F_START1, t_start.frac);
m_acc.write('h20 * channel + `ADDR_FD_U_END1, t_end.utc);
m_acc.write('h20 * channel + `ADDR_FD_C_END1, t_end.coarse);
m_acc.write('h20 * channel + `ADDR_FD_F_END1, t_end.frac);
dcr = `FD_DCR1_ENABLE | `FD_DCR1_UPDATE | (polarity ? `FD_DCR1_POL : 0);
m_acc.write('h20 * channel + `ADDR_FD_DCR1, dcr);
endtask // config_output
task init();
int rval;
m_acc.write(`ADDR_FD_TDCSR, `FD_TDCSR_START_DIS | `FD_TDCSR_STOP_DIS);
m_acc.write(`ADDR_FD_GCR, `FD_GCR_BYPASS);
acam_write(5, c_acam_start_offset); // set StartOffset
acam_read(5, rval);
$display("AcamReadback %x", rval);
// Clear the ring buffer
m_acc.write(`ADDR_FD_TSBCR, `FD_TSBCR_ENABLE | `FD_TSBCR_PURGE | `FD_TSBCR_RST_SEQ);
m_acc.write(`ADDR_FD_ADSFR, int' (real'(1<< (c_frac_bits + c_scaler_shift)) * c_acam_bin / c_ref_period));
$display("ADSFR: %d", int' (real'(1<< (c_frac_bits + c_scaler_shift)) * c_acam_bin / c_ref_period));
m_acc.write(`ADDR_FD_ASOR, c_acam_start_offset * 3);
m_acc.write(`ADDR_FD_ATMCR, c_acam_merge_c_threshold | (c_acam_merge_f_threshold << 4));
......@@ -139,6 +214,12 @@ class CSimDrv_FineDelay;
endtask // init
task force_cal_pulse(int channel, int delay_setpoint);
m_acc.write(`ADDR_FD_FRR1 + (channel * 'h20), delay_setpoint);
m_acc.write(`ADDR_FD_DCR1 + (channel * 'h20), `FD_DCR1_FORCE_CP | `FD_DCR1_POL);
endtask // force_cal_pulse
endclass // CSimDrv_FineDelay
......@@ -214,7 +295,7 @@ module main;
IWishboneMaster
#(
.g_addr_width(6),
.g_addr_width(8),
.g_data_width(32)
) wb_master
(
......@@ -231,6 +312,8 @@ module main;
.rst_n_o(rst_n)
);
wr_time_counter
time_counter
(
......@@ -243,9 +326,9 @@ module main;
random_pulse_gen
#(
.g_pulse_width(30ns),
.g_min_spacing(350.111ns),
.g_max_spacing(2000.112ns)
.g_pulse_width(2000ns),
.g_min_spacing(4000.111ns),
.g_max_spacing(4000.112ns)
)
TRIG_GEN
(
......@@ -332,6 +415,10 @@ module main;
.in_i(tdc_start),
.out_o(tdc_start_delayed)
);
wire [3:0] delay_len, delay_pulse;
wire [9:0] delay_val;
wire [3:0] d_out;
fine_delay_core
......@@ -365,18 +452,18 @@ module main;
.spi_cs_gpio_n_o (),
.spi_sclk_o (),
.spi_mosi_o (),
.spi_miso_i (1'b0),
.spi_mosi_o (spi_loop),
.spi_miso_i (spi_loop),
.delay_len_o (),
.delay_val_o (),
.delay_pulse_o (),
.delay_len_o (delay_len),
.delay_val_o (delay_val),
.delay_pulse_o (delay_pulse),
.wr_utc_i(wr_utc),
.wr_coarse_i(wr_coarse),
.wr_time_valid_i(wr_time_valid),
.wb_adr_i (wb_master.master.adr[5:0]),
.wb_adr_i (wb_master.master.adr[7:0]),
.wb_dat_i (wb_master.master.dat_o),
.wb_dat_o (wb_master.master.dat_i),
.wb_cyc_i (wb_master.master.cyc),
......@@ -386,8 +473,47 @@ module main;
);
const uint64_t c_coarse_range = 256;
mc100ep195
U_delay_line0(
.len(delay_len[0]),
.i(delay_pulse[0]),
.delay(delay_val),
.o(d_out[0])
); mc100ep195
U_delay_line1(
.len(delay_len[1]),
.i(delay_pulse[1]),
.delay(delay_val),
.o(d_out[1])
);
ideal_timestamper
Output_TSU0
(
.rst_n_i(rst_n),
.clk_ref_i(clk_ref),
.enable_i(~acam_stop_dis[1]),
.trig_a_i(d_out[0]),
.csync_p1_i(wr_time_valid & !wr_time_valid_d0),
.csync_utc_i(wr_utc),
.csync_coarse_i(wr_coarse)
);
ideal_timestamper
Output_TSU1
(
.rst_n_i(rst_n),
.clk_ref_i(clk_ref),
.enable_i(~acam_stop_dis[1]),
.trig_a_i(d_out[1]),
.csync_p1_i(wr_time_valid & !wr_time_valid_d0),
.csync_utc_i(wr_utc),
.csync_coarse_i(wr_coarse)
);
const uint64_t c_coarse_range = 256;
Timestamp ts_queue[$];
......@@ -399,9 +525,11 @@ module main;
ts_queue.push_back(t);
end
CSimDrv_FineDelay fd_drv;
CWishboneAccessor wb;
initial begin
CWishboneAccessor wb;
CSimDrv_FineDelay fd_drv;
int rval;
wait(rst_n != 0);
......@@ -411,27 +539,50 @@ module main;
wb = wb_master.get_accessor();
fd_drv = new(wb);
fd_drv.init();
// fd_drv.csync_wr();
// $stop;
end // initial begin
fd_drv.config_output(0,1, 1000000, 200000);
// fd_drv.config_output(1,1, 1100500, 200000);
// fd_drv.config_output(2,1, 1100900, 200000);
// fd_drv.config_output(3,1, 1110100, 200000);
// fd_drv.force_cal_pulse(0, 100);
// #(320ns);
// fd_drv.force_cal_pulse(0, 200);
forever fd_drv.rbuf_update();
end
Timestamp prev = null;
always@(posedge clk_ref)
if ((ts_queue.size() > 0) && IDEAL_TSU.poll())
always@(posedge clk_ref)
if (fd_drv != null)
begin
Timestamp t_acam;
Timestamp t_ideal;
t_acam = ts_queue.pop_front();
t_ideal = IDEAL_TSU.get();
$display("TS: %.4f", t_acam.flatten() - t_ideal.flatten());
if(fd_drv.poll() && IDEAL_TSU.poll() && Output_TSU0.poll()/* && Output_TSU1.poll()*/)
begin
real delta, delta2, delta3;
Timestamp t_acam;
Timestamp t_ideal;
Timestamp t_out0, t_out1;
t_acam = fd_drv.get();
t_ideal = IDEAL_TSU.get();
t_out0 = Output_TSU0.get();
// t_out1 = Output_TSU1.get();
delta = t_acam.flatten() - t_ideal.flatten();
delta2 = t_out0.flatten() - t_ideal.flatten();
// delta3 = t_out1.flatten() - t_ideal.flatten();
$display("TS: seq %d delta %.4f delta_out %.4f %.4f", t_acam.seq_id, delta, delta2, delta3);
if(delta > 0.1 || delta < -0.1)
begin
$display("TS Failure");
$stop;
end
end
end
endmodule // main
......
hdl/testbench/top/wave.do
View file @ e502cb54
onerror {resume}
quietly WaveActivateNextPane {} 0
add wave -noupdate /main/DUT/U_Acam_TSU/csync_utc_i
add wave -noupdate /main/DUT/U_Acam_TSU/csync_p1_i
add wave -noupdate /main/DUT/U_Acam_TSU/dbg_utc
add wave -noupdate /main/DUT/U_Acam_TSU/dbg_coarse
add wave -noupdate /main/time_counter/wr_utc_o
add wave -noupdate /main/time_counter/wr_coarse_o
add wave -noupdate /main/time_counter/wr_time_valid_o
add wave -noupdate /main/IDEAL_TSU/csync_p1_i
add wave -noupdate /main/IDEAL_TSU/cntr_utc
add wave -noupdate /main/IDEAL_TSU/cntr_coarse
add wave -noupdate /main/IDEAL_TSU/cntr_frac
add wave -noupdate /main/IDEAL_TSU/enable_i
add wave -noupdate /main/DUT/clk_ref_i
add wave -noupdate /main/DUT/clk_sys_i
add wave -noupdate /main/DUT/rst_n_i
add wave -noupdate /main/DUT/trig_a_n_i
add wave -noupdate /main/DUT/delay_pulse_o(0)
add wave -noupdate /main/DUT/chx_rearm
add wave -noupdate -expand /main/DUT/U_Acam_TSU/trig_d
add wave -noupdate /main/DUT/U_Acam_TSU/trig_pulse
add wave -noupdate /main/DUT/U_Acam_TSU/tag_enable
add wave -noupdate /main/DUT/trig_cal_o
add wave -noupdate /main/DUT/tdc_start_i
add wave -noupdate /main/DUT/led_trig_o
add wave -noupdate /main/DUT/acam_a_o
add wave -noupdate /main/DUT/acam_d_o
add wave -noupdate /main/DUT/acam_d_i
add wave -noupdate /main/DUT/acam_d_oen_o
add wave -noupdate /main/DUT/acam_err_i
add wave -noupdate /main/DUT/acam_int_i
add wave -noupdate /main/DUT/acam_emptyf_i
add wave -noupdate /main/DUT/acam_alutrigger_o
add wave -noupdate /main/DUT/acam_cs_n_o
add wave -noupdate /main/DUT/acam_wr_n_o
add wave -noupdate /main/DUT/acam_rd_n_o
add wave -noupdate /main/DUT/acam_start_dis_o
add wave -noupdate /main/DUT/acam_stop_dis_o
add wave -noupdate /main/DUT/spi_cs_dac_n_o
add wave -noupdate /main/DUT/spi_cs_pll_n_o
add wave -noupdate /main/DUT/spi_cs_gpio_n_o
add wave -noupdate /main/DUT/spi_sclk_o
add wave -noupdate /main/DUT/spi_mosi_o
add wave -noupdate /main/DUT/spi_miso_i
add wave -noupdate /main/DUT/delay_len_o
add wave -noupdate /main/DUT/delay_val_o
add wave -noupdate -expand /main/DUT/delay_pulse_o
add wave -noupdate /main/DUT/wr_time_valid_i
add wave -noupdate /main/DUT/wr_coarse_i
add wave -noupdate /main/DUT/wr_utc_i
add wave -noupdate /main/DUT/owr_en_o
add wave -noupdate /main/DUT/owr_i
add wave -noupdate /main/DUT/wb_adr_i
add wave -noupdate /main/DUT/wb_dat_i
add wave -noupdate /main/DUT/wb_dat_o
add wave -noupdate /main/DUT/wb_cyc_i
add wave -noupdate /main/DUT/wb_stb_i
add wave -noupdate /main/DUT/wb_we_i
add wave -noupdate /main/DUT/wb_ack_o
add wave -noupdate /main/DUT/wb_irq_o
add wave -noupdate /main/DUT/tag_frac
add wave -noupdate /main/DUT/tag_coarse
add wave -noupdate /main/DUT/tag_utc
add wave -noupdate /main/DUT/tag_valid
add wave -noupdate /main/DUT/U_Acam_TSU/acam_stop_dis_o
add wave -noupdate /main/DUT/U_Acam_TSU/tag_enable
add wave -noupdate /main/DUT/U_Acam_TSU/trig_a_n_i
add wave -noupdate /main/DUT/U_Acam_TSU/raw_tag_valid
add wave -noupdate /main/DUT/U_Acam_TSU/raw_tag_coarse
add wave -noupdate /main/DUT/U_Acam_TSU/raw_tag_frac
add wave -noupdate /main/DUT/U_Acam_TSU/raw_tag_start_offset
add wave -noupdate /main/DUT/U_Acam_TSU/raw_tag_utc
add wave -noupdate /main/DUT/rbuf_frac
add wave -noupdate /main/DUT/rbuf_coarse
add wave -noupdate /main/DUT/rbuf_utc
add wave -noupdate /main/DUT/rbuf_valid
add wave -noupdate /main/DUT/master_csync_p1
add wave -noupdate /main/DUT/master_csync_utc
add wave -noupdate /main/DUT/master_csync_coarse
add wave -noupdate /main/DUT/rst_n_sys
add wave -noupdate /main/DUT/rst_n_ref
add wave -noupdate /main/DUT/advance_rbuf
add wave -noupdate /main/DUT/rbuf_irq
add wave -noupdate /main/DUT/tdc_rearm_p1
add wave -noupdate /main/DUT/tdc_start_p1
add wave -noupdate /main/DUT/dcr_enable_vec
add wave -noupdate /main/DUT/dcr_mode_vec
add wave -noupdate /main/DUT/chx_delay_pulse
add wave -noupdate /main/DUT/chx_delay_value
add wave -noupdate /main/DUT/chx_delay_load
add wave -noupdate /main/DUT/chx_delay_load_done
add wave -noupdate /main/DUT/fan_out
add wave -noupdate /main/DUT/fan_in
add wave -noupdate /main/DUT/wb_in
add wave -noupdate /main/DUT/wb_out
add wave -noupdate /main/DUT/regs_fromwb
add wave -noupdate /main/DUT/regs_towb_csync
add wave -noupdate /main/DUT/regs_towb_tsu
add wave -noupdate /main/DUT/regs_towb_rbuf
add wave -noupdate /main/DUT/regs_towb_local
add wave -noupdate /main/DUT/regs_towb
add wave -noupdate /main/DUT/spi_cs_vec
add wave -noupdate /main/DUT/owr_en_int
add wave -noupdate /main/DUT/owr_int
TreeUpdate [SetDefaultTree]
WaveRestoreCursors {{Cursor 1} {2588000010 fs} 0}
WaveRestoreCursors {{Cursor 1} {8140001510 fs} 0}
configure wave -namecolwidth 413
configure wave -valuecolwidth 100
configure wave -justifyvalue left
......@@ -40,4 +99,4 @@ configure wave -griddelta 40
configure wave -timeline 0
configure wave -timelineunits ns
update
WaveRestoreZoom {3002500 ps} {4052500 ps}
WaveRestoreZoom {0 fs} {16800 ns}
hdl/top/spec_1_1/Manifest.py
View file @ e502cb54
files = [
"spec_top_finedelay.vhd",
"spec_top_finedelay.ucf",
"wb_gpio_port_notristates.vhd"
"spec_top.vhd",
"spec_top.ucf",
#"wb_gpio_port_notristates.vhd"
];
fetchto = "../../ip_cores"
......
hdl/top/spec_1_1/spec_top.ucf 0 → 100644
View file @ e502cb54
#bank 0
NET "CLK_20M_VCXO_I" LOC = H12;
NET "CLK_20M_VCXO_I" IOSTANDARD = "LVCMOS25";
#NET "clk_125m_pllref_n_i" LOC = F10;
#NET "clk_125m_pllref_n_i" IOSTANDARD = "LVDS_25";
#NET "clk_125m_pllref_p_i" LOC = G9;
#NET "clk_125m_pllref_p_i" IOSTANDARD = "LVDS_25";
NET "L_RST_N" LOC = N20;
NET "L_RST_N" IOSTANDARD = "LVCMOS18";
NET "L2P_CLKN" LOC = K22;
NET "L2P_CLKN" IOSTANDARD = "DIFF_SSTL18_I";
NET "L2P_CLKP" LOC = K21;
NET "L2P_CLKP" IOSTANDARD = "DIFF_SSTL18_I";
NET "L2P_DFRAME" LOC = U22;
NET "L2P_DFRAME" IOSTANDARD = "SSTL18_I";
NET "L2P_EDB" LOC = U20;
NET "L2P_EDB" IOSTANDARD = "SSTL18_I";
NET "L2P_RDY" LOC = U19;
NET "L2P_RDY" IOSTANDARD = "SSTL18_I";
NET "L2P_VALID" LOC = T18;
NET "L2P_VALID" IOSTANDARD = "SSTL18_I";
NET "L_WR_RDY[0]" LOC = R20;
NET "L_WR_RDY[0]" IOSTANDARD = "SSTL18_I";
NET "L_WR_RDY[1]" LOC = T22;
NET "L_WR_RDY[1]" IOSTANDARD = "SSTL18_I";
NET "L_CLKN" LOC = N19;
NET "L_CLKN" IOSTANDARD = "DIFF_SSTL18_I";
NET "L_CLKP" LOC = P20;
NET "L_CLKP" IOSTANDARD = "DIFF_SSTL18_I";
NET "P2L_CLKN" LOC = M19;
NET "P2L_CLKN" IOSTANDARD = "DIFF_SSTL18_I";
NET "P2L_CLKP" LOC = M20;
NET "P2L_CLKP" IOSTANDARD = "DIFF_SSTL18_I";
NET "P2L_DFRAME" LOC = J22;
NET "P2L_DFRAME" IOSTANDARD = "SSTL18_I";
NET "P2L_RDY" LOC = J16;
NET "P2L_RDY" IOSTANDARD = "SSTL18_I";
NET "P2L_VALID" LOC = L19;
NET "P2L_VALID" IOSTANDARD = "SSTL18_I";
NET "P_RD_D_RDY[0]" LOC = N16;
NET "P_RD_D_RDY[0]" IOSTANDARD = "SSTL18_I";
NET "P_RD_D_RDY[1]" LOC = P19;
NET "P_RD_D_RDY[1]" IOSTANDARD = "SSTL18_I";
NET "P_WR_RDY[0]" LOC = L15;
NET "P_WR_RDY[0]" IOSTANDARD = "SSTL18_I";
NET "P_WR_RDY[1]" LOC = K16;
NET "P_WR_RDY[1]" IOSTANDARD = "SSTL18_I";
NET "P_WR_REQ[0]" LOC = M22;
NET "P_WR_REQ[0]" IOSTANDARD = "SSTL18_I";
NET "P_WR_REQ[1]" LOC = M21;
NET "P_WR_REQ[1]" IOSTANDARD = "SSTL18_I";
NET "RX_ERROR" LOC = J17;
NET "RX_ERROR" IOSTANDARD = "SSTL18_I";
NET "TX_ERROR" LOC = M17;
NET "TX_ERROR" IOSTANDARD = "SSTL18_I";
NET "VC_RDY[0]" LOC = B21;
NET "VC_RDY[0]" IOSTANDARD = "SSTL18_I";
NET "VC_RDY[1]" LOC = B22;
NET "VC_RDY[1]" IOSTANDARD = "SSTL18_I";
NET "L2P_DATA[0]" LOC = P16;
NET "L2P_DATA[0]" IOSTANDARD = "SSTL18_I";
NET "L2P_DATA[1]" LOC = P21;
NET "L2P_DATA[1]" IOSTANDARD = "SSTL18_I";
NET "L2P_DATA[2]" LOC = P18;
NET "L2P_DATA[2]" IOSTANDARD = "SSTL18_I";
NET "L2P_DATA[3]" LOC = T20;
NET "L2P_DATA[3]" IOSTANDARD = "SSTL18_I";
NET "L2P_DATA[4]" LOC = V21;
NET "L2P_DATA[4]" IOSTANDARD = "SSTL18_I";
NET "L2P_DATA[5]" LOC = V19;
NET "L2P_DATA[5]" IOSTANDARD = "SSTL18_I";
NET "L2P_DATA[6]" LOC = W22;
NET "L2P_DATA[6]" IOSTANDARD = "SSTL18_I";
NET "L2P_DATA[7]" LOC = Y22;
NET "L2P_DATA[7]" IOSTANDARD = "SSTL18_I";
NET "L2P_DATA[8]" LOC = P22;
NET "L2P_DATA[8]" IOSTANDARD = "SSTL18_I";
NET "L2P_DATA[9]" LOC = R22;
NET "L2P_DATA[9]" IOSTANDARD = "SSTL18_I";
NET "L2P_DATA[10]" LOC = T21;
NET "L2P_DATA[10]" IOSTANDARD = "SSTL18_I";
NET "L2P_DATA[11]" LOC = T19;
NET "L2P_DATA[11]" IOSTANDARD = "SSTL18_I";
NET "L2P_DATA[12]" LOC = V22;
NET "L2P_DATA[12]" IOSTANDARD = "SSTL18_I";
NET "L2P_DATA[13]" LOC = V20;
NET "L2P_DATA[13]" IOSTANDARD = "SSTL18_I";
NET "L2P_DATA[14]" LOC = W20;
NET "L2P_DATA[14]" IOSTANDARD = "SSTL18_I";
NET "L2P_DATA[15]" LOC = Y21;
NET "L2P_DATA[15]" IOSTANDARD = "SSTL18_I";
NET "P2L_DATA[0]" LOC = K20;
NET "P2L_DATA[0]" IOSTANDARD = "SSTL18_I";
NET "P2L_DATA[1]" LOC = H22;
NET "P2L_DATA[1]" IOSTANDARD = "SSTL18_I";
NET "P2L_DATA[2]" LOC = H21;
NET "P2L_DATA[2]" IOSTANDARD = "SSTL18_I";
NET "P2L_DATA[3]" LOC = L17;
NET "P2L_DATA[3]" IOSTANDARD = "SSTL18_I";
NET "P2L_DATA[4]" LOC = K17;
NET "P2L_DATA[4]" IOSTANDARD = "SSTL18_I";
NET "P2L_DATA[5]" LOC = G22;
NET "P2L_DATA[5]" IOSTANDARD = "SSTL18_I";
NET "P2L_DATA[6]" LOC = G20;
NET "P2L_DATA[6]" IOSTANDARD = "SSTL18_I";
NET "P2L_DATA[7]" LOC = K18;
NET "P2L_DATA[7]" IOSTANDARD = "SSTL18_I";
NET "P2L_DATA[8]" LOC = K19;
NET "P2L_DATA[8]" IOSTANDARD = "SSTL18_I";
NET "P2L_DATA[9]" LOC = H20;
NET "P2L_DATA[9]" IOSTANDARD = "SSTL18_I";
NET "P2L_DATA[10]" LOC = J19;
NET "P2L_DATA[10]" IOSTANDARD = "SSTL18_I";
NET "P2L_DATA[11]" LOC = E22;
NET "P2L_DATA[11]" IOSTANDARD = "SSTL18_I";
NET "P2L_DATA[12]" LOC = E20;
NET "P2L_DATA[12]" IOSTANDARD = "SSTL18_I";
NET "P2L_DATA[13]" LOC = F22;
NET "P2L_DATA[13]" IOSTANDARD = "SSTL18_I";
NET "P2L_DATA[14]" LOC = F21;
NET "P2L_DATA[14]" IOSTANDARD = "SSTL18_I";
NET "P2L_DATA[15]" LOC = H19;
NET "P2L_DATA[15]" IOSTANDARD = "SSTL18_I";
#NET "CLK1_M2C_P" LOC = L20;
#NET "CLK1_M2C_P" IOSTANDARD = "LVDS_18";
#NET "CLK1_M2C_N" LOC = L22;
#NET "CLK1_M2C_N" IOSTANDARD = "LVDS_18";
NET "GPIO[1]" LOC = U16;
NET "GPIO[1]" IOSTANDARD = "LVCMOS25";
NET "GPIO[0]" LOC = AB19;
NET "GPIO[0]" IOSTANDARD = "LVCMOS25";
NET "LED_RED" LOC = D5;
NET "LED_RED" IOSTANDARD = "LVCMOS25";
NET "LED_GREEN" LOC = E5;
NET "LED_GREEN" IOSTANDARD = "LVCMOS25";
NET "fd_clk_ref_n_i" LOC = L22 ;
NET "fd_clk_ref_n_i" IOSTANDARD =LVDS_25;
NET "fd_clk_ref_p_i" LOC = L20 ;
NET "fd_clk_ref_p_i" IOSTANDARD =LVDS_25;
NET "fd_delay_len_o[0]" LOC = W14 ;
NET "fd_delay_len_o[0]" IOSTANDARD =LVCMOS25;
NET "fd_delay_len_o[1]" LOC = Y14 ;
NET "fd_delay_len_o[1]" IOSTANDARD =LVCMOS25;
NET "fd_delay_len_o[2]" LOC = Y18 ;
NET "fd_delay_len_o[2]" IOSTANDARD =LVCMOS25;
NET "fd_delay_len_o[3]" LOC = W17 ;
NET "fd_delay_len_o[3]" IOSTANDARD =LVCMOS25;
NET "fd_delay_pulse_o[0]" LOC = W13 ;
NET "fd_delay_pulse_o[0]" IOSTANDARD =LVCMOS25;
NET "fd_delay_pulse_o[1]" LOC = V13 ;
NET "fd_delay_pulse_o[1]" IOSTANDARD =LVCMOS25;
NET "fd_delay_pulse_o[2]" LOC = U15 ;
NET "fd_delay_pulse_o[2]" IOSTANDARD =LVCMOS25;
NET "fd_delay_pulse_o[3]" LOC = T15 ;
NET "fd_delay_pulse_o[3]" IOSTANDARD =LVCMOS25;
NET "fd_delay_val_o[0]" LOC = A20 ;
NET "fd_delay_val_o[0]" IOSTANDARD =LVCMOS25;
NET "fd_delay_val_o[1]" LOC = B20 ;
NET "fd_delay_val_o[1]" IOSTANDARD =LVCMOS25;
NET "fd_delay_val_o[2]" LOC = A19 ;
NET "fd_delay_val_o[2]" IOSTANDARD =LVCMOS25;
NET "fd_delay_val_o[3]" LOC = C19 ;
NET "fd_delay_val_o[3]" IOSTANDARD =LVCMOS25;
NET "fd_delay_val_o[4]" LOC = W18 ;
NET "fd_delay_val_o[4]" IOSTANDARD =LVCMOS25;
NET "fd_delay_val_o[5]" LOC = V17 ;
NET "fd_delay_val_o[5]" IOSTANDARD =LVCMOS25;
NET "fd_delay_val_o[6]" LOC = C18 ;
NET "fd_delay_val_o[6]" IOSTANDARD =LVCMOS25;
NET "fd_delay_val_o[7]" LOC = D17 ;
NET "fd_delay_val_o[7]" IOSTANDARD =LVCMOS25;
NET "fd_delay_val_o[8]" LOC = W15 ;
NET "fd_delay_val_o[8]" IOSTANDARD =LVCMOS25;
NET "fd_delay_val_o[9]" LOC = Y16 ;
NET "fd_delay_val_o[9]" IOSTANDARD =LVCMOS25;
NET "fd_led_trig_o" LOC = V11 ;
NET "fd_led_trig_o" IOSTANDARD =LVCMOS25;
NET "fd_spi_cs_dac_n_o" LOC = AB16 ;
NET "fd_spi_cs_dac_n_o" IOSTANDARD =LVCMOS25;
NET "fd_spi_cs_gpio_n_o" LOC = R11 ;
NET "fd_spi_cs_gpio_n_o" IOSTANDARD =LVCMOS25;
NET "fd_spi_cs_pll_n_o" LOC = AB17 ;
NET "fd_spi_cs_pll_n_o" IOSTANDARD =LVCMOS25;
NET "fd_spi_miso_i" LOC = AB18 ;
NET "fd_spi_miso_i" IOSTANDARD =LVCMOS25;
NET "fd_spi_mosi_o" LOC = AA18 ;
NET "fd_spi_mosi_o" IOSTANDARD =LVCMOS25;
NET "fd_spi_sclk_o" LOC = Y17 ;
NET "fd_spi_sclk_o" IOSTANDARD =LVCMOS25;
NET "fd_tdc_a_o[0]" LOC = T12 ;
NET "fd_tdc_a_o[0]" IOSTANDARD =LVCMOS25;
NET "fd_tdc_a_o[1]" LOC = U12 ;
NET "fd_tdc_a_o[1]" IOSTANDARD =LVCMOS25;
NET "fd_tdc_a_o[2]" LOC = Y15 ;
NET "fd_tdc_a_o[2]" IOSTANDARD =LVCMOS25;
NET "fd_tdc_a_o[3]" LOC = AB15 ;
NET "fd_tdc_a_o[3]" IOSTANDARD =LVCMOS25;
NET "fd_tdc_alutrigger_o" LOC = W12 ;
NET "fd_tdc_alutrigger_o" IOSTANDARD =LVCMOS25;
NET "fd_tdc_cs_n_o" LOC = T11 ;
NET "fd_tdc_cs_n_o" IOSTANDARD =LVCMOS25;
NET "fd_tdc_d_b[0]" LOC = AB12 ;
NET "fd_tdc_d_b[0]" IOSTANDARD =LVCMOS25;
NET "fd_tdc_d_b[1]" LOC = U8 ;
NET "fd_tdc_d_b[1]" IOSTANDARD =LVCMOS25;
NET "fd_tdc_d_b[10]" LOC = R9 ;
NET "fd_tdc_d_b[10]" IOSTANDARD =LVCMOS25;
NET "fd_tdc_d_b[11]" LOC = R8 ;
NET "fd_tdc_d_b[11]" IOSTANDARD =LVCMOS25;
NET "fd_tdc_d_b[12]" LOC = AA6 ;
NET "fd_tdc_d_b[12]" IOSTANDARD =LVCMOS25;
NET "fd_tdc_d_b[13]" LOC = AB6 ;
NET "fd_tdc_d_b[13]" IOSTANDARD =LVCMOS25;
NET "fd_tdc_d_b[14]" LOC = U9 ;
NET "fd_tdc_d_b[14]" IOSTANDARD =LVCMOS25;
NET "fd_tdc_d_b[15]" LOC = V9 ;
NET "fd_tdc_d_b[15]" IOSTANDARD =LVCMOS25;
NET "fd_tdc_d_b[16]" LOC = Y7 ;
NET "fd_tdc_d_b[16]" IOSTANDARD =LVCMOS25;
NET "fd_tdc_d_b[17]" LOC = AB7 ;
NET "fd_tdc_d_b[17]" IOSTANDARD =LVCMOS25;
NET "fd_tdc_d_b[18]" LOC = AA8 ;
NET "fd_tdc_d_b[18]" IOSTANDARD =LVCMOS25;
NET "fd_tdc_d_b[19]" LOC = AB8 ;
NET "fd_tdc_d_b[19]" IOSTANDARD =LVCMOS25;
NET "fd_tdc_d_b[2]" LOC = AA12 ;
NET "fd_tdc_d_b[2]" IOSTANDARD =LVCMOS25;
NET "fd_tdc_d_b[20]" LOC = T10 ;
NET "fd_tdc_d_b[20]" IOSTANDARD =LVCMOS25;
NET "fd_tdc_d_b[21]" LOC = U10 ;
NET "fd_tdc_d_b[21]" IOSTANDARD =LVCMOS25;
NET "fd_tdc_d_b[22]" LOC = W10 ;
NET "fd_tdc_d_b[22]" IOSTANDARD =LVCMOS25;
NET "fd_tdc_d_b[23]" LOC = Y10 ;
NET "fd_tdc_d_b[23]" IOSTANDARD =LVCMOS25;
NET "fd_tdc_d_b[24]" LOC = Y9 ;
NET "fd_tdc_d_b[24]" IOSTANDARD =LVCMOS25;
NET "fd_tdc_d_b[25]" LOC = AB9 ;
NET "fd_tdc_d_b[25]" IOSTANDARD =LVCMOS25;
NET "fd_tdc_d_b[26]" LOC = AA4 ;
NET "fd_tdc_d_b[26]" IOSTANDARD =LVCMOS25;
NET "fd_tdc_d_b[27]" LOC = AB4 ;
NET "fd_tdc_d_b[27]" IOSTANDARD =LVCMOS25;
NET "fd_tdc_d_b[3]" LOC = T8 ;
NET "fd_tdc_d_b[3]" IOSTANDARD =LVCMOS25;
NET "fd_tdc_d_b[4]" LOC = W8 ;
NET "fd_tdc_d_b[4]" IOSTANDARD =LVCMOS25;
NET "fd_tdc_d_b[5]" LOC = V7 ;
NET "fd_tdc_d_b[5]" IOSTANDARD =LVCMOS25;
NET "fd_tdc_d_b[6]" LOC = Y6 ;
NET "fd_tdc_d_b[6]" IOSTANDARD =LVCMOS25;
NET "fd_tdc_d_b[7]" LOC = W6 ;
NET "fd_tdc_d_b[7]" IOSTANDARD =LVCMOS25;
NET "fd_tdc_d_b[8]" LOC = Y5 ;
NET "fd_tdc_d_b[8]" IOSTANDARD =LVCMOS25;
NET "fd_tdc_d_b[9]" LOC = AB5 ;
NET "fd_tdc_d_b[9]" IOSTANDARD =LVCMOS25;
NET "fd_tdc_emptyf_i" LOC = Y12 ;
NET "fd_tdc_emptyf_i" IOSTANDARD =LVCMOS25;
NET "fd_tdc_oe_n_o" LOC = AA16 ;
NET "fd_tdc_oe_n_o" IOSTANDARD =LVCMOS25;
NET "fd_tdc_rd_n_o" LOC = AB13 ;
NET "fd_tdc_rd_n_o" IOSTANDARD =LVCMOS25;
NET "fd_tdc_start_dis_o" LOC = R13 ;
NET "fd_tdc_start_dis_o" IOSTANDARD =LVCMOS25;
NET "fd_tdc_start_n_i" LOC = F16 ;
NET "fd_tdc_start_n_i" IOSTANDARD =LVDS_25;
NET "fd_tdc_start_p_i" LOC = E16 ;
NET "fd_tdc_start_p_i" IOSTANDARD =LVDS_25;
NET "fd_tdc_stop_dis_o" LOC = T14 ;
NET "fd_tdc_stop_dis_o" IOSTANDARD =LVCMOS25;
NET "fd_tdc_wr_n_o" LOC = Y13 ;
NET "fd_tdc_wr_n_o" IOSTANDARD =LVCMOS25;
NET "fd_trig_a_i" LOC = Y11 ;
NET "fd_trig_a_i" IOSTANDARD =LVCMOS25;
NET "fd_trig_cal_o" LOC = AB11 ;
NET "fd_trig_cal_o" IOSTANDARD =LVCMOS25;
NET "fmc_scl_b" LOC = F7 ;
NET "fmc_scl_b" IOSTANDARD =LVCMOS25;
NET "fmc_sda_b" LOC = F8 ;
NET "fmc_sda_b" IOSTANDARD =LVCMOS25;
#NET "onewire_b" LOC = W11 ;
#NET "onewire_b" IOSTANDARD =LVCMOS25;
NET "L_CLKp" TNM_NET = "l_clkp_grp";
NET "P2L_CLKp" TNM_NET = "p2l_clkp_grp";
NET "P2L_CLKn" TNM_NET = "p2l_clkn_grp";
TIMESPEC TS_cmp_gn4124_core_cmp_clk_in_P_clk = PERIOD "cmp_gn4124_core/cmp_clk_in/P_clk" 5 ns HIGH 50%;
# System clock
# DDR3
#---------------------------------------------------------------------------------------------
# False Path
#---------------------------------------------------------------------------------------------
# GN4124
NET "l_rst_n" TIG;
NET "cmp_gn4124_core/rst_*" TIG;
#Created by Constraints Editor (xc6slx45t-fgg484-3) - 2011/01/20
NET "cmp_gn4124_core/cmp_clk_in/P_clk" TNM_NET = cmp_gn4124_core/cmp_clk_in/P_clk;
#Created by Constraints Editor (xc6slx45t-fgg484-3) - 2011/02/04
NET "clk_125m_pllref_p_i" CLOCK_DEDICATED_ROUTE = FALSE;
#Created by Constraints Editor (xc6slx45t-fgg484-3) - 2011/09/02
NET "fd_clk_ref_n_i" TNM_NET = fd_clk_ref_n_i;
TIMESPEC TS_fd_clk_ref_n_i = PERIOD "fd_clk_ref_n_i" 8 ns HIGH 50%;
NET "fd_clk_ref_p_i" TNM_NET = fd_clk_ref_p_i;
TIMESPEC TS_fd_clk_ref_p_i = PERIOD "fd_clk_ref_p_i" 8 ns HIGH 50%;
NET "L_CLKn" TNM_NET = L_CLKn;
#>DISABLED<#TIMESPEC TS_L_CLKn = PERIOD "L_CLKn" 5 ns HIGH 50%;
NET "L_CLKp" TNM_NET = L_CLKp;
#Created by Constraints Editor (xc6slx45t-fgg484-3) - 2011/09/06
NET "clk_20m_vcxo_i" TNM_NET = clk_20m_vcxo_i;
NET "clk_sys" TNM_NET = clk_sys;
TIMESPEC TS_clk_20m_vcxo_i = PERIOD "clk_20m_vcxo_i" 50 ns HIGH 50%;
TIMESPEC ts_ignore_crossclock = FROM "clk_sys" TO "fd_clk_ref_p_i" TIG;
TIMESPEC ts_ignore_crossclock2 = FROM "fd_clk_ref_p_i" TO "clk_sys" TIG;
hdl/top/spec_1_1/spec_top.vhd 0 → 100644
View file @ e502cb54
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
use work.gn4124_core_pkg.all;
use work.wishbone_pkg.all;
library UNISIM;
use UNISIM.vcomponents.all;
entity spec_top is
generic
(
TAR_ADDR_WDTH : integer := 13 -- not used for this project
);
port
(
-- Global ports
clk_20m_vcxo_i : in std_logic; -- 20MHz VCXO clock
clk_125m_pllref_p_i : in std_logic; -- 125 MHz PLL reference
clk_125m_pllref_n_i : in std_logic;
-- From GN4124 Local bus
L_CLKp : in std_logic; -- Local bus clock (frequency set in GN4124 config registers)
L_CLKn : in std_logic; -- Local bus clock (frequency set in GN4124 config registers)
L_RST_N : in std_logic; -- Reset from GN4124 (RSTOUT18_N)
-- General Purpose Interface
GPIO : inout std_logic_vector(1 downto 0); -- GPIO[0] -> GN4124 GPIO8
-- GPIO[1] -> GN4124 GPIO9
-- PCIe to Local [Inbound Data] - RX
P2L_RDY : out std_logic; -- Rx Buffer Full Flag
P2L_CLKn : in std_logic; -- Receiver Source Synchronous Clock-
P2L_CLKp : in std_logic; -- Receiver Source Synchronous Clock+
P2L_DATA : in std_logic_vector(15 downto 0); -- Parallel receive data
P2L_DFRAME : in std_logic; -- Receive Frame
P2L_VALID : in std_logic; -- Receive Data Valid
-- Inbound Buffer Request/Status
P_WR_REQ : in std_logic_vector(1 downto 0); -- PCIe Write Request
P_WR_RDY : out std_logic_vector(1 downto 0); -- PCIe Write Ready
RX_ERROR : out std_logic; -- Receive Error
-- Local to Parallel [Outbound Data] - TX
L2P_DATA : out std_logic_vector(15 downto 0); -- Parallel transmit data
L2P_DFRAME : out std_logic; -- Transmit Data Frame
L2P_VALID : out std_logic; -- Transmit Data Valid
L2P_CLKn : out std_logic; -- Transmitter Source Synchronous Clock-
L2P_CLKp : out std_logic; -- Transmitter Source Synchronous Clock+
L2P_EDB : out std_logic; -- Packet termination and discard
-- Outbound Buffer Status
L2P_RDY : in std_logic; -- Tx Buffer Full Flag
L_WR_RDY : in std_logic_vector(1 downto 0); -- Local-to-PCIe Write
P_RD_D_RDY : in std_logic_vector(1 downto 0); -- PCIe-to-Local Read Response Data Ready
TX_ERROR : in std_logic; -- Transmit Error
VC_RDY : in std_logic_vector(1 downto 0); -- Channel ready
-- Font panel LEDs
LED_RED : out std_logic;
LED_GREEN : out std_logic;
fd_tdc_start_p_i : in std_logic;
fd_tdc_start_n_i : in std_logic;
fd_clk_ref_p_i : in std_logic;
fd_clk_ref_n_i : in std_logic;
fd_trig_a_i : in std_logic;
fd_trig_cal_o : out std_logic;
fd_tdc_d_b : inout std_logic_vector(27 downto 0);
fd_tdc_a_o : out std_logic_vector(3 downto 0);
fd_tdc_emptyf_i : in std_logic;
fd_tdc_alutrigger_o : out std_logic;
fd_tdc_cs_n_o : out std_logic;
fd_tdc_wr_n_o : out std_logic;
fd_tdc_rd_n_o : out std_logic;
fd_tdc_oe_n_o : out std_logic;
fd_led_trig_o : out std_logic;
fd_tdc_start_dis_o : out std_logic;
fd_tdc_stop_dis_o : out std_logic;
fd_spi_cs_dac_n_o : out std_logic;
fd_spi_cs_pll_n_o : out std_logic;
fd_spi_cs_gpio_n_o : out std_logic;
fd_spi_sclk_o : out std_logic;
fd_spi_mosi_o : out std_logic;
fd_spi_miso_i : in std_logic;
fd_delay_len_o : out std_logic_vector(3 downto 0);
fd_delay_val_o : out std_logic_vector(9 downto 0);
fd_delay_pulse_o : out std_logic_vector(3 downto 0);
fmc_scl_b : inout std_logic;
fmc_sda_b : inout std_logic;
onewire_b : inout std_logic
);
end spec_top;
architecture rtl of spec_top is
component spec_gbit_tester
port (
clk_ref_gtp0_i : in std_logic;
clk_ref_gtp1_i : in std_logic;
clk_sys_i : in std_logic;
rst_n_i : in std_logic;
sfp_txp_o : out std_logic;
sfp_txn_o : out std_logic;
sfp_rxp_i : in std_logic;
sfp_rxn_i : in std_logic;
sata1_txp_o : out std_logic;
sata1_txn_o : out std_logic;
sata1_rxp_i : in std_logic;
sata1_rxn_i : in std_logic;
sata2_txp_o : out std_logic;
sata2_txn_o : out std_logic;
sata2_rxp_i : in std_logic;
sata2_rxn_i : in std_logic;
fmc_txp_o : out std_logic;
fmc_txn_o : out std_logic;
fmc_rxp_i : in std_logic;
fmc_rxn_i : in std_logic;
fmc_gbtclk_i : in std_logic;
wb_addr_i : in std_logic_vector(2 downto 0);
wb_data_i : in std_logic_vector(31 downto 0);
wb_data_o : out std_logic_vector(31 downto 0);
wb_cyc_i : in std_logic;
wb_sel_i : in std_logic_vector(3 downto 0);
wb_stb_i : in std_logic;
wb_we_i : in std_logic;
wb_ack_o : out std_logic);
end component;
component gn4124_core
generic(
-- g_IS_SPARTAN6 : boolean := false; -- This generic is used to instanciate spartan6 specific primitives
g_BAR0_APERTURE : integer := 20; -- BAR0 aperture, defined in GN4124 PCI_BAR_CONFIG register (0x80C)
-- => number of bits to address periph on the board
g_CSR_WB_SLAVES_NB : integer := 1; -- Number of CSR wishbone slaves
g_DMA_WB_SLAVES_NB : integer := 1; -- Number of DMA wishbone slaves
g_DMA_WB_ADDR_WIDTH : integer := 26; -- DMA wishbone address bus width;
g_CSR_WB_MODE : string := "classic"
);
port
(
---------------------------------------------------------
-- Control and status
--
-- Asynchronous reset from GN4124
rst_n_a_i : in std_logic;
-- P2L clock PLL locked
p2l_pll_locked : out std_logic;
-- Debug ouputs
debug_o : out std_logic_vector(7 downto 0);
---------------------------------------------------------
-- P2L Direction
--
-- Source Sync DDR related signals
p2l_clk_p_i : in std_logic; -- Receiver Source Synchronous Clock+
p2l_clk_n_i : in std_logic; -- Receiver Source Synchronous Clock-
p2l_data_i : in std_logic_vector(15 downto 0); -- Parallel receive data
p2l_dframe_i : in std_logic; -- Receive Frame
p2l_valid_i : in std_logic; -- Receive Data Valid
-- P2L Control
p2l_rdy_o : out std_logic; -- Rx Buffer Full Flag
p_wr_req_i : in std_logic_vector(1 downto 0); -- PCIe Write Request
p_wr_rdy_o : out std_logic_vector(1 downto 0); -- PCIe Write Ready
rx_error_o : out std_logic; -- Receive Error
---------------------------------------------------------
-- L2P Direction
--
-- Source Sync DDR related signals
l2p_clk_p_o : out std_logic; -- Transmitter Source Synchronous Clock+
l2p_clk_n_o : out std_logic; -- Transmitter Source Synchronous Clock-
l2p_data_o : out std_logic_vector(15 downto 0); -- Parallel transmit data
l2p_dframe_o : out std_logic; -- Transmit Data Frame
l2p_valid_o : out std_logic; -- Transmit Data Valid
l2p_edb_o : out std_logic; -- Packet termination and discard
-- L2P Control
l2p_rdy_i : in std_logic; -- Tx Buffer Full Flag
l_wr_rdy_i : in std_logic_vector(1 downto 0); -- Local-to-PCIe Write
p_rd_d_rdy_i : in std_logic_vector(1 downto 0); -- PCIe-to-Local Read Response Data Ready
tx_error_i : in std_logic; -- Transmit Error
vc_rdy_i : in std_logic_vector(1 downto 0); -- Channel ready
---------------------------------------------------------
-- Interrupt interface
dma_irq_o : out std_logic_vector(1 downto 0); -- Interrupts sources to IRQ manager
irq_p_i : in std_logic; -- Interrupt request pulse from IRQ manager
irq_p_o : out std_logic; -- Interrupt request pulse to GN4124 GPIO
---------------------------------------------------------
-- Target interface (CSR wishbone master)
wb_clk_i : in std_logic;
wb_adr_o : out std_logic_vector(g_BAR0_APERTURE-priv_log2_ceil(g_CSR_WB_SLAVES_NB+1)-1 downto 0);
wb_dat_o : out std_logic_vector(31 downto 0); -- Data out
wb_sel_o : out std_logic_vector(3 downto 0); -- Byte select
wb_stb_o : out std_logic;
wb_we_o : out std_logic;
wb_cyc_o : out std_logic_vector(g_CSR_WB_SLAVES_NB-1 downto 0);
wb_dat_i : in std_logic_vector((32*g_CSR_WB_SLAVES_NB)-1 downto 0); -- Data in
wb_ack_i : in std_logic_vector(g_CSR_WB_SLAVES_NB-1 downto 0);
---------------------------------------------------------
-- DMA interface (Pipelined wishbone master)
dma_clk_i : in std_logic;
dma_adr_o : out std_logic_vector(31 downto 0);
dma_dat_o : out std_logic_vector(31 downto 0); -- Data out
dma_sel_o : out std_logic_vector(3 downto 0); -- Byte select
dma_stb_o : out std_logic;
dma_we_o : out std_logic;
dma_cyc_o : out std_logic; --_vector(g_DMA_WB_SLAVES_NB-1 downto 0);
dma_dat_i : in std_logic_vector((32*g_DMA_WB_SLAVES_NB)-1 downto 0); -- Data in
dma_ack_i : in std_logic; --_vector(g_DMA_WB_SLAVES_NB-1 downto 0);
dma_stall_i : in std_logic--_vector(g_DMA_WB_SLAVES_NB-1 downto 0) -- for pipelined Wishbone
);
end component; -- gn4124_core
------------------------------------------------------------------------------
-- Constants declaration
------------------------------------------------------------------------------
constant c_BAR0_APERTURE : integer := 20;
constant c_CSR_WB_SLAVES_NB : integer := 1;
constant c_DMA_WB_SLAVES_NB : integer := 1;
constant c_DMA_WB_ADDR_WIDTH : integer := 26;
------------------------------------------------------------------------------
-- Signals declaration
------------------------------------------------------------------------------
-- LCLK from GN4124 used as system clock
signal l_clk : std_logic;
-- P2L colck PLL status
signal p2l_pll_locked : std_logic;
-- Reset
signal rst_a : std_logic;
signal rst : std_logic;
-- CSR wishbone bus
signal wb_adr : std_logic_vector(c_BAR0_APERTURE-priv_log2_ceil(c_CSR_WB_SLAVES_NB+1)-1 downto 0);
signal wb_dat_i : std_logic_vector((32*c_CSR_WB_SLAVES_NB)-1 downto 0);
signal wb_dat_o : std_logic_vector(31 downto 0);
signal wb_sel : std_logic_vector(3 downto 0);
signal wb_cyc : std_logic_vector(c_CSR_WB_SLAVES_NB-1 downto 0);
signal wb_stb : std_logic;
signal wb_we : std_logic;
signal wb_ack : std_logic_vector(c_CSR_WB_SLAVES_NB-1 downto 0);
signal spi_wb_adr : std_logic_vector(4 downto 0);
-- DMA wishbone bus
signal dma_adr : std_logic_vector(31 downto 0);
signal dma_dat_i : std_logic_vector((32*c_DMA_WB_SLAVES_NB)-1 downto 0);
signal dma_dat_o : std_logic_vector(31 downto 0);
signal dma_sel : std_logic_vector(3 downto 0);
signal dma_cyc : std_logic; --_vector(c_DMA_WB_SLAVES_NB-1 downto 0);
signal dma_stb : std_logic;
signal dma_we : std_logic;
signal dma_ack : std_logic; --_vector(c_DMA_WB_SLAVES_NB-1 downto 0);
signal dma_stall : std_logic; --_vector(c_DMA_WB_SLAVES_NB-1 downto 0);
signal ram_we : std_logic_vector(0 downto 0);
signal ddr_dma_adr : std_logic_vector(29 downto 0);
signal irq_to_gn4124 : std_logic;
-- SPI
signal spi_slave_select : std_logic_vector(7 downto 0);
signal pllout_clk_sys : std_logic;
signal pllout_clk_dmtd : std_logic;
signal pllout_clk_fb_pllref : std_logic;
signal pllout_clk_fb_dmtd : std_logic;
signal clk_20m_vcxo_buf : std_logic;
signal clk_125m_pllref : std_logic;
signal clk_125m_gtp0 : std_logic;
signal clk_125m_gtp1 : std_logic;
signal clk_sys : std_logic;
signal clk_dmtd : std_logic;
signal led_divider : unsigned(23 downto 0);
signal scl_pad_out : std_logic;
signal scl_pad_in : std_logic;
signal scl_pad_oen : std_logic;
signal sda_pad_out : std_logic;
signal sda_pad_in : std_logic;
signal sda_pad_oen : std_logic;
signal tdc_data_out, tdc_data_in : std_logic_vector(27 downto 0);
signal tdc_data_oe : std_logic;
constant c_NUM_WISHBONE_DEVS : integer := 3;
signal cnx_slave_in : t_wishbone_slave_in;
signal cnx_slave_out : t_wishbone_slave_out;
signal cnx_out : t_wishbone_master_out_array (0 to c_NUM_WISHBONE_DEVS-1);
signal cnx_in : t_wishbone_master_in_array (0 to c_NUM_WISHBONE_DEVS-1);
signal fd_clk_ref : std_logic;
signal fd_tdc_start : std_logic;
signal onewire_en : std_logic;
component fine_delay_core
port (
clk_ref_i : in std_logic;
clk_sys_i : in std_logic;
rst_n_i : in std_logic;
trig_a_n_i : in std_logic;
trig_cal_o : out std_logic;
tdc_start_i : in std_logic;
acam_a_o : out std_logic_vector(3 downto 0);
acam_d_o : out std_logic_vector(27 downto 0);
acam_d_i : in std_logic_vector(27 downto 0);
acam_d_oen_o : out std_logic;
acam_err_i : in std_logic;
acam_int_i : in std_logic;
acam_emptyf_i : in std_logic;
acam_alutrigger_o : out std_logic;
acam_cs_n_o : out std_logic;
acam_wr_n_o : out std_logic;
acam_rd_n_o : out std_logic;
acam_start_dis_o : out std_logic;
acam_stop_dis_o : out std_logic;
led_trig_o : out std_logic;
spi_cs_dac_n_o : out std_logic;
spi_cs_pll_n_o : out std_logic;
spi_cs_gpio_n_o : out std_logic;
spi_sclk_o : out std_logic;
spi_mosi_o : out std_logic;
spi_miso_i : in std_logic;
delay_len_o : out std_logic_vector(3 downto 0);
delay_val_o : out std_logic_vector(9 downto 0);
delay_pulse_o : out std_logic_vector(3 downto 0);
owr_en_o : out std_logic;
owr_i : in std_logic;
wr_time_valid_i : in std_logic;
wr_coarse_i : in std_logic_vector(27 downto 0);
wr_utc_i : in std_logic_vector(31 downto 0);
wb_adr_i : in std_logic_vector(7 downto 0);
wb_dat_i : in std_logic_vector(31 downto 0);
wb_dat_o : out std_logic_vector(31 downto 0);
wb_cyc_i : in std_logic;
wb_stb_i : in std_logic;
wb_we_i : in std_logic;
wb_ack_o : out std_logic;
wb_irq_o : out std_logic);
end component;
signal rst_n : std_logic;
signal powerup_rst_counter : std_logic_vector(10 downto 0) := "00000000000";
begin
process(clk_sys)
begin
if rising_edge(clk_sys) then
powerup_rst_counter <= '1' & powerup_rst_counter(10 downto 1);
end if;
end process;
rst_n <= powerup_rst_counter(0);
--cmp_sys_clk_pll : PLL_BASE
-- generic map (
-- BANDWIDTH => "OPTIMIZED",
-- CLK_FEEDBACK => "CLKFBOUT",
-- COMPENSATION => "INTERNAL",
-- DIVCLK_DIVIDE => 1,
-- CLKFBOUT_MULT => 8,
-- CLKFBOUT_PHASE => 0.000,
-- CLKOUT0_DIVIDE => 16, -- 62.5 MHz
-- CLKOUT0_PHASE => 0.000,
-- CLKOUT0_DUTY_CYCLE => 0.500,
-- CLKOUT1_DIVIDE => 16, -- 125 MHz
-- CLKOUT1_PHASE => 0.000,
-- CLKOUT1_DUTY_CYCLE => 0.500,
-- CLKOUT2_DIVIDE => 16,
-- CLKOUT2_PHASE => 0.000,
-- CLKOUT2_DUTY_CYCLE => 0.500,
-- CLKIN_PERIOD => 8.0,
-- REF_JITTER => 0.016)
-- port map (
-- CLKFBOUT => pllout_clk_fb_pllref,
-- CLKOUT0 => pllout_clk_sys,
-- CLKOUT1 => open,
-- CLKOUT2 => open,
-- CLKOUT3 => open,
-- CLKOUT4 => open,
-- CLKOUT5 => open,
-- LOCKED => open,
-- RST => '0',
-- CLKFBIN => pllout_clk_fb_pllref,
-- CLKIN => clk_125m_pllref);
cmp_dmtd_clk_pll : PLL_BASE
generic map (
BANDWIDTH => "OPTIMIZED",
CLK_FEEDBACK => "CLKFBOUT",
COMPENSATION => "INTERNAL",
DIVCLK_DIVIDE => 1,
CLKFBOUT_MULT => 50,
CLKFBOUT_PHASE => 0.000,
CLKOUT0_DIVIDE => 8, -- 62.5 MHz
CLKOUT0_PHASE => 0.000,
CLKOUT0_DUTY_CYCLE => 0.500,
CLKOUT1_DIVIDE => 16, -- 125 MHz
CLKOUT1_PHASE => 0.000,
CLKOUT1_DUTY_CYCLE => 0.500,
CLKOUT2_DIVIDE => 8,
CLKOUT2_PHASE => 0.000,
CLKOUT2_DUTY_CYCLE => 0.500,
CLKIN_PERIOD => 50.0,
REF_JITTER => 0.016)
port map (
CLKFBOUT => pllout_clk_fb_dmtd,
CLKOUT0 => pllout_clk_dmtd,
CLKOUT1 => pllout_clk_sys,
CLKOUT2 => open,
CLKOUT3 => open,
CLKOUT4 => open,
CLKOUT5 => open,
LOCKED => open,
RST => '0',
CLKFBIN => pllout_clk_fb_dmtd,
CLKIN => clk_20m_vcxo_i);
cmp_clk_sys_buf : BUFG
port map (
O => clk_sys,
I => pllout_clk_sys);
cmp_clk_dmtd_buf : BUFG
port map (
O => clk_dmtd,
I => pllout_clk_dmtd);
--cmp_clk_vcxo : BUFG
-- port map (
-- O => clk_20m_vcxo_buf,
-- I => clk_20m_vcxo_i);
------------------------------------------------------------------------------
-- Local clock from gennum LCLK
------------------------------------------------------------------------------
cmp_l_clk_buf : IBUFDS
generic map (
DIFF_TERM => false, -- Differential Termination
IBUF_LOW_PWR => true, -- Low power (TRUE) vs. performance (FALSE) setting for referenced I/O standards
IOSTANDARD => "DEFAULT")
port map (
O => l_clk, -- Buffer output
I => L_CLKp, -- Diff_p buffer input (connect directly to top-level port)
IB => L_CLKn -- Diff_n buffer input (connect directly to top-level port)
);
------------------------------------------------------------------------------
-- Active high reset
------------------------------------------------------------------------------
rst <= not(L_RST_N);
------------------------------------------------------------------------------
-- GN4124 interface
------------------------------------------------------------------------------
cmp_gn4124_core : gn4124_core
generic map (
-- g_IS_SPARTAN6 => true,
g_BAR0_APERTURE => c_BAR0_APERTURE,
g_CSR_WB_SLAVES_NB => c_CSR_WB_SLAVES_NB,
g_DMA_WB_SLAVES_NB => c_DMA_WB_SLAVES_NB,
g_DMA_WB_ADDR_WIDTH => c_DMA_WB_ADDR_WIDTH,
g_CSR_WB_MODE => "classic"
)
port map
(
---------------------------------------------------------
-- Control and status
--
-- Asynchronous reset from GN4124
rst_n_a_i => L_RST_N,
-- P2L clock PLL locked
p2l_pll_locked => p2l_pll_locked,
-- Debug outputs
debug_o => open,
---------------------------------------------------------
-- P2L Direction
--
-- Source Sync DDR related signals
p2l_clk_p_i => P2L_CLKp,
p2l_clk_n_i => P2L_CLKn,
p2l_data_i => P2L_DATA,
p2l_dframe_i => P2L_DFRAME,
p2l_valid_i => P2L_VALID,
-- P2L Control
p2l_rdy_o => P2L_RDY,
p_wr_req_i => P_WR_REQ,
p_wr_rdy_o => P_WR_RDY,
rx_error_o => RX_ERROR,
---------------------------------------------------------
-- L2P Direction
--
-- Source Sync DDR related signals
l2p_clk_p_o => L2P_CLKp,
l2p_clk_n_o => L2P_CLKn,
l2p_data_o => L2P_DATA,
l2p_dframe_o => L2P_DFRAME,
l2p_valid_o => L2P_VALID,
l2p_edb_o => L2P_EDB,
-- L2P Control
l2p_rdy_i => L2P_RDY,
l_wr_rdy_i => L_WR_RDY,
p_rd_d_rdy_i => P_RD_D_RDY,
tx_error_i => TX_ERROR,
vc_rdy_i => VC_RDY,
---------------------------------------------------------
-- Interrupt interface
dma_irq_o => open,
irq_p_i => '0',
irq_p_o => GPIO(0),
---------------------------------------------------------
-- Target Interface (Wishbone master)
wb_clk_i => clk_sys,
wb_adr_o => cnx_slave_in.adr(18 downto 0),
wb_dat_o => cnx_slave_in.dat,
wb_sel_o => cnx_slave_in.sel,
wb_stb_o => cnx_slave_in.stb,
wb_we_o => cnx_slave_in.we,
wb_cyc_o(0) => cnx_slave_in.cyc,
wb_dat_i => cnx_slave_out.dat,
wb_ack_i(0) => cnx_slave_out.ack,
---------------------------------------------------------
-- L2P DMA Interface (Pipelined Wishbone master)
dma_clk_i => clk_sys,
dma_adr_o => dma_adr,
dma_dat_o => dma_dat_o,
dma_sel_o => dma_sel,
dma_stb_o => dma_stb,
dma_we_o => dma_we,
dma_cyc_o => dma_cyc,
dma_dat_i => dma_dat_i,
dma_ack_i => dma_ack,
dma_stall_i => dma_stall
);
process(clk_sys, rst)
begin
if rising_edge(clk_sys) then
if(rst_n = '0') then
led_divider <= (others => '0');
else
led_divider <= led_divider + 1;
LED_RED <= std_logic(led_divider(led_divider'high));
LED_GREEN <= std_logic(led_divider(led_divider'high));
end if;
end if;
end process;
--fd_tdc_oe_n_o <= '1';
cmp_fd_refclk : IBUFGDS
generic map (
DIFF_TERM => true, -- Differential Termination
IBUF_LOW_PWR => false, -- Low power (TRUE) vs. performance (FALSE) setting for referenced I/O standards
IOSTANDARD => "LVDS_25")
port map (
O => fd_clk_ref, -- Buffer output
I => fd_clk_ref_p_i, -- Diff_p buffer input (connect directly to top-level port)
IB => fd_clk_ref_n_i -- Diff_n buffer input (connect directly to top-level port)
);
cmp_fd_tdc_start : IBUFDS
generic map (
DIFF_TERM => true,
IBUF_LOW_PWR => false -- Low power (TRUE) vs. performance (FALSE) setting for referenced
)
port map (
O => fd_tdc_start, -- Buffer output
I => fd_tdc_start_p_i, -- Diff_p buffer input (connect directly to top-level port)
IB => fd_tdc_start_n_i -- Diff_n buffer input (connect directly to top-level port)
);
U_Fanout : xwb_bus_fanout
generic map (
g_num_outputs => c_NUM_WISHBONE_DEVS,
g_bits_per_slave => 8)
port map (
clk_sys_i => clk_sys,
rst_n_i => rst_n,
slave_i => cnx_slave_in,
slave_o => cnx_slave_out,
master_i => cnx_in,
master_o => cnx_out);
cnx_in(2).int <= '0';
cnx_in(2).ack <= '0';
cnx_in(2).rty <= '0';
cnx_in(2).err <= '0';
U_I2C : xwb_i2c_master
generic map (
g_interface_mode => CLASSIC)
port map (
clk_sys_i => clk_sys,
rst_n_i => rst_n,
slave_i => cnx_out(0),
slave_o => cnx_in(0),
desc_o => open,
scl_pad_i => scl_pad_in,
scl_pad_o => scl_pad_out,
scl_padoen_o => scl_pad_oen,
sda_pad_i => sda_pad_in,
sda_pad_o => sda_pad_out,
sda_padoen_o => sda_pad_oen);
fmc_scl_b <= scl_pad_out when scl_pad_oen = '0' else 'Z';
fmc_sda_b <= sda_pad_out when sda_pad_oen = '0' else 'Z';
scl_pad_in <= fmc_scl_b;
sda_pad_in <= fmc_sda_b;
U_DELAY_CORE : fine_delay_core
port map (
clk_ref_i => fd_clk_ref,
tdc_start_i => fd_tdc_start,
clk_sys_i => clk_sys,
rst_n_i => RST_N,
trig_a_n_i => fd_trig_a_i,
trig_cal_o => fd_trig_cal_o,
led_trig_o => fd_led_trig_o,
acam_a_o => fd_tdc_a_o,
acam_d_o => tdc_data_out,
acam_d_i => tdc_data_in,
acam_d_oen_o => tdc_data_oe,
acam_err_i => '0',
acam_int_i => '0',
acam_emptyf_i => fd_tdc_emptyf_i,
acam_alutrigger_o => fd_tdc_alutrigger_o,
acam_cs_n_o => fd_tdc_cs_n_o,
acam_wr_n_o => fd_tdc_wr_n_o,
acam_rd_n_o => fd_tdc_rd_n_o,
acam_start_dis_o => fd_tdc_start_dis_o,
acam_stop_dis_o => fd_tdc_stop_dis_o,
wr_time_valid_i => '0',
wr_utc_i => x"00000000",
wr_coarse_i => x"0000000",
spi_cs_dac_n_o => fd_spi_cs_dac_n_o,
spi_cs_pll_n_o => fd_spi_cs_pll_n_o,
spi_cs_gpio_n_o => fd_spi_cs_gpio_n_o,
spi_sclk_o => fd_spi_sclk_o,
spi_mosi_o => fd_spi_mosi_o,
spi_miso_i => fd_spi_miso_i,
delay_len_o => fd_delay_len_o,
delay_val_o => fd_delay_val_o,
delay_pulse_o => fd_delay_pulse_o,
owr_i => onewire_b,
owr_en_o => onewire_en,
wb_adr_i => cnx_out(1).adr(7 downto 0),
wb_dat_i => cnx_out(1).dat,
wb_dat_o => cnx_in(1).dat,
wb_cyc_i => cnx_out(1).cyc,
wb_stb_i => cnx_out(1).stb,
wb_we_i => cnx_out(1).we,
wb_ack_o => cnx_in(1).ack);
-- tristate buffer for the TDC data bus:
fd_tdc_d_b <= tdc_data_out when tdc_data_oe = '1' else (others => 'Z');
fd_tdc_oe_n_o <= '1';
tdc_data_in <= fd_tdc_d_b;
onewire_b <= '0' when onewire_en = '0' else 'Z';
end rtl;
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