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FMC DEL 1ns 4cha
Commits
dddcbe14
Commit
dddcbe14
authored
Apr 16, 2013
by
Tomasz Wlostowski
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Plain Diff
hdl/top/svec: removed VME core reset output
parent
42bbc5ec
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1 changed file
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25 additions
and
30 deletions
+25
-30
xvme64x_core.vhd
hdl/top/svec/wr/xvme64x_core.vhd
+25
-30
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hdl/top/svec/wr/xvme64x_core.vhd
View file @
dddcbe14
...
...
@@ -9,8 +9,6 @@ entity xvme64x_core is
clk_i
:
in
std_logic
;
rst_n_i
:
in
std_logic
;
rst_n_o
:
out
std_logic
;
VME_AS_n_i
:
in
std_logic
;
VME_RST_n_i
:
in
std_logic
;
VME_WRITE_n_i
:
in
std_logic
;
...
...
@@ -51,12 +49,12 @@ architecture wrapper of xvme64x_core is
component
VME64xCore_Top
generic
(
g_wb_data_width
:
integer
:
=
32
;
g_wb_data_width
:
integer
:
=
32
;
g_wb_addr_width
:
integer
:
=
64
;
g_CRAM_SIZE
:
integer
:
=
1024
);
g_CRAM_SIZE
:
integer
:
=
1024
);
port
(
clk_i
:
in
std_logic
;
r
eset_o
:
out
std_logic
;
r
st_n_i
:
in
std_logic
;
VME_AS_n_i
:
in
std_logic
;
VME_RST_n_i
:
in
std_logic
;
VME_WRITE_n_i
:
in
std_logic
;
...
...
@@ -98,19 +96,16 @@ architecture wrapper of xvme64x_core is
debug
:
out
std_logic_vector
(
7
downto
0
));
end
component
;
signal
rst_in
,
rst_out
:
std_logic
;
signal
rst_in
,
rst_out
:
std_logic
;
signal
dat_out
,
dat_in
:
std_logic_vector
(
31
downto
0
);
signal
adr_out
:
std_logic_vector
(
63
downto
0
);
signal
adr_out
:
std_logic_vector
(
63
downto
0
);
begin
-- wrapper
rst_in
<=
not
rst_n_i
;
rst_n_o
<=
rst_n_i
and
(
not
rst_out
);
U_Wrapped_VME
:
VME64xCore_Top
port
map
(
clk_i
=>
clk_i
,
r
eset_o
=>
rst_out
,
r
st_n_i
=>
rst_n_i
,
VME_AS_n_i
=>
VME_AS_n_i
,
VME_RST_n_i
=>
VME_RST_n_i
,
VME_WRITE_n_i
=>
VME_WRITE_n_i
,
...
...
@@ -121,13 +116,13 @@ begin -- wrapper
VME_DTACK_n_o
=>
VME_DTACK_n_o
,
VME_RETRY_n_o
=>
VME_RETRY_n_o
,
VME_RETRY_OE_o
=>
VME_RETRY_OE_o
,
VME_LWORD_n_i
=>
VME_LWORD_n_b_i
,
VME_LWORD_n_o
=>
VME_LWORD_n_b_o
,
VME_ADDR_i
=>
VME_ADDR_b_i
,
VME_ADDR_o
=>
VME_ADDR_b_o
,
VME_DATA_i
=>
VME_DATA_b_i
,
VME_DATA_o
=>
VME_DATA_b_o
,
VME_IRQ_o
=>
VME_IRQ_n_o
,
VME_LWORD_n_i
=>
VME_LWORD_n_b_i
,
VME_LWORD_n_o
=>
VME_LWORD_n_b_o
,
VME_ADDR_i
=>
VME_ADDR_b_i
,
VME_ADDR_o
=>
VME_ADDR_b_o
,
VME_DATA_i
=>
VME_DATA_b_i
,
VME_DATA_o
=>
VME_DATA_b_o
,
VME_IRQ_o
=>
VME_IRQ_n_o
,
VME_IACKIN_n_i
=>
VME_IACKIN_n_i
,
VME_IACK_n_i
=>
VME_IACK_n_i
,
VME_IACKOUT_n_o
=>
VME_IACKOUT_n_o
,
...
...
@@ -137,18 +132,18 @@ begin -- wrapper
VME_ADDR_DIR_o
=>
VME_ADDR_DIR_o
,
VME_ADDR_OE_N_o
=>
VME_ADDR_OE_N_o
,
DAT_i
=>
dat_in
,
DAT_o
=>
dat_out
,
ADR_o
=>
adr_out
,
CYC_o
=>
master_o
.
cyc
,
ERR_i
=>
master_i
.
err
,
RTY_i
=>
master_i
.
rty
,
SEL_o
=>
open
,
STB_o
=>
master_o
.
stb
,
ACK_i
=>
master_i
.
ack
,
WE_o
=>
master_o
.
we
,
STALL_i
=>
master_i
.
stall
,
IRQ_i
=>
irq_i
,
DAT_i
=>
dat_in
,
DAT_o
=>
dat_out
,
ADR_o
=>
adr_out
,
CYC_o
=>
master_o
.
cyc
,
ERR_i
=>
master_i
.
err
,
RTY_i
=>
master_i
.
rty
,
SEL_o
=>
open
,
STB_o
=>
master_o
.
stb
,
ACK_i
=>
master_i
.
ack
,
WE_o
=>
master_o
.
we
,
STALL_i
=>
master_i
.
stall
,
IRQ_i
=>
irq_i
,
INT_ack_o
=>
irq_ack_o
);
...
...
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