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FMC DEL 1ns 4cha
Commit d7d5c816 authored by Tomasz Wlostowski's avatar Tomasz Wlostowski
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Backup_*.cdr
\#*\#
*.texi
*.wb
*.aux
*.info
*.ky
*.log
*.toc
*.cp
*.fn
*.in~
*.pdf
*.pg
*.tp
*.txt
*.vr
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#
# Makefile for the documentation directory
#
# Copyright 1994,2000,2010,2011 Alessandro Rubini <rubini@linux.it>
#
#################
# There is not basenames here, all *.in are considered input
INPUT = $(wildcard *.in)
TEXI = $(INPUT:.in=.texi)
INFO = $(INPUT:.in=.info)
HTML = $(INPUT:.in=.html)
TXT = $(INPUT:.in=.txt)
PDF = $(INPUT:.in=.pdf)
ALL = $(PDF)
MAKEINFO ?= makeinfo
%.texi: %.in
@rm -f $@
sed -f ./infofilter $< > $@
emacs -batch --no-site-file -l fixinfo $@
chmod -w $@
%.pdf: %.texi
texi2pdf --batch $<
#%.info: %.texi
# $(MAKEINFO) $< -o $@
#%.html: %.texi
# $(MAKEINFO) --html --no-split -o $@ $<
#%.txt: %.texi
# $(MAKEINFO) --no-headers $< > $@
##############################################
.PHONY: all images check terse clean install
.INTERMEDIATE: $(TEXI)
all: images $(ALL)
$(MAKE) terse
images::
if [ -d images ]; then $(MAKE) -C images || exit 1; fi
check: _err.ps
gs -sDEVICE=linux -r320x200x16 $<
terse:
for n in cp fn ky pg toc tp vr aux log; do rm -f *.$$n; done
rm -f *~
clean: terse
rm -f $(ALL) $(TEXI)
install:
doc/design-notes/fine-delay.in
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......@@ -182,12 +182,12 @@ The FD's TDC is a single-chip solution, called TDC-GPX made by Acam (IC8). It ca
timestamp from 1 to 8 inputs, with accuracy and repetition rate depending on the mode of
operation (R, I, M, G-modes, more details in the @cite{TDC-GPX datasheet}). In the FD, the ACAM serves two purposes:
@itemize
@item The obvious one: @b{time tagging trigger pulses}. The TDC in configured in the R-mode, with a single
stop input, providing 10 Mpulses/second throughput, measurement range of 40 us and resolution (one-sigma)
of 27 ps. In this mode, LVPECL inputs are used, the Start being connected to the 7.125 MHz PLL
clock, and the Stop feeding in trigger pulses. As a result, we get the time difference between
the rising edge of the most recent start pulse and the stop pulse - for a 7.125 MHz start signal
frequency, it gives a measurement range of 0 to 128 ns. The coarse part of the timestamp is
@item The obvious one: @b{time tagging trigger pulses}. The TDC in configured in the G-mode, with a single
stop input, providing 7 Mpulses/second throughput, measurement range of 40 us and resolution (one-sigma)
of 42 ps. In this mode, LVPECL inputs are used, the Start being connected to the 7.125 MHz PLL
clock (divided internally by 2), and the Stop feeding in trigger pulses. As a result, we get the time difference between
the rising edge of the most recent start pulse and the stop pulse - for a (7.125 / 2) MHz start event
frequency, it gives a measurement range of 0 to 256 ns. The coarse part of the timestamp is
produced with a counter inside the FPGA and the two values are merged together to obtain the
final, accurate value (see @ref{Timestamp processing}).
......@@ -354,7 +354,7 @@ Timing-wise, the FD can work in one of these two modes:
@itemize
@item @b{local time base} mode, where @code{clk_ref_0} oscillator is free running and the time counters
are coarsely initialized by the host through the @code{TM_SECH}, @code{TM_SECL}, @code{TM_COARSE} and @code{TCR} registers.
In this mode, the TDC input/output events cannot be related to other cores/devices,
In this mode, the TDC input/output events cannot be accurately related to other cores/devices,
and the delay accuracy is as good as of the local oscillator (±2.5 ppm),
which means worst case error of 2.5 ns for a delay setting of 1 ms).
@item @b{White Rabbit time base} mode, in which the reference clock is phase-locked to the WR master clock (by means of the SoftPLL
......@@ -369,7 +369,7 @@ For your convenience, the diagram on @ref{fig:wr_pll} shows the interaction betw
@caption{Operation of the FD core with White Rabbit as a time source.}
@end float
Mode selection is controlled by the @code{TCR} register and the @code{p_whiterabbit_fsm} state machin,
Mode selection is controlled by the @code{TCR} register and the @code{p_whiterabbit_fsm} state machine,
which also provides the status of WR/local operation and can generate interrupts whenever the state
of the synchronization source changes. When the WR link goes down, the FSM automatically
switches the card to local time base mode, retaining the previous value of time base counters
......@@ -381,29 +381,32 @@ Relevant files: @code{fd_acam_timestamper.vhd}, @code{fd_acam_timestamp_postproc
The TDC controller interfaces with the ACAM TDC-GPX chip and does whatever is neccessary to output timestamps aligned with the FD core's time base, as fast (in terms of delay) as possible. That is:
@itemize
@item detection of input pulses, checking their width and generation of coarse (128 ns granularity) timestamps by taking a snapshot of an internal counter,
@item detection of input pulses, checking their width and generation of coarse (256 ns granularity) timestamps by taking a snapshot of an internal counter,
@item reading out the fine part from the ACAM,
@item merging these values together, aligning the result to the local timebase and outputting everything in a format digestible by the pulse generators.
@end itemize
The TDC works by default in a so-called G-Mode, utilizing four tapped delay lines, two for start events and two for stop events. This improves the resolution and average precision at the cost of worst-case error. For calibration purposes, another mode (I-mode) is used, as it provides independent, FPGA driven start input and 4 stop inputs.
@subsection TDC timing
Before we time tag any pulses, we need to make sure the TDC is referenced to something and the time shift between
this something and the ACAM's internal time base is known (or better, fixed). Inside the TDC core, the local time base consists of:
this something and the ACAM's internal time base is known (or even better, constant). Inside the TDC core, the time base consists of:
@itemize
@item @code{utc_count} - seconds counter,
@item @code{coarse_count} - coarse start cycle counter (counting at TDC start signal rising edge in cycles of 128 ns),
@item @code{start_count} - start subcycle counter (0..15, reset with each start cycle of the TDC,
@item @code{subcycle_offset} - offset between the ACAM's and TDC core's timescales.
@item @code{coarse_count} - coarse start cycle counter, that counts TDC start events. In our case, the TDC start period of 256 ns is achieved by driving the Start input with a 7.8125 MHz clock coming from the PLL and gating out every second cycle via ACAM's StartDis input to effectively divide it by 2.
@item @code{start_count} - start subcycle counter (0..31, reset with each start cycle of the TDC,
@item @code{subcycle_offset} - offset between the ACAM's and core's internal timescales.
@end itemize
It's very simple if we work in local time base mode, as
the counters need not be aligned to any other counters. The WR mode is a bit more complicated:
TDC start occurs every 16 reference clock ticks, but a PPS pulse from the Csync
unit can come anytime. The most straightformward method here would be to reset the TDC start
generator at every PPS pulse, but it's unsafe (AD9516's output divider SYNC input is asynchronous).
A snapshot of these counters is sampled for every input event. The values are later postprocessed to obtain White Rabbit-formatted timestamps.
The interesting thing is how the TDC timebase is related to an external time scale, as TDC start events occur at fixed multiplies of 256 ns, but a PPS pulse from the Csync
unit can come anytime (with 8 ns granularity). The most straightformward method here would be to reset the TDC start
generator at every PPS pulse, but it is not very safe, as the AD9516's output divider synchronization feature is asynchronous.
The TDC core employs a simple trick here: when a PPS pulse comes, it stores the difference between the lowest
bits of the Csync coarse counter and the subcycle counter (@code{subcycle_offset} signal in @code{p_start_subcycle_counter} process). This difference is added to the timestamps at the postprocessing stage.
bits of the Csync coarse counter and the subcycle counter (@code{subcycle_offset} signal in @code{p_start_subcycle_counter} process). This difference is added to the timestamps at the postprocessing stage to compensate time base shift.
@ref{fig:tdc_timing} shows the relations between the time base signals.
@float Figure,fig:tdc_timing
......@@ -413,6 +416,28 @@ bits of the Csync coarse counter and the subcycle counter (@code{subcycle_offset
@subsection Input stage and TDC control
This part of the core takes care of the coarse input pulse, TDC start and stop enable singnals. It is responsible for:
@itemize
@item @b{Sampling the coarse pulse input.} This is done in the @code{p_sync_trigger} process which implements
a modified 3-stage synchronizer with enable signal ANDed with the input signal at each synchronization stage,
minimizing the input's on/off reaction time.
@item @b{Safely enable and disable the TDC input}.
There are three processes involved here: @code{p_safety_counter}, which disables the input upon the rising edge
of the incoming pulse and re-enables it a certain time (@code{c_FALLING_REENABLE_TIMEOUT}) after the falling
edge of the currently processed pulse. This prevents the core from generating incorrect timestamps when the
input pulses come too close to each other or in case of poor quality or noise on the falling edge of the signal, which
could be misinterpreted as a spurious input event. Even if the signal quality is fine, such spurious pulses may
occur while plugging the trigger input to a live signal. The remaining processes: @code{p_gen_acam_start_dis}
and @code{p_gen_acam_stop} drive the TDC's START and STOP disable signals. The former ensures that the start
input is not enabled in the middle of a rising edge of the 7.125 MHz start clock and gates the StartDis TDC input to effectively divide the start clock by 2.
The latter enables the stop input when the TDC has received at least one correct start pulse.
@item @b{Reject pulses that are not within the requirements.}
@end itemize
@subsection Host interface
......@@ -486,8 +511,6 @@ have shown that the error between DDMTD calibration mechanism and the external T
For more information on DDMTD phase/time measurement techniques please refer to @ref{book:toms_msc}.
@chapter Long term stability
@chapter Carrier implementation example
This chapter shows how to implement the FD core on an FMC carrier, taking the production design of the SVEC VME carrier equipped with two Fine Delays as an example.
......
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\input texinfo @c -*-texinfo-*-
%
% fine-delay.in - main file for the documentation
%
%%%%
%------------------------------------------------------------------------------
%
% NOTE FOR THE UNAWARE USER
% =========================
%
% This file is a texinfo source. It isn't the binary file of some strange
% editor of mine. If you want ASCII, you should "make fine-delay.txt".
%
%------------------------------------------------------------------------------
%
% This is not a conventional info file...
% I use three extra features:
% - The '%' as a comment marker, if at beginning of line ("\%" -> "%")
% - leading blanks are allowed (this is something I can't live without)
% - braces are automatically escaped when they appear in example blocks
%
@comment %**start of header
@documentlanguage en
@documentencoding UTF-8
@setfilename fine-delay.info
@settitle fine-delay
@iftex
@afourpaper
@end iftex
@paragraphindent 3
@comment %**end of header
@setchapternewpage off
@set update-month October 2011
@finalout
@titlepage
@title Fine Delay User's Manual
@subtitle FMC Delay 1ns-4cha
@author CERN BE-CO-HT / Tomasz Włostowski, Alessandro Rubini
@end titlepage
@headings single
@iftex
@contents
@end iftex
@c ##########################################################################
@node Top
@chapter Introduction
The @i{FMC Delay 1ns-4cha} is an FPGA Mezzanine Card (FMC - VITA 57 standard),
whose main purpose is to produce pulses delayed by a user-programmed value with
respect to the input trigger pulse. The card can also work as a Time to Digital converter (TDC)
or as a programmable pulse generator triggering at a given UTC time.
This document provides an end-user description of Fmc Delay 1ns-4cha's features and its
programming API. Moreover, an explanation of the card's operation and a short carrier FPGA
implementation guide are available for advanced users or developers. For the sake of clarity of this document, the card's
name will be further abbreviated as @i{FmcDelay}.
@menu
* Requirements and supported platforms::
* Card speficications::
* Card operation::
* Programmer's API reference::
* Theory of operation::
* FPGA implementers' guidelines::
* Acknowledgments::
@end menu
@c ##########################################################################
@node Requirements and supported platforms
@chapter Requirements and supported platforms
@i{FmcDelay} can work with any VITA 57-compliant FMC carrier, provided that the carrier's FPGA has enough logic resources.
So far, FmcDelay has been only tested with the CERN's SPEC (Simple PCI-Express Carrier) board and the provided drivers currently
work only with that carrier. A VME version using the SVEC carrier is currently being developed and should be available soon.
In order to operate @i{FmcDelay}, the following hardware/software components are required:
@itemize @bullet
@item A standard PC with at least one free 4x (or wider) PCI-Express slot,
@item A SPEC PCI-Express FMC carrier (supplied with the @i{FmcDelay}),
@item 50-ohm cables with 1-pin LEMO 00 plugs for connecting the I/O signals,
@item Any Linux (kernel 2.6 or 3.0+) distribution,
@item Demo GUI Application requires Python 2.7+ and PyQt 4.0+
@end itemize
@c ==========================================================================
@node Card specifications
@chapter Card specifications
@node Modes of operation
@section Modes of operation
@i{FmcDelay} can work in one or more of the following modes:
@itemize @bullet
@item @b{Pulse Delay}: produces one or more pulse(s) on selected outputs
a given time after an input trigger pulse (fig. 1a)
@item @b{Pulse Generator}: produces one or more pulse(s) on selected outputs starting at an
absolute time value programmed by the user (fig. 1b). In this mode, time base is usually provided by the White Rabbit network.
@item @b{Time to Digital Converter}: tags all trigger and output pulses and delivers the timestamps to the user's application.
@end itemize
@float
@image{drawings/func, 12cm,,,.pdf}
@caption{Fig. 1. @i{FmcDelay} operating modes.}
@end float
Modes (pulse delay/generator) can be selected independently for each output. For example, one can configure the output 1 to delay trigger pulses
by 1 us, and the output 2 to produce a pulse at the beginning of each second. The TDC mode can be enabled for the input and output at any time and
does not interfere with the operation of the channels being time tagged.
@c ==========================================================================
@section Mechanical/Environmental
@noindent @b{Mechanical and environmental specs:}
@itemize @bullet
@item Format: FMC (VITA 57), with rear zone for conduction cooling
@item Operating temperature range: 0 - 90 degC.
@item Carrier connection: 160-pin Low Pin Count FMC connector
@end itemize
@section Electrical
@noindent @b{Inputs/Outputs:}
@itemize @bullet
@item 1 trigger input (LEMO 00)
@item 4 pulse outputs (LEMO 00)
@item 2 LEDs
@item Carrier communication via 160-pin Low Pin Count FMC connector
@end itemize
@noindent @b{Trigger input:}
@itemize
@item TTL/LVTTL levels, DC-coupled. Reception of a trigger pulse is indicated by blinking the "TRIG" LED in the front panel.
@item 2 kOhm or 50 Ohm input impedance (programmable via software). 50 Ohm termination is indicated by the "TERM" LED in the front panel.
@item Power-up input impedance: 2 kOhm.
@item Protected against short circuit, overcurrent (> 200 mA) and overvoltage (up to +28 V).
@item Maximum input pulse edge rise time: 20 ns.
@end itemize
@noindent @b{Outputs:}
@itemize
@item TTL-compatible levels DC-coupled: Voh = 3 V, Vol = 200 mV (50 Ohm load), Voh = 6 V, Vol = 400 mV (high impedance).
@item Output impedance: 50 Ohm (source-terminated)
@item Rise/fall time: 2.5 ns (10%% - 90%%, 50 Ohm load)
@item Power-up state: LOW (2 kOhm pulldown), guaranteed glitch-free.
@item Protected against continuous short circuit, overcurrent and overvoltage (up to +28 V).
@end itemize
@noindent @b{Power supply:}
@itemize
@item Used power supplies: P12V0, P3V3, P3V3_AUX, VADJ (voltage monitor only).
@item Typical current comsumption: 200 mA (P12V0) + 1.5 A (P3V3).
@item Power dissipation: 7 W. Forced cooling is required.
@end itemize
@node Timing
@section Timing
@float
@image{drawings/io_timing, 14cm,,,.pdf}
@caption{Fig. 2. @i{FmcDelay} timing parameter definitions.}
@end float
@noindent @b{Time base:}
@itemize @bullet
@item Onboard oscillator accuracy: +/- 2.5 ppm (i.e. max. 2.5 ns error for a delay of 1 ms).
@item When using White Rabbit as the timing reference: depending on the characteristics of the grandmaster clock and the carrier used. On SPEC v 4.0 FMC carrier, the accuracy is better than 1 ns.
@end itemize
@noindent @b{Input timing:}
@itemize @bullet
@item Minimum pulse width: @math{t_{IW}} = 50 ns. Pulses below 24 ns are rejected.
@item Minimum gap between the last delayed output pulse and subsequent trigger pulse: @math{T_{LT}} = 50 ns
@item Input TDC performance: 400 ps pp accuracy, 27 ps resolution, 70 ps trigger-to-trigger rms jitter (measured at 500 kHz pulse rate)
@end itemize
@noindent @b{Output timing:}
@itemize @bullet
@item Resolution: 10 ps.
@item Accuracy (pulse generator mode): 300 ps.
@item Train generation: trains of 1-65536 pulses or continuous square wave up to 10 MHz.
@item Output-to-output jitter (outputs programmed to the same delay): 10 ps rms.
@item Output-to-output jitter (outputs programmed to to different delays, worst case): 30 ps rms.
@item Output pulse spacing (@math{T_{SP}}) : 100 ns - 16 s. Adjustable in 10 ps steps when both @math{T_{PW}}, @math{T_{GAP}} > 200 ns. Outside that range, @math{T_{SP}} resolution is limited to 4 ns.
@item Output pulse start (@math{t_{START}}) resolution: 10 ps for the rising edge of the pulse, 10 ps for subsequent pulses if the condition above is met, otherwise 4 ns.
@end itemize
@noindent @b{Delay mode specific parameters:}
@itemize @bullet
@item Delay accuracy: < 1 ns.
@item Trigger-to-output jitter: 80 ps rms.
@item Trigger-to-output delay: minimum @math{T_{DLY}} = 500 ns, maximum @math{T_{DLY}} = 120 s.
@item Maximum trigger pulse rate: @math{T_{DLY} + N*(T_{SP} + T_{GAP}) +} 100 ns, where N = number of output pulses.
@item Trigger pulses are ignored until the output with the biggest delay has finished generation of the pulse(s).
@end itemize
@chapter Principles of operation
@b{Note:} If you are an electronics engineer, you can skip this section, as you will most likely find it rather boring.
@float
@image{drawings/analog_digital_delays, 16cm,,,.pdf}
@caption{Fig. 3. Principle of operation of analog and digital delay generators.}
@end float
Contrary to typical analog delay cards, which work by comparing an analog ramp triggered by the input pulse with a voltage proportional to the desired delay,
@i{FmcDelay} is a digital delay generator, which relies on time tag arithmetic. The principle of operation of both generators is illustrated in figure 3.
When a trigger pulse comes to the input, @i{FmcDelay} first produces its' precise time tag using a Time-to-Digital converter (TDC). Afterwards, the time tag is summed together
with the delay preset and the result is passed to a digital pulse generator. In its simplest form, it consists of a free running counter and a comparator. When the counter
reaches the value provided on the input, a pulse is produced on the output. Note that in order for the system to work correctly, both the TDC and the Pulse Generator must
use exactly the same time base (not shown on the drawings).
Digital architecture brings several advantages compared to analog predecessors: Timestamps generated by the TDC can be also passed to the host system,
and the Pulse Generators can be programmed with arbitrary pulse start times instead of @math{t_{TRIG} + T_{DLY}}. Therefore, @i{FmcDelay} can be used simultaneously as
a TDC, pulse generator or a pulse delay.
% @c ##########################################################################
@bye
doc/fixinfo deleted 100644 → 0
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;; use:
;; emacs -batch -l ./fixinfo.el <file>
;; or, better:
;; emacs -batch --no-site-file -l ./fixinfo.el <file>
(defun fixinfo (file)
(find-file-other-window file)
(message (concat "Maxing texinfo tree in " file))
(texinfo-all-menus-update)
(texinfo-every-node-update)
(save-buffer)
(kill-buffer (current-buffer))
)
;; loop over command line arguments
(mapcar 'fixinfo command-line-args-left)
(kill-emacs)
doc/infofilter deleted 100644 → 0
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#! /usr/bin/sed -f
# allow "%" as a comment char, but only at the beginning of the line
s/^%/@c /
#s/[^\\]%.*$//
s/^\\%/%/
#preserve blanks and braces in @example blocks
/@example/,/@end example/ s/{/@{/g
/@example/,/@end example/ s/}/@}/g
/@example/,/@end example/ p
/@example/,/@end example/ d
/@smallexample/,/@end smallexample/ s/{/@{/g
/@smallexample/,/@end smallexample/ s/}/@}/g
/@smallexample/,/@end smallexample/ p
/@smallexample/,/@end smallexample/ d
# remove leading blanks
s/^[ ]*//
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