Commit d78c214c authored by Tomasz Wlostowski's avatar Tomasz Wlostowski

rtl: removed alignment of the DCR register to 8 (it was a bug hidden by wrong…

rtl: removed alignment of the DCR register to 8 (it was a bug hidden by wrong alignment handling bug in wbgen)
parent b2a1db4e
...@@ -3,7 +3,7 @@ ...@@ -3,7 +3,7 @@
--------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------
-- File : fd_channel_wbgen2_pkg.vhd -- File : fd_channel_wbgen2_pkg.vhd
-- Author : auto-generated by wbgen2 from fd_channel_wishbone_slave.wb -- Author : auto-generated by wbgen2 from fd_channel_wishbone_slave.wb
-- Created : Thu Jul 4 10:40:48 2013 -- Created : Wed Dec 4 17:20:17 2013
-- Standard : VHDL'87 -- Standard : VHDL'87
--------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE fd_channel_wishbone_slave.wb -- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE fd_channel_wishbone_slave.wb
...@@ -86,11 +86,11 @@ end package; ...@@ -86,11 +86,11 @@ end package;
package body fd_channel_wbgen2_pkg is package body fd_channel_wbgen2_pkg is
function f_x_to_zero (x:std_logic) return std_logic is function f_x_to_zero (x:std_logic) return std_logic is
begin begin
if(x = 'X' or x = 'U') then if x = '1' then
return '0'; return '1';
else else
return x; return '0';
end if; end if;
end function; end function;
function f_x_to_zero (x:std_logic_vector) return std_logic_vector is function f_x_to_zero (x:std_logic_vector) return std_logic_vector is
variable tmp: std_logic_vector(x'length-1 downto 0); variable tmp: std_logic_vector(x'length-1 downto 0);
......
...@@ -3,7 +3,7 @@ ...@@ -3,7 +3,7 @@
--------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------
-- File : fd_channel_wishbone_slave.vhd -- File : fd_channel_wishbone_slave.vhd
-- Author : auto-generated by wbgen2 from fd_channel_wishbone_slave.wb -- Author : auto-generated by wbgen2 from fd_channel_wishbone_slave.wb
-- Created : Thu Jul 4 13:50:31 2013 -- Created : Wed Dec 4 17:20:17 2013
-- Standard : VHDL'87 -- Standard : VHDL'87
--------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE fd_channel_wishbone_slave.wb -- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE fd_channel_wishbone_slave.wb
......
...@@ -50,7 +50,6 @@ peripheral { ...@@ -50,7 +50,6 @@ peripheral {
name = "Delay Control Register"; name = "Delay Control Register";
description = "Main control registers of the particular output channel of the Fine Delay Core."; description = "Main control registers of the particular output channel of the Fine Delay Core.";
prefix = "DCR"; prefix = "DCR";
align = 8;
field { field {
name = "Enable channel"; name = "Enable channel";
......
...@@ -3,7 +3,7 @@ ...@@ -3,7 +3,7 @@
--------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------
-- File : fd_main_wbgen2_pkg.vhd -- File : fd_main_wbgen2_pkg.vhd
-- Author : auto-generated by wbgen2 from fd_main_wishbone_slave.wb -- Author : auto-generated by wbgen2 from fd_main_wishbone_slave.wb
-- Created : Thu Jul 4 10:40:48 2013 -- Created : Wed Dec 4 17:20:16 2013
-- Standard : VHDL'87 -- Standard : VHDL'87
--------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE fd_main_wishbone_slave.wb -- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE fd_main_wishbone_slave.wb
...@@ -217,11 +217,11 @@ end package; ...@@ -217,11 +217,11 @@ end package;
package body fd_main_wbgen2_pkg is package body fd_main_wbgen2_pkg is
function f_x_to_zero (x:std_logic) return std_logic is function f_x_to_zero (x:std_logic) return std_logic is
begin begin
if(x = 'X' or x = 'U') then if x = '1' then
return '0'; return '1';
else else
return x; return '0';
end if; end if;
end function; end function;
function f_x_to_zero (x:std_logic_vector) return std_logic_vector is function f_x_to_zero (x:std_logic_vector) return std_logic_vector is
variable tmp: std_logic_vector(x'length-1 downto 0); variable tmp: std_logic_vector(x'length-1 downto 0);
......
...@@ -3,7 +3,7 @@ ...@@ -3,7 +3,7 @@
--------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------
-- File : fd_main_wishbone_slave.vhd -- File : fd_main_wishbone_slave.vhd
-- Author : auto-generated by wbgen2 from fd_main_wishbone_slave.wb -- Author : auto-generated by wbgen2 from fd_main_wishbone_slave.wb
-- Created : Thu Jul 4 10:40:48 2013 -- Created : Wed Dec 4 17:20:16 2013
-- Standard : VHDL'87 -- Standard : VHDL'87
--------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE fd_main_wishbone_slave.wb -- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE fd_main_wishbone_slave.wb
......
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