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FMC DEL 1ns 4cha
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FMC DEL 1ns 4cha
Commits
d459367b
Commit
d459367b
authored
Feb 27, 2012
by
Tomasz Wlostowski
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software: updated register definitions and header for V3 HW
parent
9cc135fb
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5 changed files
with
593 additions
and
22 deletions
+593
-22
fd_channel_regs.h
software/include/fd_channel_regs.h
+122
-0
fd_main_regs.h
software/include/fd_main_regs.h
+445
-0
fdelay_lib.h
software/include/fdelay_lib.h
+4
-2
fdelay_private.h
software/include/fdelay_private.h
+17
-15
pll_config.h
software/include/pll_config.h
+5
-5
No files found.
software/include/fd_channel_regs.h
0 → 100644
View file @
d459367b
/*
Register definitions for slave core: Fine Delay Channel WB Slave
* File : fd_channel_regs.h
* Author : auto-generated by wbgen2 from fd_channel_wishbone_slave.wb
* Created : Mon Feb 27 13:58:08 2012
* Standard : ANSI C
THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE fd_channel_wishbone_slave.wb
DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
*/
#ifndef __WBGEN2_REGDEFS_FD_CHANNEL_WISHBONE_SLAVE_WB
#define __WBGEN2_REGDEFS_FD_CHANNEL_WISHBONE_SLAVE_WB
#include <inttypes.h>
#if defined( __GNUC__)
#define PACKED __attribute__ ((packed))
#else
#error "Unsupported compiler?"
#endif
#ifndef __WBGEN2_MACROS_DEFINED__
#define __WBGEN2_MACROS_DEFINED__
#define WBGEN2_GEN_MASK(offset, size) (((1<<(size))-1) << (offset))
#define WBGEN2_GEN_WRITE(value, offset, size) (((value) & ((1<<(size))-1)) << (offset))
#define WBGEN2_GEN_READ(reg, offset, size) (((reg) >> (offset)) & ((1<<(size))-1))
#define WBGEN2_SIGN_EXTEND(value, bits) (((value) & (1<<bits) ? ~((1<<(bits))-1): 0 ) | (value))
#endif
/* definitions for register: Delay Control Register */
/* definitions for field: Enable channel in reg: Delay Control Register */
#define FD_DCR_ENABLE WBGEN2_GEN_MASK(0, 1)
/* definitions for field: Delay mode select in reg: Delay Control Register */
#define FD_DCR_MODE WBGEN2_GEN_MASK(1, 1)
/* definitions for field: Pulse generator arm in reg: Delay Control Register */
#define FD_DCR_PG_ARM WBGEN2_GEN_MASK(2, 1)
/* definitions for field: Pulse generator triggered in reg: Delay Control Register */
#define FD_DCR_PG_TRIG WBGEN2_GEN_MASK(3, 1)
/* definitions for field: Start Delay Update in reg: Delay Control Register */
#define FD_DCR_UPDATE WBGEN2_GEN_MASK(4, 1)
/* definitions for field: Delay Update Done in reg: Delay Control Register */
#define FD_DCR_UPD_DONE WBGEN2_GEN_MASK(5, 1)
/* definitions for field: Force Calibration Delay in reg: Delay Control Register */
#define FD_DCR_FORCE_DLY WBGEN2_GEN_MASK(6, 1)
/* definitions for field: Disable Fine Part update in reg: Delay Control Register */
#define FD_DCR_NO_FINE WBGEN2_GEN_MASK(7, 1)
/* definitions for register: Fine Range Register */
/* definitions for register: Pulse start time / offset (MSB TAI seconds) */
/* definitions for register: Pulse start time / offset (LSB TAI seconds) */
/* definitions for register: Pulse start time / offset (8 ns cycles) */
/* definitions for register: Pulse start time / offset (sub-cycle fine part) */
/* definitions for register: Pulse end time / offset (MSB TAI seconds) */
/* definitions for register: Pulse end time / offset (LSB TAI seconds) */
/* definitions for register: Pulse end time / offset (8 ns cycles) */
/* definitions for register: Pulse end time / offset (sub-cycle fine part) */
/* definitions for register: Pulse spacing (TAI seconds) */
/* definitions for register: Pulse spacing (8 ns cycles) */
/* definitions for register: Pulse spacing (sub-cycle fine part) */
/* definitions for register: Repeat Count Register */
/* definitions for field: Repeat Count in reg: Repeat Count Register */
#define FD_RCR_REP_CNT_MASK WBGEN2_GEN_MASK(0, 16)
#define FD_RCR_REP_CNT_SHIFT 0
#define FD_RCR_REP_CNT_W(value) WBGEN2_GEN_WRITE(value, 0, 16)
#define FD_RCR_REP_CNT_R(reg) WBGEN2_GEN_READ(reg, 0, 16)
/* definitions for field: Continuous Waveform Mode in reg: Repeat Count Register */
#define FD_RCR_CONT WBGEN2_GEN_MASK(16, 1)
/* [0x0]: REG Delay Control Register */
#define FD_REG_DCR 0x00000000
/* [0x4]: REG Fine Range Register */
#define FD_REG_FRR 0x00000004
/* [0x8]: REG Pulse start time / offset (MSB TAI seconds) */
#define FD_REG_U_STARTH 0x00000008
/* [0xc]: REG Pulse start time / offset (LSB TAI seconds) */
#define FD_REG_U_STARTL 0x0000000c
/* [0x10]: REG Pulse start time / offset (8 ns cycles) */
#define FD_REG_C_START 0x00000010
/* [0x14]: REG Pulse start time / offset (sub-cycle fine part) */
#define FD_REG_F_START 0x00000014
/* [0x18]: REG Pulse end time / offset (MSB TAI seconds) */
#define FD_REG_U_ENDH 0x00000018
/* [0x1c]: REG Pulse end time / offset (LSB TAI seconds) */
#define FD_REG_U_ENDL 0x0000001c
/* [0x20]: REG Pulse end time / offset (8 ns cycles) */
#define FD_REG_C_END 0x00000020
/* [0x24]: REG Pulse end time / offset (sub-cycle fine part) */
#define FD_REG_F_END 0x00000024
/* [0x28]: REG Pulse spacing (TAI seconds) */
#define FD_REG_U_DELTA 0x00000028
/* [0x2c]: REG Pulse spacing (8 ns cycles) */
#define FD_REG_C_DELTA 0x0000002c
/* [0x30]: REG Pulse spacing (sub-cycle fine part) */
#define FD_REG_F_DELTA 0x00000030
/* [0x34]: REG Repeat Count Register */
#define FD_REG_RCR 0x00000034
#endif
software/include/fd
elay
_regs.h
→
software/include/fd
_main
_regs.h
View file @
d459367b
This diff is collapsed.
Click to expand it.
software/include/fdelay_lib.h
View file @
d459367b
...
...
@@ -37,10 +37,11 @@ typedef struct fdelay_device
typedef
struct
{
int
32
_t
utc
;
int
64
_t
utc
;
int32_t
coarse
;
int32_t
frac
;
uint16_t
seq_id
;
int
channel
;
}
fdelay_time_t
;
/*
...
...
@@ -60,10 +61,11 @@ int fdelay_init(fdelay_device_t *dev);
int
fdelay_release
(
fdelay_device_t
*
dev
);
int
fdelay_read
(
fdelay_device_t
*
dev
,
fdelay_time_t
*
timestamps
,
int
how_many
);
int
fdelay_configure_trigger
(
fdelay_device_t
*
dev
,
int
enable
,
int
termination
);
int
fdelay_configure_output
(
fdelay_device_t
*
dev
,
int
channel
,
int
enable
,
int64_t
delay_ps
,
int64_t
width_ps
);
int
fdelay_configure_output
(
fdelay_device_t
*
dev
,
int
channel
,
int
enable
,
int64_t
delay_ps
,
int64_t
width_ps
,
int64_t
delta_ps
,
int
rep_count
);
int
fdelay_configure_sync
(
fdelay_device_t
*
dev
,
int
mode
);
int
fdelay_update_sync_status
(
fdelay_device_t
*
dev
);
int
fdelay_set_time
(
fdelay_device_t
*
dev
,
const
fdelay_time_t
t
);
#endif
software/include/fdelay_private.h
View file @
d459367b
/*
/*
FmcDelay1ns4Cha (a.k.a. The Fine Delay Card)
User-space driver/library
Private includes
Tomasz Włostowski/BE-CO-HT, 2011
(c) Copyright CERN 2011
Licensed under LGPL 2.1
*/
...
...
@@ -22,8 +22,8 @@
/* MCP23S17 GPIO expander pin locations: bit 8 = select bank 2, bits 7..0 = mask of the pin in the selected bank */
#define SGPIO_TERM_EN (1<<0)
/* Input termination enable (1 = on) */
#define SGPIO_OUTPUT_EN(x) (1<<(6-x))
/* Output driver enable (1 = on) */
#define SGPIO_TRIG_SEL (1<<
3
)
/* TDC trigger select (0 = trigger input, 1 = FPGA) */
#define SGPIO_CAL_EN (1<<
3
)
/* Calibration mode enable (0 = on) */
#define SGPIO_TRIG_SEL (1<<
6
)
/* TDC trigger select (0 = trigger input, 1 = FPGA) */
#define SGPIO_CAL_EN (1<<
7
)
/* Calibration mode enable (0 = on) */
/* ACAM TDC operation modes */
#define ACAM_RMODE 0
...
...
@@ -31,8 +31,9 @@
/* MCP23S17 register addresses (only ones which are used by the lib) */
#define MCP_IODIR 0x0
#define MCP_
GPIO 0x12
#define MCP_
OLAT 0x14
#define MCP_IOCON 0x0a
#define MCP_GPIO 0x12
/* Number of fractional bits in the timestamps/time definitions. Must be consistent with the HDL bitstream. */
#define FDELAY_FRAC_BITS 12
...
...
@@ -62,10 +63,8 @@ struct fine_delay_calibration {
uint32_t
adsfr_val
;
/* ADSFR register value */
uint32_t
acam_start_offset
;
/* ACAM Start offset value */
uint32_t
atmcr_val
;
/* ATMCR register value */
int32_t
dly_tempco
[
4
];
/* SY89295 delay/temperature coefficient in ps/degC << FDELAY_FRAC_BITS */
int32_t
zero_tempco
[
4
];
/* Zero offset/temperature coefficient in ps/degC << FDELAY_FRAC_BITS */
int32_t
cal_temp
;
/* Calibration temperature in 0.1 degC */
uint32_t
tdc_zero_offset
;
/* Zero offset of the TDC, in picoseconds */
int64_t
frr_poly
[
3
];
/* SY89295 delay/temperature polynomial coefficients */
}
__attribute__
((
packed
));
/* Internal state of the fine delay card */
...
...
@@ -74,17 +73,20 @@ struct fine_delay_hw
uint32_t
base_addr
;
/* Base address of the core */
uint32_t
base_onewire
;
/* Base address of the core */
uint32_t
base_i2c
;
/* SPI Controller offset */
double
acam_bin
;
/* bin size of the ACAM TDC - calculated for */
uint32_t
frr
[
4
];
/* Fine range register for each output, determi*/
int32_t
board_temp
;
/* Current temperature of the board in 0.1 degC */
uint32_t
acam_addr
;
/* Current state of ACAM's address lines */
double
acam_bin
;
/* bin size of the ACAM TDC - calculated for 31.25 MHz reference */
uint32_t
frr_offset
[
4
];
/* Offset between the FRR measured at a known temperature at startup and poly-fitted FRR */
uint32_t
frr_cur
[
4
];
/* Fine range register for each output, current value (after online temp. compensation) */
int32_t
cal_temp
;
/* SY89295 calibration temperature in 1/16 degC units */
int32_t
board_temp
;
/* Current temperature of the board, unit = 1/16 degC */
int
wr_enabled
;
int
wr_state
;
struct
fine_delay_calibration
calib
;
};
/* some useful access/declaration macros */
#define fd_writel(data, addr) dev->writel(dev->priv_io, data, (
dev
->base_addr + (addr)))
#define fd_readl(addr) dev->readl(dev->priv_io, (
dev
->base_addr + (addr)))
#define fd_writel(data, addr) dev->writel(dev->priv_io, data, (
hw
->base_addr + (addr)))
#define fd_readl(addr) dev->readl(dev->priv_io, (
hw
->base_addr + (addr)))
#define fd_decl_private(dev) struct fine_delay_hw *hw = (struct fine_delay_hw *) dev->priv_fd;
...
...
software/include/pll_config.h
View file @
d459367b
...
...
@@ -11,7 +11,7 @@ const struct {int reg; uint8_t val; } ad9516_regs[] = {
{
0x0014
,
0x12
},
{
0x0015
,
0x00
},
{
0x0016
,
0x05
},
{
0x0017
,
0x
00
},
{
0x0017
,
0x
b4
},
/* PLL_STATUS = Lock Detect */
{
0x0018
,
0x07
},
{
0x0019
,
0x00
},
{
0x001A
,
0x00
},
...
...
@@ -35,7 +35,7 @@ const struct {int reg; uint8_t val; } ad9516_regs[] = {
{
0x00F0
,
0x08
},
{
0x00F1
,
0x08
},
{
0x00F2
,
0x08
},
{
0x00F3
,
0x
08
},
{
0x00F3
,
0x
18
},
/* out3 inverted */
{
0x00F4
,
0x00
},
{
0x00F5
,
0x08
},
{
0x0140
,
0x5A
},
...
...
@@ -43,10 +43,10 @@ const struct {int reg; uint8_t val; } ad9516_regs[] = {
{
0x0142
,
0x5B
},
{
0x0143
,
0x42
},
{
0x0190
,
0x00
},
{
0x0191
,
0x
0
0
},
{
0x0191
,
0x
8
0
},
{
0x0192
,
0x00
},
{
0x0193
,
0x00
},
{
0x0194
,
0x
0
0
},
{
0x0194
,
0x
8
0
},
{
0x0195
,
0x00
},
{
0x0196
,
0xFF
},
{
0x0197
,
0x00
},
...
...
@@ -62,7 +62,7 @@ const struct {int reg; uint8_t val; } ad9516_regs[] = {
{
0x01A1
,
0x20
},
{
0x01A2
,
0x00
},
{
0x01A3
,
0x00
},
{
0x01E0
,
0x04
},
{
0x01E0
,
0x04
},
/* VCODIV = 6 */
{
0x01E1
,
0x02
},
{
0x0230
,
0x00
},
{
0x0231
,
0x00
},
...
...
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