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FMC DEL 1ns 4cha
Commit d459367b authored by Tomasz Wlostowski's avatar Tomasz Wlostowski
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software: updated register definitions and header for V3 HW

parent 9cc135fb
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software/include/fd_channel_regs.h 0 → 100644
View file @ d459367b
/*
Register definitions for slave core: Fine Delay Channel WB Slave
* File : fd_channel_regs.h
* Author : auto-generated by wbgen2 from fd_channel_wishbone_slave.wb
* Created : Mon Feb 27 13:58:08 2012
* Standard : ANSI C
THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE fd_channel_wishbone_slave.wb
DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
*/
#ifndef __WBGEN2_REGDEFS_FD_CHANNEL_WISHBONE_SLAVE_WB
#define __WBGEN2_REGDEFS_FD_CHANNEL_WISHBONE_SLAVE_WB
#include <inttypes.h>
#if defined( __GNUC__)
#define PACKED __attribute__ ((packed))
#else
#error "Unsupported compiler?"
#endif
#ifndef __WBGEN2_MACROS_DEFINED__
#define __WBGEN2_MACROS_DEFINED__
#define WBGEN2_GEN_MASK(offset, size) (((1<<(size))-1) << (offset))
#define WBGEN2_GEN_WRITE(value, offset, size) (((value) & ((1<<(size))-1)) << (offset))
#define WBGEN2_GEN_READ(reg, offset, size) (((reg) >> (offset)) & ((1<<(size))-1))
#define WBGEN2_SIGN_EXTEND(value, bits) (((value) & (1<<bits) ? ~((1<<(bits))-1): 0 ) | (value))
#endif
/* definitions for register: Delay Control Register */
/* definitions for field: Enable channel in reg: Delay Control Register */
#define FD_DCR_ENABLE WBGEN2_GEN_MASK(0, 1)
/* definitions for field: Delay mode select in reg: Delay Control Register */
#define FD_DCR_MODE WBGEN2_GEN_MASK(1, 1)
/* definitions for field: Pulse generator arm in reg: Delay Control Register */
#define FD_DCR_PG_ARM WBGEN2_GEN_MASK(2, 1)
/* definitions for field: Pulse generator triggered in reg: Delay Control Register */
#define FD_DCR_PG_TRIG WBGEN2_GEN_MASK(3, 1)
/* definitions for field: Start Delay Update in reg: Delay Control Register */
#define FD_DCR_UPDATE WBGEN2_GEN_MASK(4, 1)
/* definitions for field: Delay Update Done in reg: Delay Control Register */
#define FD_DCR_UPD_DONE WBGEN2_GEN_MASK(5, 1)
/* definitions for field: Force Calibration Delay in reg: Delay Control Register */
#define FD_DCR_FORCE_DLY WBGEN2_GEN_MASK(6, 1)
/* definitions for field: Disable Fine Part update in reg: Delay Control Register */
#define FD_DCR_NO_FINE WBGEN2_GEN_MASK(7, 1)
/* definitions for register: Fine Range Register */
/* definitions for register: Pulse start time / offset (MSB TAI seconds) */
/* definitions for register: Pulse start time / offset (LSB TAI seconds) */
/* definitions for register: Pulse start time / offset (8 ns cycles) */
/* definitions for register: Pulse start time / offset (sub-cycle fine part) */
/* definitions for register: Pulse end time / offset (MSB TAI seconds) */
/* definitions for register: Pulse end time / offset (LSB TAI seconds) */
/* definitions for register: Pulse end time / offset (8 ns cycles) */
/* definitions for register: Pulse end time / offset (sub-cycle fine part) */
/* definitions for register: Pulse spacing (TAI seconds) */
/* definitions for register: Pulse spacing (8 ns cycles) */
/* definitions for register: Pulse spacing (sub-cycle fine part) */
/* definitions for register: Repeat Count Register */
/* definitions for field: Repeat Count in reg: Repeat Count Register */
#define FD_RCR_REP_CNT_MASK WBGEN2_GEN_MASK(0, 16)
#define FD_RCR_REP_CNT_SHIFT 0
#define FD_RCR_REP_CNT_W(value) WBGEN2_GEN_WRITE(value, 0, 16)
#define FD_RCR_REP_CNT_R(reg) WBGEN2_GEN_READ(reg, 0, 16)
/* definitions for field: Continuous Waveform Mode in reg: Repeat Count Register */
#define FD_RCR_CONT WBGEN2_GEN_MASK(16, 1)
/* [0x0]: REG Delay Control Register */
#define FD_REG_DCR 0x00000000
/* [0x4]: REG Fine Range Register */
#define FD_REG_FRR 0x00000004
/* [0x8]: REG Pulse start time / offset (MSB TAI seconds) */
#define FD_REG_U_STARTH 0x00000008
/* [0xc]: REG Pulse start time / offset (LSB TAI seconds) */
#define FD_REG_U_STARTL 0x0000000c
/* [0x10]: REG Pulse start time / offset (8 ns cycles) */
#define FD_REG_C_START 0x00000010
/* [0x14]: REG Pulse start time / offset (sub-cycle fine part) */
#define FD_REG_F_START 0x00000014
/* [0x18]: REG Pulse end time / offset (MSB TAI seconds) */
#define FD_REG_U_ENDH 0x00000018
/* [0x1c]: REG Pulse end time / offset (LSB TAI seconds) */
#define FD_REG_U_ENDL 0x0000001c
/* [0x20]: REG Pulse end time / offset (8 ns cycles) */
#define FD_REG_C_END 0x00000020
/* [0x24]: REG Pulse end time / offset (sub-cycle fine part) */
#define FD_REG_F_END 0x00000024
/* [0x28]: REG Pulse spacing (TAI seconds) */
#define FD_REG_U_DELTA 0x00000028
/* [0x2c]: REG Pulse spacing (8 ns cycles) */
#define FD_REG_C_DELTA 0x0000002c
/* [0x30]: REG Pulse spacing (sub-cycle fine part) */
#define FD_REG_F_DELTA 0x00000030
/* [0x34]: REG Repeat Count Register */
#define FD_REG_RCR 0x00000034
#endif
software/include/fdelay_regs.h → software/include/fd_main_regs.h
View file @ d459367b
/*
Register definitions for slave core: Fine Delay Wishbone slave
Register definitions for slave core: Fine Delay Main WB Slave
* File : fd_core.h
* Author : auto-generated by wbgen2 from fd_wishbone_slave.wb
* Created : Mon Oct 31 17:01:03 2011
* File : fd_main_regs.h
* Author : auto-generated by wbgen2 from fd_main_wishbone_slave.wb
* Created : Mon Feb 27 13:58:07 2012
* Standard : ANSI C
THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE fd_wishbone_slave.wb
THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE fd_main_wishbone_slave.wb
DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
*/
#ifndef __WBGEN2_REGDEFS_FD_WISHBONE_SLAVE_WB
#define __WBGEN2_REGDEFS_FD_WISHBONE_SLAVE_WB
#ifndef __WBGEN2_REGDEFS_FD_MAIN_WISHBONE_SLAVE_WB
#define __WBGEN2_REGDEFS_FD_MAIN_WISHBONE_SLAVE_WB
#include <inttypes.h>
......@@ -33,44 +33,70 @@
/* definitions for register: Reset Register */
/* definitions for field: State of the reset Line of the FMC Card in reg: Reset Register */
#define FD_RSTR_RST_FMC_MASK WBGEN2_GEN_MASK(0, 1)
#define FD_RSTR_RST_FMC_SHIFT 0
#define FD_RSTR_RST_FMC_W(value) WBGEN2_GEN_WRITE(value, 0, 1)
#define FD_RSTR_RST_FMC_R(reg) WBGEN2_GEN_READ(reg, 0, 1)
/* definitions for field: State of the reset of the Fine Delay HDL Core in reg: Reset Register */
#define FD_RSTR_RST_CORE_MASK WBGEN2_GEN_MASK(1, 1)
#define FD_RSTR_RST_CORE_SHIFT 1
#define FD_RSTR_RST_CORE_W(value) WBGEN2_GEN_WRITE(value, 1, 1)
#define FD_RSTR_RST_CORE_R(reg) WBGEN2_GEN_READ(reg, 1, 1)
/* definitions for field: Reset magic value in reg: Reset Register */
#define FD_RSTR_LOCK_MASK WBGEN2_GEN_MASK(16, 16)
#define FD_RSTR_LOCK_SHIFT 16
#define FD_RSTR_LOCK_W(value) WBGEN2_GEN_WRITE(value, 16, 16)
#define FD_RSTR_LOCK_R(reg) WBGEN2_GEN_READ(reg, 16, 16)
/* definitions for register: ID Register */
/* definitions for register: Global Control Register */
/* definitions for field: Bypass delay block in reg: Global Control Register */
/* definitions for field: Bypass Hardware TDC/Delay Controller in reg: Global Control Register */
#define FD_GCR_BYPASS WBGEN2_GEN_MASK(0, 1)
/* definitions for field: Enable trigger input in reg: Global Control Register */
#define FD_GCR_INPUT_EN WBGEN2_GEN_MASK(1, 1)
/* definitions for field: Internal Counter Sync in reg: Global Control Register */
#define FD_GCR_CSYNC_INT WBGEN2_GEN_MASK(2, 1)
/* definitions for field: PLL Locked in reg: Global Control Register */
#define FD_GCR_DDR_LOCKED WBGEN2_GEN_MASK(2, 1)
/* definitions for register: Timing Control Register */
/* definitions for field: DMTD Clock Status in reg: Timing Control Register */
#define FD_TCR_DMTD_STAT WBGEN2_GEN_MASK(0, 1)
/* definitions for field: WR Timing Enable in reg: Timing Control Register */
#define FD_TCR_WR_ENABLE WBGEN2_GEN_MASK(1, 1)
/* definitions for field: WR Timing Locked in reg: Timing Control Register */
#define FD_TCR_WR_LOCKED WBGEN2_GEN_MASK(2, 1)
/* definitions for field: White Rabbit Counter Sync in reg: Global Control Register */
#define FD_GCR_CSYNC_WR WBGEN2_GEN_MASK(3, 1)
/* definitions for field: WR Core Present in reg: Timing Control Register */
#define FD_TCR_WR_PRESENT WBGEN2_GEN_MASK(3, 1)
/* definitions for field: White Rabbit Timecode Ready in reg: Global Control Register */
#define FD_GCR_WR_READY WBGEN2_GEN_MASK(4, 1)
/* definitions for field: WR Core Time Ready in reg: Timing Control Register */
#define FD_TCR_WR_READY WBGEN2_GEN_MASK(4, 1)
/* definitions for field: White Rabbit Locking Enable in reg: Global Control Register */
#define FD_GCR_WR_LOCK_EN WBGEN2_GEN_MASK(5, 1)
/* definitions for field: WR Core Link Up in reg: Timing Control Register */
#define FD_TCR_WR_LINK WBGEN2_GEN_MASK(5, 1)
/* definitions for field: White Rabbit Oscillator Locked in reg: Global Control Register */
#define FD_GCR_WR_LOCKED WBGEN2_GEN_MASK(6, 1)
/* definitions for field: Capture Current Time in reg: Timing Control Register */
#define FD_TCR_CAP_TIME WBGEN2_GEN_MASK(6, 1)
/* definitions for register: TDC Address/Data Register */
/* definitions for field: Set Current Time in reg: Timing Control Register */
#define FD_TCR_SET_TIME WBGEN2_GEN_MASK(7, 1)
/* definitions for field: DATA in reg: TDC Address/Data Register */
#define FD_TAR_DATA_MASK WBGEN2_GEN_MASK(0, 28)
#define FD_TAR_DATA_SHIFT 0
#define FD_TAR_DATA_W(value) WBGEN2_GEN_WRITE(value, 0, 28)
#define FD_TAR_DATA_R(reg) WBGEN2_GEN_READ(reg, 0, 28)
/* definitions for register: Time Register - TAI seconds (MSB) */
/* definitions for field: ADDR in reg: TDC Address/Data Register */
#define FD_TAR_ADDR_MASK WBGEN2_GEN_MASK(28, 4)
#define FD_TAR_ADDR_SHIFT 28
#define FD_TAR_ADDR_W(value) WBGEN2_GEN_WRITE(value, 28, 4)
#define FD_TAR_ADDR_R(reg) WBGEN2_GEN_READ(reg, 28, 4)
/* definitions for register: Time Register - TAI seconds (LSB) */
/* definitions for register: Time Register - sub-second 125 MHz clock cycles */
/* definitions for register: TDC Data Register */
/* definitions for register: TDC control/status reg */
......@@ -80,43 +106,74 @@
/* definitions for field: Start TDC read in reg: TDC control/status reg */
#define FD_TDCSR_READ WBGEN2_GEN_MASK(1, 1)
/* definitions for field: Error flag in reg: TDC control/status reg */
#define FD_TDCSR_ERR WBGEN2_GEN_MASK(2, 1)
/* definitions for field: Interrupt flag in reg: TDC control/status reg */
#define FD_TDCSR_INT WBGEN2_GEN_MASK(3, 1)
/* definitions for field: Load flag in reg: TDC control/status reg */
#define FD_TDCSR_LOAD WBGEN2_GEN_MASK(4, 1)
/* definitions for field: Empty flag in reg: TDC control/status reg */
#define FD_TDCSR_EMPTY WBGEN2_GEN_MASK(5, 1)
#define FD_TDCSR_EMPTY WBGEN2_GEN_MASK(2, 1)
/* definitions for field: Start enable in reg: TDC control/status reg */
#define FD_TDCSR_STOP_EN WBGEN2_GEN_MASK(6, 1)
#define FD_TDCSR_STOP_EN WBGEN2_GEN_MASK(3, 1)
/* definitions for field: Start disable in reg: TDC control/status reg */
#define FD_TDCSR_START_DIS WBGEN2_GEN_MASK(7, 1)
#define FD_TDCSR_START_DIS WBGEN2_GEN_MASK(4, 1)
/* definitions for field: Stop enable in reg: TDC control/status reg */
#define FD_TDCSR_START_EN WBGEN2_GEN_MASK(8, 1)
#define FD_TDCSR_START_EN WBGEN2_GEN_MASK(5, 1)
/* definitions for field: Stop disable in reg: TDC control/status reg */
#define FD_TDCSR_STOP_DIS WBGEN2_GEN_MASK(9, 1)
#define FD_TDCSR_STOP_DIS WBGEN2_GEN_MASK(6, 1)
/* definitions for field: write 1: Pulse the Alutrigger line in reg: TDC control/status reg */
#define FD_TDCSR_ALUTRIG WBGEN2_GEN_MASK(10, 1)
#define FD_TDCSR_ALUTRIG WBGEN2_GEN_MASK(7, 1)
/* definitions for register: Calibration register */
/* definitions for field: Triggers calibration pulses in reg: Calibration register */
#define FD_CALR_CAL_PULSE WBGEN2_GEN_MASK(0, 1)
/* definitions for field: PPS Calibration output enable in reg: Calibration register */
#define FD_CALR_CAL_PPS WBGEN2_GEN_MASK(1, 1)
/* definitions for field: Triggers calibration pulses in reg: Calibration register */
#define FD_CALR_CAL_DMTD WBGEN2_GEN_MASK(2, 1)
/* definitions for field: Enable pulse generation in reg: Calibration register */
#define FD_CALR_PSEL_MASK WBGEN2_GEN_MASK(1, 4)
#define FD_CALR_PSEL_SHIFT 1
#define FD_CALR_PSEL_W(value) WBGEN2_GEN_WRITE(value, 1, 4)
#define FD_CALR_PSEL_R(reg) WBGEN2_GEN_READ(reg, 1, 4)
#define FD_CALR_PSEL_MASK WBGEN2_GEN_MASK(3, 4)
#define FD_CALR_PSEL_SHIFT 3
#define FD_CALR_PSEL_W(value) WBGEN2_GEN_WRITE(value, 3, 4)
#define FD_CALR_PSEL_R(reg) WBGEN2_GEN_READ(reg, 3, 4)
/* definitions for field: DMTD Feedback Channel Select in reg: Calibration register */
#define FD_CALR_DMTD_FBSEL WBGEN2_GEN_MASK(7, 1)
/* definitions for field: DMTD Tag in reg: Calibration register */
#define FD_CALR_DMTD_TAG_MASK WBGEN2_GEN_MASK(8, 23)
#define FD_CALR_DMTD_TAG_SHIFT 8
#define FD_CALR_DMTD_TAG_W(value) WBGEN2_GEN_WRITE(value, 8, 23)
#define FD_CALR_DMTD_TAG_R(reg) WBGEN2_GEN_READ(reg, 8, 23)
/* definitions for field: DMTD Tag Ready in reg: Calibration register */
#define FD_CALR_DMTD_TAG_RDY WBGEN2_GEN_MASK(31, 1)
/* definitions for register: Softpll Register */
/* definitions for field: Frequency/Phase tag in reg: Softpll Register */
#define FD_SPLLR_TAG_MASK WBGEN2_GEN_MASK(0, 20)
#define FD_SPLLR_TAG_SHIFT 0
#define FD_SPLLR_TAG_W(value) WBGEN2_GEN_WRITE(value, 0, 20)
#define FD_SPLLR_TAG_R(reg) WBGEN2_GEN_READ(reg, 0, 20)
/* definitions for field: Tag Ready in reg: Softpll Register */
#define FD_SPLLR_TAG_RDY WBGEN2_GEN_MASK(20, 1)
/* definitions for field: Freq/Phase mode select in reg: Softpll Register */
#define FD_SPLLR_MODE WBGEN2_GEN_MASK(21, 1)
/* definitions for register: Softpll DAC Register */
/* definitions for field: DAC Value in reg: Softpll DAC Register */
#define FD_SDACR_DAC_VAL_MASK WBGEN2_GEN_MASK(0, 16)
#define FD_SDACR_DAC_VAL_SHIFT 0
#define FD_SDACR_DAC_VAL_W(value) WBGEN2_GEN_WRITE(value, 0, 16)
#define FD_SDACR_DAC_VAL_R(reg) WBGEN2_GEN_READ(reg, 0, 16)
/* definitions for register: Acam to Delay line fractional part Scale Factor Register */
......@@ -185,38 +242,70 @@
/* definitions for register: Reference Clock Rate Register */
/* definitions for register: Reference Clock Frequency Register */
/* definitions for register: Timestamp Buffer Control Register */
/* definitions for field: Channel Mask in reg: Timestamp Buffer Control Register */
#define FD_TSBCR_CHAN_MASK_MASK WBGEN2_GEN_MASK(0, 5)
#define FD_TSBCR_CHAN_MASK_SHIFT 0
#define FD_TSBCR_CHAN_MASK_W(value) WBGEN2_GEN_WRITE(value, 0, 5)
#define FD_TSBCR_CHAN_MASK_R(reg) WBGEN2_GEN_READ(reg, 0, 5)
/* definitions for field: Buffer enable in reg: Timestamp Buffer Control Register */
#define FD_TSBCR_ENABLE WBGEN2_GEN_MASK(0, 1)
#define FD_TSBCR_ENABLE WBGEN2_GEN_MASK(5, 1)
/* definitions for field: Buffer purge in reg: Timestamp Buffer Control Register */
#define FD_TSBCR_PURGE WBGEN2_GEN_MASK(1, 1)
#define FD_TSBCR_PURGE WBGEN2_GEN_MASK(6, 1)
/* definitions for field: Reset TS Sequence Number in reg: Timestamp Buffer Control Register */
#define FD_TSBCR_RST_SEQ WBGEN2_GEN_MASK(2, 1)
/* definitions for field: Reset TS Sequence Numbers in reg: Timestamp Buffer Control Register */
#define FD_TSBCR_RST_SEQ WBGEN2_GEN_MASK(7, 1)
/* definitions for field: Buffer full in reg: Timestamp Buffer Control Register */
#define FD_TSBCR_FULL WBGEN2_GEN_MASK(3, 1)
#define FD_TSBCR_FULL WBGEN2_GEN_MASK(8, 1)
/* definitions for field: Buffer empty in reg: Timestamp Buffer Control Register */
#define FD_TSBCR_EMPTY WBGEN2_GEN_MASK(4, 1)
#define FD_TSBCR_EMPTY WBGEN2_GEN_MASK(9, 1)
/* definitions for register: Timestamp Buffer Readout UTC Register */
/* definitions for field: Buffer entries count in reg: Timestamp Buffer Control Register */
#define FD_TSBCR_COUNT_MASK WBGEN2_GEN_MASK(10, 12)
#define FD_TSBCR_COUNT_SHIFT 10
#define FD_TSBCR_COUNT_W(value) WBGEN2_GEN_WRITE(value, 10, 12)
#define FD_TSBCR_COUNT_R(reg) WBGEN2_GEN_READ(reg, 10, 12)
/* definitions for register: Timestamp Buffer Interrupt Register */
/* definitions for field: IRQ timeout [milliseconds] in reg: Timestamp Buffer Interrupt Register */
#define FD_TSBIR_TIMEOUT_MASK WBGEN2_GEN_MASK(0, 10)
#define FD_TSBIR_TIMEOUT_SHIFT 0
#define FD_TSBIR_TIMEOUT_W(value) WBGEN2_GEN_WRITE(value, 0, 10)
#define FD_TSBIR_TIMEOUT_R(reg) WBGEN2_GEN_READ(reg, 0, 10)
/* definitions for field: Interrupt threshold in reg: Timestamp Buffer Interrupt Register */
#define FD_TSBIR_THRESHOLD_MASK WBGEN2_GEN_MASK(10, 12)
#define FD_TSBIR_THRESHOLD_SHIFT 10
#define FD_TSBIR_THRESHOLD_W(value) WBGEN2_GEN_WRITE(value, 10, 12)
#define FD_TSBIR_THRESHOLD_R(reg) WBGEN2_GEN_READ(reg, 10, 12)
/* definitions for register: Timestamp Buffer Readout Seconds Register (MSB) */
/* definitions for register: Timestamp Buffer Readout Seconds Register (LSB) */
/* definitions for register: Timestamp Buffer Readout Cycles Register */
/* definitions for register: Timestamp Buffer Readout Fine / Seq ID Register */
/* definitions for register: Timestamp Buffer Readout Fine / Channel / Seq ID Register */
/* definitions for field: Channel ID in reg: Timestamp Buffer Readout Fine / Channel / Seq ID Register */
#define FD_TSBR_FID_CHANNEL_MASK WBGEN2_GEN_MASK(0, 4)
#define FD_TSBR_FID_CHANNEL_SHIFT 0
#define FD_TSBR_FID_CHANNEL_W(value) WBGEN2_GEN_WRITE(value, 0, 4)
#define FD_TSBR_FID_CHANNEL_R(reg) WBGEN2_GEN_READ(reg, 0, 4)
/* definitions for field: Fine Value [in phase units] in reg: Timestamp Buffer Readout Fine / Seq ID Register */
#define FD_TSBR_FID_FINE_MASK WBGEN2_GEN_MASK(0, 12)
#define FD_TSBR_FID_FINE_SHIFT 0
#define FD_TSBR_FID_FINE_W(value) WBGEN2_GEN_WRITE(value, 0, 12)
#define FD_TSBR_FID_FINE_R(reg) WBGEN2_GEN_READ(reg, 0, 12)
/* definitions for field: Fine Value [in phase units] in reg: Timestamp Buffer Readout Fine / Channel / Seq ID Register */
#define FD_TSBR_FID_FINE_MASK WBGEN2_GEN_MASK(4, 12)
#define FD_TSBR_FID_FINE_SHIFT 4
#define FD_TSBR_FID_FINE_W(value) WBGEN2_GEN_WRITE(value, 4, 12)
#define FD_TSBR_FID_FINE_R(reg) WBGEN2_GEN_READ(reg, 4, 12)
/* definitions for field: Timestamp Sequence ID in reg: Timestamp Buffer Readout Fine / Seq ID Register */
/* definitions for field: Timestamp Sequence ID in reg: Timestamp Buffer Readout Fine / Channel / Seq ID Register */
#define FD_TSBR_FID_SEQID_MASK WBGEN2_GEN_MASK(16, 16)
#define FD_TSBR_FID_SEQID_SHIFT 16
#define FD_TSBR_FID_SEQID_W(value) WBGEN2_GEN_WRITE(value, 16, 16)
......@@ -236,322 +325,121 @@
/* definitions for field: SDA Line in in reg: I2C bitbanged IO register */
#define FD_I2CR_SDA_IN WBGEN2_GEN_MASK(3, 1)
/* definitions for register: Delay Control Register (channel 1) */
/* definitions for field: Enable channel in reg: Delay Control Register (channel 1) */
#define FD_DCR1_ENABLE WBGEN2_GEN_MASK(0, 1)
/* definitions for field: Delay mode select in reg: Delay Control Register (channel 1) */
#define FD_DCR1_MODE WBGEN2_GEN_MASK(1, 1)
/* definitions for field: Pulse generator arm in reg: Delay Control Register (channel 1) */
#define FD_DCR1_PG_ARM WBGEN2_GEN_MASK(2, 1)
/* definitions for field: Pulse generator triggered in reg: Delay Control Register (channel 1) */
#define FD_DCR1_PG_TRIG WBGEN2_GEN_MASK(3, 1)
/* definitions for field: Start Delay Update in reg: Delay Control Register (channel 1) */
#define FD_DCR1_UPDATE WBGEN2_GEN_MASK(4, 1)
/* definitions for field: Delay Update Done in reg: Delay Control Register (channel 1) */
#define FD_DCR1_UPD_DONE WBGEN2_GEN_MASK(5, 1)
/* definitions for field: Force Calibration Delay in reg: Delay Control Register (channel 1) */
#define FD_DCR1_FORCE_DLY WBGEN2_GEN_MASK(6, 1)
/* definitions for field: Output Polarity in reg: Delay Control Register (channel 1) */
#define FD_DCR1_POL WBGEN2_GEN_MASK(7, 1)
/* definitions for register: Fine Range Register (channel 1) */
/* definitions for register: Pulse start time / offset (UTC part, channel 1) */
/* definitions for register: Pulse start time / offset (8 ns cycles, channel 1) */
/* definitions for register: Pulse start time / offset (sub-cycle fine part, channel 1) */
/* definitions for register: Pulse end time / offset (UTC part, channel 1) */
/* definitions for register: Pulse end time / offset (8 ns cycles, channel 1) */
/* definitions for register: Pulse end time / offset (sub-cycle fine part, channel 1) */
/* definitions for register: Delay Control Register (channel 2) */
/* definitions for field: Enable channel in reg: Delay Control Register (channel 2) */
#define FD_DCR2_ENABLE WBGEN2_GEN_MASK(0, 1)
/* definitions for field: Delay mode select in reg: Delay Control Register (channel 2) */
#define FD_DCR2_MODE WBGEN2_GEN_MASK(1, 1)
/* definitions for field: Pulse generator arm in reg: Delay Control Register (channel 2) */
#define FD_DCR2_PG_ARM WBGEN2_GEN_MASK(2, 1)
/* definitions for field: Pulse generator triggered in reg: Delay Control Register (channel 2) */
#define FD_DCR2_PG_TRIG WBGEN2_GEN_MASK(3, 1)
/* definitions for field: Debug in in reg: I2C bitbanged IO register */
#define FD_I2CR_DBG_MASK WBGEN2_GEN_MASK(4, 4)
#define FD_I2CR_DBG_SHIFT 4
#define FD_I2CR_DBG_W(value) WBGEN2_GEN_WRITE(value, 4, 4)
#define FD_I2CR_DBG_R(reg) WBGEN2_GEN_READ(reg, 4, 4)
/* definitions for field: Start Delay Update in reg: Delay Control Register (channel 2) */
#define FD_DCR2_UPDATE WBGEN2_GEN_MASK(4, 1)
/* definitions for field: Delay Update Done in reg: Delay Control Register (channel 2) */
#define FD_DCR2_UPD_DONE WBGEN2_GEN_MASK(5, 1)
/* definitions for field: Force Calibration Delay in reg: Delay Control Register (channel 2) */
#define FD_DCR2_FORCE_DLY WBGEN2_GEN_MASK(6, 1)
/* definitions for field: Output Polarity in reg: Delay Control Register (channel 2) */
#define FD_DCR2_POL WBGEN2_GEN_MASK(7, 1)
/* definitions for register: Fine Range Register (channel 2) */
/* definitions for register: Pulse start time / offset (UTC part, channel 2) */
/* definitions for register: Pulse start time / offset (8 ns cycles, channel 2) */
/* definitions for register: Pulse start time / offset (sub-cycle fine part, channel 2) */
/* definitions for register: Pulse end time / offset (UTC part, channel 2) */
/* definitions for register: Pulse end time / offset (8 ns cycles, channel 2) */
/* definitions for register: Pulse end time / offset (sub-cycle fine part, channel 2) */
/* definitions for register: Delay Control Register (channel 3) */
/* definitions for field: Enable channel in reg: Delay Control Register (channel 3) */
#define FD_DCR3_ENABLE WBGEN2_GEN_MASK(0, 1)
/* definitions for field: Delay mode select in reg: Delay Control Register (channel 3) */
#define FD_DCR3_MODE WBGEN2_GEN_MASK(1, 1)
/* definitions for field: Pulse generator arm in reg: Delay Control Register (channel 3) */
#define FD_DCR3_PG_ARM WBGEN2_GEN_MASK(2, 1)
/* definitions for field: Pulse generator triggered in reg: Delay Control Register (channel 3) */
#define FD_DCR3_PG_TRIG WBGEN2_GEN_MASK(3, 1)
/* definitions for field: Start Delay Update in reg: Delay Control Register (channel 3) */
#define FD_DCR3_UPDATE WBGEN2_GEN_MASK(4, 1)
/* definitions for field: Delay Update Done in reg: Delay Control Register (channel 3) */
#define FD_DCR3_UPD_DONE WBGEN2_GEN_MASK(5, 1)
/* definitions for field: Force Calibration Delay in reg: Delay Control Register (channel 3) */
#define FD_DCR3_FORCE_DLY WBGEN2_GEN_MASK(6, 1)
/* definitions for field: Output Polarity in reg: Delay Control Register (channel 3) */
#define FD_DCR3_POL WBGEN2_GEN_MASK(7, 1)
/* definitions for register: Fine Range Register (channel 3) */
/* definitions for register: Pulse start time / offset (UTC part, channel 3) */
/* definitions for register: Pulse start time / offset (8 ns cycles, channel 3) */
/* definitions for register: Pulse start time / offset (sub-cycle fine part, channel 3) */
/* definitions for register: Pulse end time / offset (UTC part, channel 3) */
/* definitions for register: Pulse end time / offset (8 ns cycles, channel 3) */
/* definitions for register: Pulse end time / offset (sub-cycle fine part, channel 3) */
/* definitions for register: Delay Control Register (channel 4) */
/* definitions for field: Enable channel in reg: Delay Control Register (channel 4) */
#define FD_DCR4_ENABLE WBGEN2_GEN_MASK(0, 1)
/* definitions for field: Delay mode select in reg: Delay Control Register (channel 4) */
#define FD_DCR4_MODE WBGEN2_GEN_MASK(1, 1)
/* definitions for field: Pulse generator arm in reg: Delay Control Register (channel 4) */
#define FD_DCR4_PG_ARM WBGEN2_GEN_MASK(2, 1)
/* definitions for field: Pulse generator triggered in reg: Delay Control Register (channel 4) */
#define FD_DCR4_PG_TRIG WBGEN2_GEN_MASK(3, 1)
/* definitions for field: Start Delay Update in reg: Delay Control Register (channel 4) */
#define FD_DCR4_UPDATE WBGEN2_GEN_MASK(4, 1)
/* definitions for field: Delay Update Done in reg: Delay Control Register (channel 4) */
#define FD_DCR4_UPD_DONE WBGEN2_GEN_MASK(5, 1)
/* definitions for field: Force Calibration Delay in reg: Delay Control Register (channel 4) */
#define FD_DCR4_FORCE_DLY WBGEN2_GEN_MASK(6, 1)
/* definitions for field: Output Polarity in reg: Delay Control Register (channel 4) */
#define FD_DCR4_POL WBGEN2_GEN_MASK(7, 1)
/* definitions for register: Fine Range Register (channel 4) */
/* definitions for register: Pulse start time / offset (UTC part, channel 4) */
/* definitions for register: Pulse start time / offset (8 ns cycles, channel 4) */
/* definitions for register: Pulse start time / offset (sub-cycle fine part, channel 4) */
/* definitions for register: Pulse end time / offset (UTC part, channel 4) */
/* definitions for register: Pulse end time / offset (8 ns cycles, channel 4) */
/* definitions for register: Pulse end time / offset (sub-cycle fine part, channel 4) */
/* definitions for field: Debug out in reg: I2C bitbanged IO register */
#define FD_I2CR_DBGOUT_MASK WBGEN2_GEN_MASK(8, 12)
#define FD_I2CR_DBGOUT_SHIFT 8
#define FD_I2CR_DBGOUT_W(value) WBGEN2_GEN_WRITE(value, 8, 12)
#define FD_I2CR_DBGOUT_R(reg) WBGEN2_GEN_READ(reg, 8, 12)
/* definitions for register: Interrupt disable register */
/* definitions for field: TS Buffer not empty in reg: Interrupt disable register */
/* definitions for field: TS Buffer not empty. in reg: Interrupt disable register */
#define FD_EIC_IDR_TS_BUF_NOTEMPTY WBGEN2_GEN_MASK(0, 1)
/* definitions for field: DMTD Softpll interrupt in reg: Interrupt disable register */
#define FD_EIC_IDR_DMTD_SPLL WBGEN2_GEN_MASK(1, 1)
/* definitions for field: Sync Status Changed in reg: Interrupt disable register */
#define FD_EIC_IDR_SYNC_STATUS WBGEN2_GEN_MASK(2, 1)
/* definitions for register: Interrupt enable register */
/* definitions for field: TS Buffer not empty in reg: Interrupt enable register */
/* definitions for field: TS Buffer not empty. in reg: Interrupt enable register */
#define FD_EIC_IER_TS_BUF_NOTEMPTY WBGEN2_GEN_MASK(0, 1)
/* definitions for register: Interrupt mask register */
/* definitions for field: DMTD Softpll interrupt in reg: Interrupt enable register */
#define FD_EIC_IER_DMTD_SPLL WBGEN2_GEN_MASK(1, 1)
/* definitions for field: TS Buffer not empty in reg: Interrupt mask register */
#define FD_EIC_IMR_TS_BUF_NOTEMPTY WBGEN2_GEN_MASK(0, 1)
/* definitions for field: Sync Status Changed in reg: Interrupt enable register */
#define FD_EIC_IER_SYNC_STATUS WBGEN2_GEN_MASK(2, 1)
/* definitions for register: Interrupt status register */
/* definitions for register: Interrupt mask register */
/* definitions for field: TS Buffer not empty in reg: Interrupt status register */
#define FD_EIC_ISR_TS_BUF_NOTEMPTY WBGEN2_GEN_MASK(0, 1)
/* definitions for field: TS Buffer not empty. in reg: Interrupt mask register */
#define FD_EIC_IMR_TS_BUF_NOTEMPTY WBGEN2_GEN_MASK(0, 1)
/* definitions for register: FIFO 'RAW FIFO' data output register 0 */
/* definitions for field: DMTD Softpll interrupt in reg: Interrupt mask register */
#define FD_EIC_IMR_DMTD_SPLL WBGEN2_GEN_MASK(1, 1)
/* definitions for field: RawFrac in reg: FIFO 'RAW FIFO' data output register 0 */
#define FD_RAWFIFO_R0_FRAC_MASK WBGEN2_GEN_MASK(0, 28)
#define FD_RAWFIFO_R0_FRAC_SHIFT 0
#define FD_RAWFIFO_R0_FRAC_W(value) WBGEN2_GEN_WRITE(value, 0, 28)
#define FD_RAWFIFO_R0_FRAC_R(reg) WBGEN2_GEN_READ(reg, 0, 28)
/* definitions for field: Sync Status Changed in reg: Interrupt mask register */
#define FD_EIC_IMR_SYNC_STATUS WBGEN2_GEN_MASK(2, 1)
/* definitions for register: FIFO 'RAW FIFO' data output register 1 */
/* definitions for register: Interrupt status register */
/* definitions for field: RawCoarse in reg: FIFO 'RAW FIFO' data output register 1 */
#define FD_RAWFIFO_R1_COARSE_MASK WBGEN2_GEN_MASK(0, 28)
#define FD_RAWFIFO_R1_COARSE_SHIFT 0
#define FD_RAWFIFO_R1_COARSE_W(value) WBGEN2_GEN_WRITE(value, 0, 28)
#define FD_RAWFIFO_R1_COARSE_R(reg) WBGEN2_GEN_READ(reg, 0, 28)
/* definitions for field: TS Buffer not empty. in reg: Interrupt status register */
#define FD_EIC_ISR_TS_BUF_NOTEMPTY WBGEN2_GEN_MASK(0, 1)
/* definitions for register: FIFO 'RAW FIFO' control/status register */
/* definitions for field: DMTD Softpll interrupt in reg: Interrupt status register */
#define FD_EIC_ISR_DMTD_SPLL WBGEN2_GEN_MASK(1, 1)
/* definitions for field: FIFO empty flag in reg: FIFO 'RAW FIFO' control/status register */
#define FD_RAWFIFO_CSR_EMPTY WBGEN2_GEN_MASK(17, 1)
/* definitions for field: Sync Status Changed in reg: Interrupt status register */
#define FD_EIC_ISR_SYNC_STATUS WBGEN2_GEN_MASK(2, 1)
/* [0x0]: REG Reset Register */
#define FD_REG_RSTR 0x00000000
/* [0x4]: REG ID Register */
#define FD_REG_IDR 0x00000004
/* [0x8]: REG Global Control Register */
#define FD_REG_GCR 0x00000008
/* [0xc]: REG TDC Address/Data Register */
#define FD_REG_TAR 0x0000000c
/* [0x10]: REG TDC control/status reg */
#define FD_REG_TDCSR 0x00000010
/* [0x14]: REG Calibration register */
#define FD_REG_CALR 0x00000014
/* [0x18]: REG Acam to Delay line fractional part Scale Factor Register */
#define FD_REG_ADSFR 0x00000018
/* [0x1c]: REG Acam Timestamp Merging Control Register */
#define FD_REG_ATMCR 0x0000001c
/* [0x20]: REG Acam Start Offset Register */
#define FD_REG_ASOR 0x00000020
/* [0x24]: REG Raw Input Events Counter Register */
#define FD_REG_IECRAW 0x00000024
/* [0x28]: REG Tagged Input Events Counter Register */
#define FD_REG_IECTAG 0x00000028
/* [0x2c]: REG Input Event Processing Delay Register */
#define FD_REG_IEPD 0x0000002c
/* [0x30]: REG SPI Control Register */
#define FD_REG_SCR 0x00000030
/* [0x34]: REG Reference Clock Rate Register */
#define FD_REG_RCRR 0x00000034
/* [0x38]: REG Reference Clock Frequency Register */
#define FD_REG_RCFR 0x00000038
/* [0x3c]: REG Timestamp Buffer Control Register */
#define FD_REG_TSBCR 0x0000003c
/* [0x40]: REG Timestamp Buffer Readout UTC Register */
#define FD_REG_TSBR_U 0x00000040
/* [0x44]: REG Timestamp Buffer Readout Cycles Register */
#define FD_REG_TSBR_C 0x00000044
/* [0x48]: REG Timestamp Buffer Readout Fine / Seq ID Register */
#define FD_REG_TSBR_FID 0x00000048
/* [0x4c]: REG I2C bitbanged IO register */
#define FD_REG_I2CR 0x0000004c
/* [0x60]: REG Delay Control Register (channel 1) */
#define FD_REG_DCR1 0x00000060
/* [0x64]: REG Fine Range Register (channel 1) */
#define FD_REG_FRR1 0x00000064
/* [0x68]: REG Pulse start time / offset (UTC part, channel 1) */
#define FD_REG_U_START1 0x00000068
/* [0x6c]: REG Pulse start time / offset (8 ns cycles, channel 1) */
#define FD_REG_C_START1 0x0000006c
/* [0x70]: REG Pulse start time / offset (sub-cycle fine part, channel 1) */
#define FD_REG_F_START1 0x00000070
/* [0x74]: REG Pulse end time / offset (UTC part, channel 1) */
#define FD_REG_U_END1 0x00000074
/* [0x78]: REG Pulse end time / offset (8 ns cycles, channel 1) */
#define FD_REG_C_END1 0x00000078
/* [0x7c]: REG Pulse end time / offset (sub-cycle fine part, channel 1) */
#define FD_REG_F_END1 0x0000007c
/* [0x80]: REG Delay Control Register (channel 2) */
#define FD_REG_DCR2 0x00000080
/* [0x84]: REG Fine Range Register (channel 2) */
#define FD_REG_FRR2 0x00000084
/* [0x88]: REG Pulse start time / offset (UTC part, channel 2) */
#define FD_REG_U_START2 0x00000088
/* [0x8c]: REG Pulse start time / offset (8 ns cycles, channel 2) */
#define FD_REG_C_START2 0x0000008c
/* [0x90]: REG Pulse start time / offset (sub-cycle fine part, channel 2) */
#define FD_REG_F_START2 0x00000090
/* [0x94]: REG Pulse end time / offset (UTC part, channel 2) */
#define FD_REG_U_END2 0x00000094
/* [0x98]: REG Pulse end time / offset (8 ns cycles, channel 2) */
#define FD_REG_C_END2 0x00000098
/* [0x9c]: REG Pulse end time / offset (sub-cycle fine part, channel 2) */
#define FD_REG_F_END2 0x0000009c
/* [0xa0]: REG Delay Control Register (channel 3) */
#define FD_REG_DCR3 0x000000a0
/* [0xa4]: REG Fine Range Register (channel 3) */
#define FD_REG_FRR3 0x000000a4
/* [0xa8]: REG Pulse start time / offset (UTC part, channel 3) */
#define FD_REG_U_START3 0x000000a8
/* [0xac]: REG Pulse start time / offset (8 ns cycles, channel 3) */
#define FD_REG_C_START3 0x000000ac
/* [0xb0]: REG Pulse start time / offset (sub-cycle fine part, channel 3) */
#define FD_REG_F_START3 0x000000b0
/* [0xb4]: REG Pulse end time / offset (UTC part, channel 3) */
#define FD_REG_U_END3 0x000000b4
/* [0xb8]: REG Pulse end time / offset (8 ns cycles, channel 3) */
#define FD_REG_C_END3 0x000000b8
/* [0xbc]: REG Pulse end time / offset (sub-cycle fine part, channel 3) */
#define FD_REG_F_END3 0x000000bc
/* [0xc0]: REG Delay Control Register (channel 4) */
#define FD_REG_DCR4 0x000000c0
/* [0xc4]: REG Fine Range Register (channel 4) */
#define FD_REG_FRR4 0x000000c4
/* [0xc8]: REG Pulse start time / offset (UTC part, channel 4) */
#define FD_REG_U_START4 0x000000c8
/* [0xcc]: REG Pulse start time / offset (8 ns cycles, channel 4) */
#define FD_REG_C_START4 0x000000cc
/* [0xd0]: REG Pulse start time / offset (sub-cycle fine part, channel 4) */
#define FD_REG_F_START4 0x000000d0
/* [0xd4]: REG Pulse end time / offset (UTC part, channel 4) */
#define FD_REG_U_END4 0x000000d4
/* [0xd8]: REG Pulse end time / offset (8 ns cycles, channel 4) */
#define FD_REG_C_END4 0x000000d8
/* [0xdc]: REG Pulse end time / offset (sub-cycle fine part, channel 4) */
#define FD_REG_F_END4 0x000000dc
/* [0xe0]: REG Interrupt disable register */
#define FD_REG_EIC_IDR 0x000000e0
/* [0xe4]: REG Interrupt enable register */
#define FD_REG_EIC_IER 0x000000e4
/* [0xe8]: REG Interrupt mask register */
#define FD_REG_EIC_IMR 0x000000e8
/* [0xec]: REG Interrupt status register */
#define FD_REG_EIC_ISR 0x000000ec
/* [0xf0]: REG FIFO 'RAW FIFO' data output register 0 */
#define FD_REG_RAWFIFO_R0 0x000000f0
/* [0xf4]: REG FIFO 'RAW FIFO' data output register 1 */
#define FD_REG_RAWFIFO_R1 0x000000f4
/* [0xf8]: REG FIFO 'RAW FIFO' control/status register */
#define FD_REG_RAWFIFO_CSR 0x000000f8
/* [0xc]: REG Timing Control Register */
#define FD_REG_TCR 0x0000000c
/* [0x10]: REG Time Register - TAI seconds (MSB) */
#define FD_REG_TM_SECH 0x00000010
/* [0x14]: REG Time Register - TAI seconds (LSB) */
#define FD_REG_TM_SECL 0x00000014
/* [0x18]: REG Time Register - sub-second 125 MHz clock cycles */
#define FD_REG_TM_CYCLES 0x00000018
/* [0x1c]: REG TDC Data Register */
#define FD_REG_TDR 0x0000001c
/* [0x20]: REG TDC control/status reg */
#define FD_REG_TDCSR 0x00000020
/* [0x24]: REG Calibration register */
#define FD_REG_CALR 0x00000024
/* [0x28]: REG Softpll Register */
#define FD_REG_SPLLR 0x00000028
/* [0x2c]: REG Softpll DAC Register */
#define FD_REG_SDACR 0x0000002c
/* [0x30]: REG Acam to Delay line fractional part Scale Factor Register */
#define FD_REG_ADSFR 0x00000030
/* [0x34]: REG Acam Timestamp Merging Control Register */
#define FD_REG_ATMCR 0x00000034
/* [0x38]: REG Acam Start Offset Register */
#define FD_REG_ASOR 0x00000038
/* [0x3c]: REG Raw Input Events Counter Register */
#define FD_REG_IECRAW 0x0000003c
/* [0x40]: REG Tagged Input Events Counter Register */
#define FD_REG_IECTAG 0x00000040
/* [0x44]: REG Input Event Processing Delay Register */
#define FD_REG_IEPD 0x00000044
/* [0x48]: REG SPI Control Register */
#define FD_REG_SCR 0x00000048
/* [0x4c]: REG Reference Clock Rate Register */
#define FD_REG_RCRR 0x0000004c
/* [0x50]: REG Timestamp Buffer Control Register */
#define FD_REG_TSBCR 0x00000050
/* [0x54]: REG Timestamp Buffer Interrupt Register */
#define FD_REG_TSBIR 0x00000054
/* [0x58]: REG Timestamp Buffer Readout Seconds Register (MSB) */
#define FD_REG_TSBR_SECH 0x00000058
/* [0x5c]: REG Timestamp Buffer Readout Seconds Register (LSB) */
#define FD_REG_TSBR_SECL 0x0000005c
/* [0x60]: REG Timestamp Buffer Readout Cycles Register */
#define FD_REG_TSBR_CYCLES 0x00000060
/* [0x64]: REG Timestamp Buffer Readout Fine / Channel / Seq ID Register */
#define FD_REG_TSBR_FID 0x00000064
/* [0x68]: REG I2C bitbanged IO register */
#define FD_REG_I2CR 0x00000068
/* [0x80]: REG Interrupt disable register */
#define FD_REG_EIC_IDR 0x00000080
/* [0x84]: REG Interrupt enable register */
#define FD_REG_EIC_IER 0x00000084
/* [0x88]: REG Interrupt mask register */
#define FD_REG_EIC_IMR 0x00000088
/* [0x8c]: REG Interrupt status register */
#define FD_REG_EIC_ISR 0x0000008c
#endif
software/include/fdelay_lib.h
View file @ d459367b
......@@ -37,10 +37,11 @@ typedef struct fdelay_device
typedef struct
{
int32_t utc;
int64_t utc;
int32_t coarse;
int32_t frac;
uint16_t seq_id;
int channel;
} fdelay_time_t;
/*
......@@ -60,10 +61,11 @@ int fdelay_init(fdelay_device_t *dev);
int fdelay_release(fdelay_device_t *dev);
int fdelay_read(fdelay_device_t *dev, fdelay_time_t *timestamps, int how_many);
int fdelay_configure_trigger(fdelay_device_t *dev, int enable, int termination);
int fdelay_configure_output(fdelay_device_t *dev, int channel, int enable, int64_t delay_ps, int64_t width_ps);
int fdelay_configure_output(fdelay_device_t *dev, int channel, int enable, int64_t delay_ps, int64_t width_ps, int64_t delta_ps, int rep_count);
int fdelay_configure_sync(fdelay_device_t *dev, int mode);
int fdelay_update_sync_status(fdelay_device_t *dev);
int fdelay_set_time(fdelay_device_t *dev, const fdelay_time_t t);
#endif
software/include/fdelay_private.h
View file @ d459367b
/*
/*
FmcDelay1ns4Cha (a.k.a. The Fine Delay Card)
User-space driver/library
Private includes
Tomasz Włostowski/BE-CO-HT, 2011
(c) Copyright CERN 2011
Licensed under LGPL 2.1
*/
......@@ -22,8 +22,8 @@
/* MCP23S17 GPIO expander pin locations: bit 8 = select bank 2, bits 7..0 = mask of the pin in the selected bank */
#define SGPIO_TERM_EN (1<<0) /* Input termination enable (1 = on) */
#define SGPIO_OUTPUT_EN(x) (1<<(6-x)) /* Output driver enable (1 = on) */
#define SGPIO_TRIG_SEL (1<<3) /* TDC trigger select (0 = trigger input, 1 = FPGA) */
#define SGPIO_CAL_EN (1<<3) /* Calibration mode enable (0 = on) */
#define SGPIO_TRIG_SEL (1<<6) /* TDC trigger select (0 = trigger input, 1 = FPGA) */
#define SGPIO_CAL_EN (1<<7) /* Calibration mode enable (0 = on) */
/* ACAM TDC operation modes */
#define ACAM_RMODE 0
......@@ -31,8 +31,9 @@
/* MCP23S17 register addresses (only ones which are used by the lib) */
#define MCP_IODIR 0x0
#define MCP_GPIO 0x12
#define MCP_OLAT 0x14
#define MCP_IOCON 0x0a
#define MCP_GPIO 0x12
/* Number of fractional bits in the timestamps/time definitions. Must be consistent with the HDL bitstream. */
#define FDELAY_FRAC_BITS 12
......@@ -62,10 +63,8 @@ struct fine_delay_calibration {
uint32_t adsfr_val; /* ADSFR register value */
uint32_t acam_start_offset; /* ACAM Start offset value */
uint32_t atmcr_val; /* ATMCR register value */
int32_t dly_tempco[4]; /* SY89295 delay/temperature coefficient in ps/degC << FDELAY_FRAC_BITS */
int32_t zero_tempco[4]; /* Zero offset/temperature coefficient in ps/degC << FDELAY_FRAC_BITS */
int32_t cal_temp; /* Calibration temperature in 0.1 degC */
uint32_t tdc_zero_offset; /* Zero offset of the TDC, in picoseconds */
int64_t frr_poly[3]; /* SY89295 delay/temperature polynomial coefficients */
} __attribute__((packed));
/* Internal state of the fine delay card */
......@@ -74,17 +73,20 @@ struct fine_delay_hw
uint32_t base_addr; /* Base address of the core */
uint32_t base_onewire; /* Base address of the core */
uint32_t base_i2c; /* SPI Controller offset */
double acam_bin; /* bin size of the ACAM TDC - calculated for */
uint32_t frr[4]; /* Fine range register for each output, determi*/
int32_t board_temp; /* Current temperature of the board in 0.1 degC */
uint32_t acam_addr; /* Current state of ACAM's address lines */
double acam_bin; /* bin size of the ACAM TDC - calculated for 31.25 MHz reference */
uint32_t frr_offset[4]; /* Offset between the FRR measured at a known temperature at startup and poly-fitted FRR */
uint32_t frr_cur[4]; /* Fine range register for each output, current value (after online temp. compensation) */
int32_t cal_temp; /* SY89295 calibration temperature in 1/16 degC units */
int32_t board_temp; /* Current temperature of the board, unit = 1/16 degC */
int wr_enabled;
int wr_state;
struct fine_delay_calibration calib;
};
/* some useful access/declaration macros */
#define fd_writel(data, addr) dev->writel(dev->priv_io, data, (dev->base_addr + (addr)))
#define fd_readl(addr) dev->readl(dev->priv_io, (dev->base_addr + (addr)))
#define fd_writel(data, addr) dev->writel(dev->priv_io, data, (hw->base_addr + (addr)))
#define fd_readl(addr) dev->readl(dev->priv_io, (hw->base_addr + (addr)))
#define fd_decl_private(dev) struct fine_delay_hw *hw = (struct fine_delay_hw *) dev->priv_fd;
......
software/include/pll_config.h
View file @ d459367b
......@@ -11,7 +11,7 @@ const struct {int reg; uint8_t val; } ad9516_regs[] = {
{0x0014, 0x12},
{0x0015, 0x00},
{0x0016, 0x05},
{0x0017, 0x00},
{0x0017, 0xb4}, /* PLL_STATUS = Lock Detect */
{0x0018, 0x07},
{0x0019, 0x00},
{0x001A, 0x00},
......@@ -35,7 +35,7 @@ const struct {int reg; uint8_t val; } ad9516_regs[] = {
{0x00F0, 0x08},
{0x00F1, 0x08},
{0x00F2, 0x08},
{0x00F3, 0x08},
{0x00F3, 0x18}, /* out3 inverted */
{0x00F4, 0x00},
{0x00F5, 0x08},
{0x0140, 0x5A},
......@@ -43,10 +43,10 @@ const struct {int reg; uint8_t val; } ad9516_regs[] = {
{0x0142, 0x5B},
{0x0143, 0x42},
{0x0190, 0x00},
{0x0191, 0x00},
{0x0191, 0x80},
{0x0192, 0x00},
{0x0193, 0x00},
{0x0194, 0x00},
{0x0194, 0x80},
{0x0195, 0x00},
{0x0196, 0xFF},
{0x0197, 0x00},
......@@ -62,7 +62,7 @@ const struct {int reg; uint8_t val; } ad9516_regs[] = {
{0x01A1, 0x20},
{0x01A2, 0x00},
{0x01A3, 0x00},
{0x01E0, 0x04},
{0x01E0, 0x04}, /* VCODIV = 6 */
{0x01E1, 0x02},
{0x0230, 0x00},
{0x0231, 0x00},
......
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