From d3e6cf13b982c4c7708007e47ab57eade946f9d0 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Tomasz=20W=C5=82ostowski?= <tomasz.wlostowski@cern.ch>
Date: Thu, 13 Mar 2014 10:45:05 +0100
Subject: [PATCH] hdl: added submodule references for SVEC release bitstream

---
 .gitmodules                          |    9 +
 hdl/ip_cores/general-cores           |    1 +
 hdl/ip_cores/vme64x-core             |    1 +
 hdl/ip_cores/wr-cores                |    1 +
 hdl/syn/svec/wr/svec_fine_delay.xise | 2152 +++++++++++++-------------
 5 files changed, 1126 insertions(+), 1038 deletions(-)
 create mode 100644 .gitmodules
 create mode 160000 hdl/ip_cores/general-cores
 create mode 160000 hdl/ip_cores/vme64x-core
 create mode 160000 hdl/ip_cores/wr-cores

diff --git a/.gitmodules b/.gitmodules
new file mode 100644
index 0000000..1b7fe8c
--- /dev/null
+++ b/.gitmodules
@@ -0,0 +1,9 @@
+[submodule "hdl/ip_cores/general-cores"]
+	path = hdl/ip_cores/general-cores
+	url = git://ohwr.org/hdl-core-lib/general-cores.git
+[submodule "hdl/ip_cores/wr-cores"]
+	path = hdl/ip_cores/wr-cores
+	url = git://ohwr.org/hdl-core-lib/wr-cores.git
+[submodule "hdl/ip_cores/vme64x-core"]
+	path = hdl/ip_cores/vme64x-core
+	url = git://ohwr.org/hdl-core-lib/vme64x-core.git
diff --git a/hdl/ip_cores/general-cores b/hdl/ip_cores/general-cores
new file mode 160000
index 0000000..3e530e6
--- /dev/null
+++ b/hdl/ip_cores/general-cores
@@ -0,0 +1 @@
+Subproject commit 3e530e6c0510a7dc89981f620a421480551b3c74
diff --git a/hdl/ip_cores/vme64x-core b/hdl/ip_cores/vme64x-core
new file mode 160000
index 0000000..b2fc3ce
--- /dev/null
+++ b/hdl/ip_cores/vme64x-core
@@ -0,0 +1 @@
+Subproject commit b2fc3ce76485404f831d15f7ce31fdde08e234d5
diff --git a/hdl/ip_cores/wr-cores b/hdl/ip_cores/wr-cores
new file mode 160000
index 0000000..b8aee73
--- /dev/null
+++ b/hdl/ip_cores/wr-cores
@@ -0,0 +1 @@
+Subproject commit b8aee73b631ce492edacae4f8f63ae11377c61c8
diff --git a/hdl/syn/svec/wr/svec_fine_delay.xise b/hdl/syn/svec/wr/svec_fine_delay.xise
index 7ce0743..d49290b 100644
--- a/hdl/syn/svec/wr/svec_fine_delay.xise
+++ b/hdl/syn/svec/wr/svec_fine_delay.xise
@@ -1,1040 +1,1116 @@
-<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+<?xml version="1.0" ?>
 <project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
-
-  <header>
-    <!-- ISE source project file created by Project Navigator.             -->
-    <!--                                                                   -->
-    <!-- This file contains project source information including a list of -->
-    <!-- project source files, project and process properties.  This file, -->
-    <!-- along with the project source files, is sufficient to open and    -->
-    <!-- implement in ISE Project Navigator.                               -->
-    <!--                                                                   -->
-    <!-- Copyright (c) 1995-2011 Xilinx, Inc.  All rights reserved. -->
-  </header>
-
-  <autoManagedFiles>
-    <!-- The following files are identified by `include statements in verilog -->
-    <!-- source files and are automatically managed by Project Navigator.     -->
-    <!--                                                                      -->
-    <!-- Do not hand-edit this section, as it will be overwritten when the    -->
-    <!-- project is analyzed based on files automatically identified as       -->
-    <!-- include files.                                                       -->
-  </autoManagedFiles>
-
-  <properties>
-    <property xil_pn:name="AES Initial Vector spartan6" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="AES Key (Hex String) spartan6" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Add I/O Buffers" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Allow Logic Optimization Across Hierarchy" xil_pn:value="false" xil_pn:valueState="default"/>
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-    <property xil_pn:name="Allow Unexpanded Blocks" xil_pn:value="false" xil_pn:valueState="default"/>
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-    <property xil_pn:name="Allow Unmatched Timing Group Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Analysis Effort Level" xil_pn:value="Standard" xil_pn:valueState="default"/>
-    <property xil_pn:name="Asynchronous To Synchronous" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Auto Implementation Compile Order" xil_pn:value="false" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Auto Implementation Top" xil_pn:value="false" xil_pn:valueState="non-default"/>
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-    <property xil_pn:name="Automatically Insert glbl Module in the Netlist" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Automatically Run Generate Target PROM/ACE File" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="BRAM Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
-    <property xil_pn:name="Bring Out Global Set/Reset Net as a Port" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Bring Out Global Tristate Net as a Port" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Bus Delimiter" xil_pn:value="&lt;>" xil_pn:valueState="default"/>
-    <property xil_pn:name="Case" xil_pn:value="Maintain" xil_pn:valueState="default"/>
-    <property xil_pn:name="Case Implementation Style" xil_pn:value="None" xil_pn:valueState="default"/>
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-    <property xil_pn:name="Change Device Speed To Post Trace" xil_pn:value="-3" xil_pn:valueState="default"/>
-    <property xil_pn:name="Combinatorial Logic Optimization" xil_pn:value="false" xil_pn:valueState="default"/>
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-    <property xil_pn:name="DSP Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
-    <property xil_pn:name="Delay Values To Be Read from SDF" xil_pn:value="Setup Time" xil_pn:valueState="default"/>
-    <property xil_pn:name="Device" xil_pn:value="xc6slx150t" xil_pn:valueState="non-default"/>
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-    <property xil_pn:name="Enable Internal Done Pipe" xil_pn:value="true" xil_pn:valueState="non-default"/>
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-    <property xil_pn:name="Output File Name" xil_pn:value="svec_top" xil_pn:valueState="default"/>
-    <property xil_pn:name="Overwrite Compiled Libraries" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Pack I/O Registers into IOBs" xil_pn:value="Auto" xil_pn:valueState="default"/>
-    <property xil_pn:name="Pack I/O Registers/Latches into IOBs" xil_pn:value="Off" xil_pn:valueState="default"/>
-    <property xil_pn:name="Package" xil_pn:value="fgg900" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Perform Advanced Analysis" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Perform Advanced Analysis Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Perform Timing-Driven Packing and Placement" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Place &amp; Route Effort Level (Overall)" xil_pn:value="High" xil_pn:valueState="default"/>
-    <property xil_pn:name="Place And Route Mode" xil_pn:value="Normal Place and Route" xil_pn:valueState="default"/>
-    <property xil_pn:name="Place MultiBoot Settings into Bitstream spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Placer Effort Level Map" xil_pn:value="High" xil_pn:valueState="default"/>
-    <property xil_pn:name="Placer Extra Effort Map" xil_pn:value="None" xil_pn:valueState="default"/>
-    <property xil_pn:name="Port to be used" xil_pn:value="Auto - default" xil_pn:valueState="default"/>
-    <property xil_pn:name="Post Map Simulation Model Name" xil_pn:value="svec_top_map.v" xil_pn:valueState="default"/>
-    <property xil_pn:name="Post Place &amp; Route Simulation Model Name" xil_pn:value="svec_top_timesim.v" xil_pn:valueState="default"/>
-    <property xil_pn:name="Post Synthesis Simulation Model Name" xil_pn:value="svec_top_synthesis.v" xil_pn:valueState="default"/>
-    <property xil_pn:name="Post Translate Simulation Model Name" xil_pn:value="svec_top_translate.v" xil_pn:valueState="default"/>
-    <property xil_pn:name="Power Reduction Map spartan6" xil_pn:value="Off" xil_pn:valueState="default"/>
-    <property xil_pn:name="Power Reduction Par" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Power Reduction Xst" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Preferred Language" xil_pn:value="Verilog" xil_pn:valueState="default"/>
-    <property xil_pn:name="Produce Verbose Report" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Project Description" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Project Generator" xil_pn:value="ProjNav" xil_pn:valueState="default"/>
-    <property xil_pn:name="Property Specification in Project File" xil_pn:value="Store all values" xil_pn:valueState="default"/>
-    <property xil_pn:name="RAM Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="RAM Style" xil_pn:value="Auto" xil_pn:valueState="default"/>
-    <property xil_pn:name="ROM Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="ROM Style" xil_pn:value="Auto" xil_pn:valueState="default"/>
-    <property xil_pn:name="Read Cores" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Reduce Control Sets" xil_pn:value="Auto" xil_pn:valueState="default"/>
-    <property xil_pn:name="Regenerate Core" xil_pn:value="Under Current Project Setting" xil_pn:valueState="default"/>
-    <property xil_pn:name="Register Balancing" xil_pn:value="No" xil_pn:valueState="default"/>
-    <property xil_pn:name="Register Duplication Map" xil_pn:value="Off" xil_pn:valueState="default"/>
-    <property xil_pn:name="Register Duplication Xst" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Register Ordering spartan6" xil_pn:value="4" xil_pn:valueState="default"/>
-    <property xil_pn:name="Release Write Enable (Output Events)" xil_pn:value="Default (6)" xil_pn:valueState="default"/>
-    <property xil_pn:name="Rename Design Instance in Testbench File to" xil_pn:value="UUT" xil_pn:valueState="default"/>
-    <property xil_pn:name="Rename Top Level Architecture To" xil_pn:value="Structure" xil_pn:valueState="default"/>
-    <property xil_pn:name="Rename Top Level Entity to" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Rename Top Level Module To" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Report Fastest Path(s) in Each Constraint" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Report Fastest Path(s) in Each Constraint Post Trace" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Report Paths by Endpoint" xil_pn:value="3" xil_pn:valueState="default"/>
-    <property xil_pn:name="Report Paths by Endpoint Post Trace" xil_pn:value="3" xil_pn:valueState="default"/>
-    <property xil_pn:name="Report Type" xil_pn:value="Verbose Report" xil_pn:valueState="default"/>
-    <property xil_pn:name="Report Type Post Trace" xil_pn:value="Verbose Report" xil_pn:valueState="default"/>
-    <property xil_pn:name="Report Unconstrained Paths" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Report Unconstrained Paths Post Trace" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Reset On Configuration Pulse Width" xil_pn:value="100" xil_pn:valueState="default"/>
-    <property xil_pn:name="Resource Sharing" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Retain Hierarchy" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Retry Configuration if CRC Error Occurs spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Run Design Rules Checker (DRC)" xil_pn:value="false" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Run for Specified Time" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Run for Specified Time Map" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Run for Specified Time Par" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Run for Specified Time Translate" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Safe Implementation" xil_pn:value="No" xil_pn:valueState="default"/>
-    <property xil_pn:name="Security" xil_pn:value="Enable Readback and Reconfiguration" xil_pn:valueState="default"/>
-    <property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Selected Simulation Root Source Node Post-Map" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Selected Simulation Root Source Node Post-Route" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Selected Simulation Root Source Node Post-Translate" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Selected Simulation Source Node" xil_pn:value="UUT" xil_pn:valueState="default"/>
-    <property xil_pn:name="Set SPI Configuration Bus Width spartan6" xil_pn:value="1" xil_pn:valueState="default"/>
-    <property xil_pn:name="Setup External Master Clock Division spartan6" xil_pn:value="1" xil_pn:valueState="default"/>
-    <property xil_pn:name="Shift Register Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Shift Register Minimum Size spartan6" xil_pn:value="2" xil_pn:valueState="default"/>
-    <property xil_pn:name="Show All Models" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Simulation Model Target" xil_pn:value="Verilog" xil_pn:valueState="default"/>
-    <property xil_pn:name="Simulation Run Time ISim" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
-    <property xil_pn:name="Simulation Run Time Map" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
-    <property xil_pn:name="Simulation Run Time Par" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
-    <property xil_pn:name="Simulation Run Time Translate" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
-    <property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)" xil_pn:valueState="default"/>
-    <property xil_pn:name="Slice Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
-    <property xil_pn:name="Specify 'define Macro Name and Value" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="Default" xil_pn:valueState="default"/>
-    <property xil_pn:name="Specify Top Level Instance Names Post-Map" xil_pn:value="Default" xil_pn:valueState="default"/>
-    <property xil_pn:name="Specify Top Level Instance Names Post-Route" xil_pn:value="Default" xil_pn:valueState="default"/>
-    <property xil_pn:name="Specify Top Level Instance Names Post-Translate" xil_pn:value="Default" xil_pn:valueState="default"/>
-    <property xil_pn:name="Speed Grade" xil_pn:value="-3" xil_pn:valueState="default"/>
-    <property xil_pn:name="Starting Placer Cost Table (1-100) Map spartan6" xil_pn:value="1" xil_pn:valueState="default"/>
-    <property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/>
-    <property xil_pn:name="Target Simulator" xil_pn:value="Please Specify" xil_pn:valueState="default"/>
-    <property xil_pn:name="Timing Mode Map" xil_pn:value="Performance Evaluation" xil_pn:valueState="default"/>
-    <property xil_pn:name="Timing Mode Par" xil_pn:value="Performance Evaluation" xil_pn:valueState="default"/>
-    <property xil_pn:name="Top-Level Module Name in Output Netlist" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Top-Level Source Type" xil_pn:value="HDL" xil_pn:valueState="default"/>
-    <property xil_pn:name="Trim Unconnected Signals" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Tristate On Configuration Pulse Width" xil_pn:value="0" xil_pn:valueState="default"/>
-    <property xil_pn:name="Unused IOB Pins" xil_pn:value="Float" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Use 64-bit PlanAhead on 64-bit Systems" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Clock Enable" xil_pn:value="Auto" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Custom Project File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Custom Project File Post-Map" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Custom Project File Post-Route" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Custom Project File Post-Translate" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Custom Simulation Command File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Custom Simulation Command File Map" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Custom Simulation Command File Par" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Custom Simulation Command File Translate" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Custom Waveform Configuration File Behav" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Custom Waveform Configuration File Map" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Custom Waveform Configuration File Par" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Custom Waveform Configuration File Translate" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use DSP Block spartan6" xil_pn:value="Auto" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use LOC Constraints" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use RLOC Constraints" xil_pn:value="Yes" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Smart Guide" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Synchronous Reset" xil_pn:value="Auto" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Synchronous Set" xil_pn:value="Auto" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Synthesis Constraints File" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="User Browsed Strategy Files" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="UserID Code (8 Digit Hexadecimal)" xil_pn:value="0xFFFFFFFF" xil_pn:valueState="default"/>
-    <property xil_pn:name="VCCAUX Voltage Level spartan6" xil_pn:value="2.5V" xil_pn:valueState="default"/>
-    <property xil_pn:name="VHDL Source Analysis Standard" xil_pn:value="VHDL-93" xil_pn:valueState="default"/>
-    <property xil_pn:name="Value Range Check" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Verilog Macros" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Wait for DCM and PLL Lock (Output Events) spartan6" xil_pn:value="Default (NoWait)" xil_pn:valueState="default"/>
-    <property xil_pn:name="Wakeup Clock spartan6" xil_pn:value="Startup Clock" xil_pn:valueState="default"/>
-    <property xil_pn:name="Watchdog Timer Value spartan6" xil_pn:value="0xFFFF" xil_pn:valueState="default"/>
-    <property xil_pn:name="Working Directory" xil_pn:value="." xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Write Timing Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
-    <!--                                                                                  -->
-    <!-- The following properties are for internal use only. These should not be modified.-->
-    <!--                                                                                  -->
-    <property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="PROP_DesignName" xil_pn:value="svec_fine_delay" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="spartan6" xil_pn:valueState="default"/>
-    <property xil_pn:name="PROP_FPGAConfiguration" xil_pn:value="FPGAConfiguration" xil_pn:valueState="default"/>
-    <property xil_pn:name="PROP_PostMapSimTop" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="PROP_PostParSimTop" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="PROP_PostSynthSimTop" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="PROP_PostXlateSimTop" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="PROP_PreSynthesis" xil_pn:value="PreSynthesis" xil_pn:valueState="default"/>
-    <property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2012-06-15T01:54:52" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="75490B2F46FDA56B834CEF144C627CBB" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="Same" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/>
-  </properties>
-
-  <libraries/>
-
-  <files>
-    <file xil_pn:name="../../../top/svec/wr/svec_top.ucf" xil_pn:type="FILE_UCF">
-      <association xil_pn:name="Implementation" xil_pn:seqID="2"/>
-    </file>
-    <file xil_pn:name="../../../platform/chipscope_icon.ngc" xil_pn:type="FILE_NGC">
-      <association xil_pn:name="Implementation" xil_pn:seqID="3"/>
-    </file>
-    <file xil_pn:name="../../../platform/chipscope_ila.ngc" xil_pn:type="FILE_NGC">
-      <association xil_pn:name="Implementation" xil_pn:seqID="4"/>
-    </file>
-    <file xil_pn:name="../../../../../general-cores/modules/genrams/genram_pkg.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="Implementation" xil_pn:seqID="5"/>
-    </file>
-    <file xil_pn:name="../../../../../general-cores/modules/wishbone/wbgen2/wbgen2_pkg.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="Implementation" xil_pn:seqID="6"/>
-    </file>
-    <file xil_pn:name="../../../../../vme64x-core/trunk/hdl/vme64x-core/rtl/vme64x_pack.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="Implementation" xil_pn:seqID="7"/>
-    </file>
-    <file xil_pn:name="../../../top/svec/wr/bicolor_led_ctrl_pkg.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="Implementation" xil_pn:seqID="8"/>
-    </file>
-    <file xil_pn:name="../../../top/svec/wr/bicolor_led_ctrl.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="Implementation" xil_pn:seqID="9"/>
-    </file>
-    <file xil_pn:name="../../../platform/fd_ddr_driver.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="Implementation" xil_pn:seqID="10"/>
-    </file>
-    <file xil_pn:name="../../../platform/fd_ddr_pll.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="Implementation" xil_pn:seqID="11"/>
-    </file>
-    <file xil_pn:name="../../../../../general-cores/modules/wishbone/wishbone_pkg.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="Implementation" xil_pn:seqID="12"/>
-    </file>
-    <file xil_pn:name="../../../rtl/fd_channel_wbgen2_pkg.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="Implementation" xil_pn:seqID="13"/>
-    </file>
-    <file xil_pn:name="../../../rtl/fd_ts_adder.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="Implementation" xil_pn:seqID="14"/>
-    </file>
-    <file xil_pn:name="../../../../../general-cores/modules/common/gencores_pkg.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="Implementation" xil_pn:seqID="15"/>
-    </file>
-    <file xil_pn:name="../../../rtl/fd_main_wbgen2_pkg.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="Implementation" xil_pn:seqID="16"/>
-    </file>
-    <file xil_pn:name="../../../rtl/fd_timestamper_stat_unit.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="Implementation" xil_pn:seqID="17"/>
-    </file>
-    <file xil_pn:name="../../../rtl/fine_delay_pkg.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="Implementation" xil_pn:seqID="18"/>
-    </file>
-    <file xil_pn:name="../../../rtl/fd_csync_generator.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="Implementation" xil_pn:seqID="19"/>
-    </file>
-    <file xil_pn:name="../../../rtl/fd_delay_line_arbiter.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="Implementation" xil_pn:seqID="20"/>
-    </file>
-    <file xil_pn:name="../../../rtl/fd_spi_master.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="Implementation" xil_pn:seqID="21"/>
-    </file>
-    <file xil_pn:name="../../../rtl/fd_spi_dac_arbiter.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="Implementation" xil_pn:seqID="22"/>
-    </file>
-    <file xil_pn:name="../../../top/svec/wr/synthesis_descriptor.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="Implementation" xil_pn:seqID="23"/>
-    </file>
-    <file xil_pn:name="../../../rtl/fine_delay_core.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="Implementation" xil_pn:seqID="24"/>
-    </file>
-    <file xil_pn:name="../../../rtl/fd_channel_wishbone_slave.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="Implementation" xil_pn:seqID="25"/>
-    </file>
-    <file xil_pn:name="../../../rtl/fd_acam_timestamp_postprocessor.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="Implementation" xil_pn:seqID="26"/>
-    </file>
-    <file xil_pn:name="../../../rtl/fd_delay_channel_driver.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="Implementation" xil_pn:seqID="27"/>
-    </file>
-    <file xil_pn:name="../../../rtl/fd_acam_timestamper.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="Implementation" xil_pn:seqID="28"/>
-    </file>
-    <file xil_pn:name="../../../rtl/fd_dmtd_insertion_calibrator.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="Implementation" xil_pn:seqID="29"/>
-    </file>
-    <file xil_pn:name="../../../rtl/fd_dmtd_with_deglitcher.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="Implementation" xil_pn:seqID="30"/>
-    </file>
-    <file xil_pn:name="../../../../../vme64x-core/trunk/hdl/vme64x-core/rtl/VME_CR_pack.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="Implementation" xil_pn:seqID="31"/>
-    </file>
-    <file xil_pn:name="../../../top/svec/wr/xvme64x_core.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="Implementation" xil_pn:seqID="32"/>
-    </file>
-    <file xil_pn:name="../../../../../vme64x-core/trunk/hdl/vme64x-core/rtl/VME_Access_Decode.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="Implementation" xil_pn:seqID="33"/>
-    </file>
-    <file xil_pn:name="../../../../../vme64x-core/trunk/hdl/vme64x-core/rtl/VME_Am_Match.vhd" xil_pn:type="FILE_VHDL">
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+	<header>
+		<!-- ISE source project file created by Project Navigator.             -->
+		<!--                                                                   -->
+		<!-- This file contains project source information including a list of -->
+		<!-- project source files, project and process properties.  This file, -->
+		<!-- along with the project source files, is sufficient to open and    -->
+		<!-- implement in ISE Project Navigator.                               -->
+		<!--                                                                   -->
+		<!-- Copyright (c) 1995-2011 Xilinx, Inc.  All rights reserved. -->
+</header>
+	<autoManagedFiles>
+		<!-- The following files are identified by `include statements in verilog -->
+		<!-- source files and are automatically managed by Project Navigator.     -->
+		<!--                                                                      -->
+		<!-- Do not hand-edit this section, as it will be overwritten when the    -->
+		<!-- project is analyzed based on files automatically identified as       -->
+		<!-- include files.                                                       -->
+		<file xil_pn:name="../../../../../general-cores/modules/wishbone/wb_lm32/src/lm32_include.v" xil_pn:type="FILE_VERILOG"/>
+		<file xil_pn:name="../../../../../general-cores/modules/wishbone/wb_spi/spi_defines.v" xil_pn:type="FILE_VERILOG"/>
+		<file xil_pn:name="../../../../../general-cores/modules/wishbone/wb_spi/timescale.v" xil_pn:type="FILE_VERILOG"/>
+</autoManagedFiles>
+	<properties>
+		<property xil_pn:name="AES Initial Vector spartan6" xil_pn:value="" xil_pn:valueState="default"/>
+		<property xil_pn:name="AES Key (Hex String) spartan6" xil_pn:value="" xil_pn:valueState="default"/>
+		<property xil_pn:name="Add I/O Buffers" xil_pn:value="true" xil_pn:valueState="default"/>
+		<property xil_pn:name="Allow Logic Optimization Across Hierarchy" xil_pn:value="true" xil_pn:valueState="non-default"/>
+		<property xil_pn:name="Allow SelectMAP Pins to Persist" xil_pn:value="false" xil_pn:valueState="default"/>
+		<property xil_pn:name="Allow Unexpanded Blocks" xil_pn:value="false" xil_pn:valueState="default"/>
+		<property xil_pn:name="Allow Unmatched LOC Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
+		<property xil_pn:name="Allow Unmatched Timing Group Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
+		<property xil_pn:name="Analysis Effort Level" xil_pn:value="Standard" xil_pn:valueState="default"/>
+		<property xil_pn:name="Asynchronous To Synchronous" xil_pn:value="false" xil_pn:valueState="default"/>
+		<property xil_pn:name="Auto Implementation Compile Order" xil_pn:value="true" xil_pn:valueState="default"/>
+		<property xil_pn:name="Auto Implementation Top" xil_pn:value="false" xil_pn:valueState="non-default"/>
+		<property xil_pn:name="Automatic BRAM Packing" xil_pn:value="false" xil_pn:valueState="default"/>
+		<property xil_pn:name="Automatically Insert glbl Module in the Netlist" xil_pn:value="true" xil_pn:valueState="default"/>
+		<property xil_pn:name="Automatically Run Generate Target PROM/ACE File" xil_pn:value="false" xil_pn:valueState="default"/>
+		<property xil_pn:name="BRAM Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
+		<property xil_pn:name="Bring Out Global Set/Reset Net as a Port" xil_pn:value="false" xil_pn:valueState="default"/>
+		<property xil_pn:name="Bring Out Global Tristate Net as a Port" xil_pn:value="false" xil_pn:valueState="default"/>
+		<property xil_pn:name="Bus Delimiter" xil_pn:value="&lt;&gt;" xil_pn:valueState="default"/>
+		<property xil_pn:name="Case" xil_pn:value="Maintain" xil_pn:valueState="default"/>
+		<property xil_pn:name="Case Implementation Style" xil_pn:value="None" xil_pn:valueState="default"/>
+		<property xil_pn:name="Change Device Speed To" xil_pn:value="-3" xil_pn:valueState="default"/>
+		<property xil_pn:name="Change Device Speed To Post Trace" xil_pn:value="-3" xil_pn:valueState="default"/>
+		<property xil_pn:name="Combinatorial Logic Optimization" xil_pn:value="false" xil_pn:valueState="default"/>
+		<property xil_pn:name="Compile EDK Simulation Library" xil_pn:value="false" xil_pn:valueState="default"/>
+		<property xil_pn:name="Compile SIMPRIM (Timing) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
+		<property xil_pn:name="Compile UNISIM (Functional) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
+		<property xil_pn:name="Compile XilinxCoreLib (CORE Generator) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
+		<property xil_pn:name="Compile for HDL Debugging" xil_pn:value="true" xil_pn:valueState="default"/>
+		<property xil_pn:name="Configuration Pin Done" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
+		<property xil_pn:name="Configuration Pin Program" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
+		<property xil_pn:name="Configuration Rate spartan6" xil_pn:value="2" xil_pn:valueState="default"/>
+		<property xil_pn:name="Correlate Output to Input Design" xil_pn:value="false" xil_pn:valueState="default"/>
+		<property xil_pn:name="Create ASCII Configuration File" xil_pn:value="false" xil_pn:valueState="default"/>
+		<property xil_pn:name="Create Binary Configuration File" xil_pn:value="true" xil_pn:valueState="non-default"/>
+		<property xil_pn:name="Create Bit File" xil_pn:value="true" xil_pn:valueState="default"/>
+		<property xil_pn:name="Create I/O Pads from Ports" xil_pn:value="false" xil_pn:valueState="default"/>
+		<property xil_pn:name="Create IEEE 1532 Configuration File spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
+		<property xil_pn:name="Create Logic Allocation File" xil_pn:value="false" xil_pn:valueState="default"/>
+		<property xil_pn:name="Create Mask File" xil_pn:value="false" xil_pn:valueState="default"/>
+		<property xil_pn:name="Create ReadBack Data Files" xil_pn:value="false" xil_pn:valueState="default"/>
+		<property xil_pn:name="Cross Clock Analysis" xil_pn:value="false" xil_pn:valueState="default"/>
+		<property xil_pn:name="DSP Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
+		<property xil_pn:name="Delay Values To Be Read from SDF" xil_pn:value="Setup Time" xil_pn:valueState="default"/>
+		<property xil_pn:name="Device" xil_pn:value="xc6slx150t" xil_pn:valueState="non-default"/>
+		<property xil_pn:name="Device Family" xil_pn:value="Spartan6" xil_pn:valueState="non-default"/>
+		<property xil_pn:name="Device Speed Grade/Select ABS Minimum" xil_pn:value="-3" xil_pn:valueState="default"/>
+		<property xil_pn:name="Disable Detailed Package Model Insertion" xil_pn:value="false" xil_pn:valueState="default"/>
+		<property xil_pn:name="Do Not Escape Signal and Instance Names in Netlist" xil_pn:value="false" xil_pn:valueState="default"/>
+		<property xil_pn:name="Done (Output Events)" xil_pn:value="Default (4)" xil_pn:valueState="default"/>
+		<property xil_pn:name="Drive Awake Pin During Suspend/Wake Sequence spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
+		<property xil_pn:name="Drive Done Pin High" xil_pn:value="false" xil_pn:valueState="default"/>
+		<property xil_pn:name="Enable BitStream Compression" xil_pn:value="false" xil_pn:valueState="default"/>
+		<property xil_pn:name="Enable Cyclic Redundancy Checking (CRC) spartan6" xil_pn:value="true" xil_pn:valueState="default"/>
+		<property xil_pn:name="Enable Debugging of Serial Mode BitStream" xil_pn:value="false" xil_pn:valueState="default"/>
+		<property xil_pn:name="Enable External Master Clock spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
+		<property xil_pn:name="Enable Hardware Co-Simulation" xil_pn:value="false" xil_pn:valueState="default"/>
+		<property xil_pn:name="Enable Internal Done Pipe" xil_pn:value="true" xil_pn:valueState="non-default"/>
+		<property xil_pn:name="Enable Message Filtering" xil_pn:value="false" xil_pn:valueState="default"/>
+		<property xil_pn:name="Enable Multi-Pin Wake-Up Suspend Mode spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
+		<property xil_pn:name="Enable Multi-Threading" xil_pn:value="2" xil_pn:valueState="non-default"/>
+		<property xil_pn:name="Enable Multi-Threading par spartan6" xil_pn:value="Off" xil_pn:valueState="default"/>
+		<property xil_pn:name="Enable Outputs (Output Events)" xil_pn:value="Default (5)" xil_pn:valueState="default"/>
+		<property xil_pn:name="Enable Suspend/Wake Global Set/Reset spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
+		<property xil_pn:name="Encrypt Bitstream spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
+		<property xil_pn:name="Encrypt Key Select spartan6" xil_pn:value="BBRAM" xil_pn:valueState="default"/>
+		<property xil_pn:name="Equivalent Register Removal Map" xil_pn:value="true" xil_pn:valueState="default"/>
+		<property xil_pn:name="Equivalent Register Removal XST" xil_pn:value="true" xil_pn:valueState="default"/>
+		<property xil_pn:name="Essential Bits" xil_pn:value="false" xil_pn:valueState="default"/>
+		<property xil_pn:name="Evaluation Development Board" xil_pn:value="None Specified" xil_pn:valueState="default"/>
+		<property xil_pn:name="Exclude Compilation of Deprecated EDK Cores" xil_pn:value="true" xil_pn:valueState="default"/>
+		<property xil_pn:name="Exclude Compilation of EDK Sub-Libraries" xil_pn:value="false" xil_pn:valueState="default"/>
+		<property xil_pn:name="Extra Cost Tables Map" xil_pn:value="0" xil_pn:valueState="default"/>
+		<property xil_pn:name="Extra Effort (Highest PAR level only)" xil_pn:value="None" xil_pn:valueState="default"/>
+		<property xil_pn:name="FPGA Start-Up Clock" xil_pn:value="CCLK" xil_pn:valueState="default"/>
+		<property xil_pn:name="FSM Encoding Algorithm" xil_pn:value="Auto" xil_pn:valueState="default"/>
+		<property xil_pn:name="FSM Style" xil_pn:value="LUT" xil_pn:valueState="default"/>
+		<property xil_pn:name="Filter Files From Compile Order" xil_pn:value="true" xil_pn:valueState="default"/>
+		<property xil_pn:name="Flatten Output Netlist" xil_pn:value="false" xil_pn:valueState="default"/>
+		<property xil_pn:name="Functional Model Target Language ArchWiz" xil_pn:value="Verilog" xil_pn:valueState="default"/>
+		<property xil_pn:name="Functional Model Target Language Coregen" xil_pn:value="Verilog" xil_pn:valueState="default"/>
+		<property xil_pn:name="Functional Model Target Language Schematic" xil_pn:value="Verilog" xil_pn:valueState="default"/>
+		<property xil_pn:name="GTS Cycle During Suspend/Wakeup Sequence spartan6" xil_pn:value="4" xil_pn:valueState="default"/>
+		<property xil_pn:name="GWE Cycle During Suspend/Wakeup Sequence spartan6" xil_pn:value="5" xil_pn:valueState="default"/>
+		<property xil_pn:name="Generate Architecture Only (No Entity Declaration)" xil_pn:value="false" xil_pn:valueState="default"/>
+		<property xil_pn:name="Generate Asynchronous Delay Report" xil_pn:value="false" xil_pn:valueState="default"/>
+		<property xil_pn:name="Generate Clock Region Report" xil_pn:value="false" xil_pn:valueState="default"/>
+		<property xil_pn:name="Generate Constraints Interaction Report" xil_pn:value="false" xil_pn:valueState="default"/>
+		<property xil_pn:name="Generate Constraints Interaction Report Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
+		<property xil_pn:name="Generate Datasheet Section" xil_pn:value="true" xil_pn:valueState="default"/>
+		<property xil_pn:name="Generate Datasheet Section Post Trace" xil_pn:value="true" xil_pn:valueState="default"/>
+		<property xil_pn:name="Generate Detailed MAP Report" xil_pn:value="true" xil_pn:valueState="non-default"/>
+		<property xil_pn:name="Generate Multiple Hierarchical Netlist Files" xil_pn:value="false" xil_pn:valueState="default"/>
+		<property xil_pn:name="Generate Post-Place &amp; Route Power Report" xil_pn:value="false" xil_pn:valueState="default"/>
+		<property xil_pn:name="Generate Post-Place &amp; Route Simulation Model" xil_pn:value="false" xil_pn:valueState="default"/>
+		<property xil_pn:name="Generate RTL Schematic" xil_pn:value="Yes" xil_pn:valueState="default"/>
+		<property xil_pn:name="Generate SAIF File for Power Optimization/Estimation Par" xil_pn:value="false" xil_pn:valueState="default"/>
+		<property xil_pn:name="Generate Testbench File" xil_pn:value="false" xil_pn:valueState="default"/>
+		<property xil_pn:name="Generate Timegroups Section" xil_pn:value="false" xil_pn:valueState="default"/>
+		<property xil_pn:name="Generate Timegroups Section Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
+		<property xil_pn:name="Generics, Parameters" xil_pn:value="" xil_pn:valueState="default"/>
+		<property xil_pn:name="Global Optimization Goal" xil_pn:value="AllClockNets" xil_pn:valueState="default"/>
+		<property xil_pn:name="Global Optimization map spartan6" xil_pn:value="Off" xil_pn:valueState="default"/>
+		<property xil_pn:name="Global Set/Reset Port Name" xil_pn:value="GSR_PORT" xil_pn:valueState="default"/>
+		<property xil_pn:name="Global Tristate Port Name" xil_pn:value="GTS_PORT" xil_pn:valueState="default"/>
+		<property xil_pn:name="Hierarchy Separator" xil_pn:value="/" xil_pn:valueState="default"/>
+		<property xil_pn:name="ISim UUT Instance Name" xil_pn:value="UUT" xil_pn:valueState="default"/>
+		<property xil_pn:name="Ignore User Timing Constraints Map" xil_pn:value="false" xil_pn:valueState="default"/>
+		<property xil_pn:name="Ignore User Timing Constraints Par" xil_pn:value="false" xil_pn:valueState="default"/>
+		<property xil_pn:name="Implementation Top" xil_pn:value="Architecture|svec_top|rtl" xil_pn:valueState="non-default"/>
+		<property xil_pn:name="Implementation Top File" xil_pn:value="../../../top/svec/wr/svec_top.vhd" xil_pn:valueState="non-default"/>
+		<property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/svec_top" xil_pn:valueState="non-default"/>
+		<property xil_pn:name="Include 'uselib Directive in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
+		<property xil_pn:name="Include SIMPRIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
+		<property xil_pn:name="Include UNISIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
+		<property xil_pn:name="Include sdf_annotate task in Verilog File" xil_pn:value="true" xil_pn:valueState="default"/>
+		<property xil_pn:name="Incremental Compilation" xil_pn:value="true" xil_pn:valueState="default"/>
+		<property xil_pn:name="Insert Buffers to Prevent Pulse Swallowing" xil_pn:value="true" xil_pn:valueState="default"/>
+		<property xil_pn:name="Instantiation Template Target Language Xps" xil_pn:value="Verilog" xil_pn:valueState="default"/>
+		<property xil_pn:name="JTAG Pin TCK" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
+		<property xil_pn:name="JTAG Pin TDI" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
+		<property xil_pn:name="JTAG Pin TDO" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
+		<property xil_pn:name="JTAG Pin TMS" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
+		<property xil_pn:name="Keep Hierarchy" xil_pn:value="No" xil_pn:valueState="default"/>
+		<property xil_pn:name="LUT Combining Map" xil_pn:value="Off" xil_pn:valueState="default"/>
+		<property xil_pn:name="LUT Combining Xst" xil_pn:value="Auto" xil_pn:valueState="default"/>
+		<property xil_pn:name="Language" xil_pn:value="VHDL" xil_pn:valueState="default"/>
+		<property xil_pn:name="Last Applied Goal" xil_pn:value="Balanced" xil_pn:valueState="default"/>
+		<property xil_pn:name="Last Applied Strategy" xil_pn:value="Xilinx Default (unlocked)" xil_pn:valueState="default"/>
+		<property xil_pn:name="Last Unlock Status" xil_pn:value="false" xil_pn:valueState="default"/>
+		<property xil_pn:name="Launch SDK after Export" xil_pn:value="true" xil_pn:valueState="default"/>
+		<property xil_pn:name="Library for Verilog Sources" xil_pn:value="" xil_pn:valueState="default"/>
+		<property xil_pn:name="Load glbl" xil_pn:value="true" xil_pn:valueState="default"/>
+		<property xil_pn:name="Manual Implementation Compile Order" xil_pn:value="false" xil_pn:valueState="default"/>
+		<property xil_pn:name="Map Slice Logic into Unused Block RAMs" xil_pn:value="false" xil_pn:valueState="default"/>
+		<property xil_pn:name="Mask Pins for Multi-Pin Wake-Up Suspend Mode spartan6" xil_pn:value="0x00" xil_pn:valueState="default"/>
+		<property xil_pn:name="Max Fanout" xil_pn:value="100000" xil_pn:valueState="default"/>
+		<property xil_pn:name="Maximum Compression" xil_pn:value="false" xil_pn:valueState="default"/>
+		<property xil_pn:name="Maximum Number of Lines in Report" xil_pn:value="1000" xil_pn:valueState="default"/>
+		<property xil_pn:name="Maximum Signal Name Length" xil_pn:value="20" xil_pn:valueState="default"/>
+		<property xil_pn:name="Move First Flip-Flop Stage" xil_pn:value="true" xil_pn:valueState="default"/>
+		<property xil_pn:name="Move Last Flip-Flop Stage" xil_pn:value="true" xil_pn:valueState="default"/>
+		<property xil_pn:name="MultiBoot: Next Configuration Mode spartan6" xil_pn:value="001" xil_pn:valueState="default"/>
+		<property xil_pn:name="MultiBoot: Starting Address for Golden Configuration spartan6" xil_pn:value="0x00000000" xil_pn:valueState="default"/>
+		<property xil_pn:name="MultiBoot: Starting Address for Next Configuration spartan6" xil_pn:value="0x0b00000" xil_pn:valueState="non-default"/>
+		<property xil_pn:name="MultiBoot: Use New Mode for Next Configuration spartan6" xil_pn:value="true" xil_pn:valueState="default"/>
+		<property xil_pn:name="MultiBoot: User-Defined Register for Failsafe Scheme spartan6" xil_pn:value="0x0000" xil_pn:valueState="default"/>
+		<property xil_pn:name="Netlist Hierarchy" xil_pn:value="As Optimized" xil_pn:valueState="default"/>
+		<property xil_pn:name="Netlist Translation Type" xil_pn:value="Timestamp" xil_pn:valueState="default"/>
+		<property xil_pn:name="Number of Clock Buffers" xil_pn:value="16" xil_pn:valueState="default"/>
+		<property xil_pn:name="Number of Paths in Error/Verbose Report" xil_pn:value="3" xil_pn:valueState="default"/>
+		<property xil_pn:name="Number of Paths in Error/Verbose Report Post Trace" xil_pn:value="3" xil_pn:valueState="default"/>
+		<property xil_pn:name="Optimization Effort spartan6" xil_pn:value="Normal" xil_pn:valueState="default"/>
+		<property xil_pn:name="Optimization Goal" xil_pn:value="Speed" xil_pn:valueState="default"/>
+		<property xil_pn:name="Optimize Instantiated Primitives" xil_pn:value="false" xil_pn:valueState="default"/>
+		<property xil_pn:name="Other Bitgen Command Line Options spartan6" xil_pn:value="" xil_pn:valueState="default"/>
+		<property xil_pn:name="Other Compiler Options" xil_pn:value="" xil_pn:valueState="default"/>
+		<property xil_pn:name="Other Compiler Options Map" xil_pn:value="" xil_pn:valueState="default"/>
+		<property xil_pn:name="Other Compiler Options Par" xil_pn:value="" xil_pn:valueState="default"/>
+		<property xil_pn:name="Other Compiler Options Translate" xil_pn:value="" xil_pn:valueState="default"/>
+		<property xil_pn:name="Other Compxlib Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
+		<property xil_pn:name="Other Map Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
+		<property xil_pn:name="Other NETGEN Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
+		<property xil_pn:name="Other Ngdbuild Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
+		<property xil_pn:name="Other Place &amp; Route Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
+		<property xil_pn:name="Other Simulator Commands Behavioral" xil_pn:value="" xil_pn:valueState="default"/>
+		<property xil_pn:name="Other Simulator Commands Post-Map" xil_pn:value="" xil_pn:valueState="default"/>
+		<property xil_pn:name="Other Simulator Commands Post-Route" xil_pn:value="" xil_pn:valueState="default"/>
+		<property xil_pn:name="Other Simulator Commands Post-Translate" xil_pn:value="" xil_pn:valueState="default"/>
+		<property xil_pn:name="Other XPWR Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
+		<property xil_pn:name="Other XST Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
+		<property xil_pn:name="Output Extended Identifiers" xil_pn:value="false" xil_pn:valueState="default"/>
+		<property xil_pn:name="Output File Name" xil_pn:value="svec_top" xil_pn:valueState="default"/>
+		<property xil_pn:name="Overwrite Compiled Libraries" xil_pn:value="false" xil_pn:valueState="default"/>
+		<property xil_pn:name="Pack I/O Registers into IOBs" xil_pn:value="Auto" xil_pn:valueState="default"/>
+		<property xil_pn:name="Pack I/O Registers/Latches into IOBs" xil_pn:value="For Inputs and Outputs" xil_pn:valueState="non-default"/>
+		<property xil_pn:name="Package" xil_pn:value="fgg900" xil_pn:valueState="non-default"/>
+		<property xil_pn:name="Perform Advanced Analysis" xil_pn:value="false" xil_pn:valueState="default"/>
+		<property xil_pn:name="Perform Advanced Analysis Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
+		<property xil_pn:name="Perform Timing-Driven Packing and Placement" xil_pn:value="false" xil_pn:valueState="default"/>
+		<property xil_pn:name="Place &amp; Route Effort Level (Overall)" xil_pn:value="High" xil_pn:valueState="default"/>
+		<property xil_pn:name="Place And Route Mode" xil_pn:value="Normal Place and Route" xil_pn:valueState="default"/>
+		<property xil_pn:name="Place MultiBoot Settings into Bitstream spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
+		<property xil_pn:name="Placer Effort Level Map" xil_pn:value="High" xil_pn:valueState="default"/>
+		<property xil_pn:name="Placer Extra Effort Map" xil_pn:value="None" xil_pn:valueState="default"/>
+		<property xil_pn:name="Port to be used" xil_pn:value="Auto - default" xil_pn:valueState="default"/>
+		<property xil_pn:name="Post Map Simulation Model Name" xil_pn:value="svec_top_map.v" xil_pn:valueState="default"/>
+		<property xil_pn:name="Post Place &amp; Route Simulation Model Name" xil_pn:value="svec_top_timesim.v" xil_pn:valueState="default"/>
+		<property xil_pn:name="Post Synthesis Simulation Model Name" xil_pn:value="svec_top_synthesis.v" xil_pn:valueState="default"/>
+		<property xil_pn:name="Post Translate Simulation Model Name" xil_pn:value="svec_top_translate.v" xil_pn:valueState="default"/>
+		<property xil_pn:name="Power Reduction Map spartan6" xil_pn:value="Off" xil_pn:valueState="default"/>
+		<property xil_pn:name="Power Reduction Par" xil_pn:value="false" xil_pn:valueState="default"/>
+		<property xil_pn:name="Power Reduction Xst" xil_pn:value="false" xil_pn:valueState="default"/>
+		<property xil_pn:name="Preferred Language" xil_pn:value="Verilog" xil_pn:valueState="default"/>
+		<property xil_pn:name="Produce Verbose Report" xil_pn:value="false" xil_pn:valueState="default"/>
+		<property xil_pn:name="Project Description" xil_pn:value="" xil_pn:valueState="default"/>
+		<property xil_pn:name="Project Generator" xil_pn:value="ProjNav" xil_pn:valueState="default"/>
+		<property xil_pn:name="Property Specification in Project File" xil_pn:value="Store all values" xil_pn:valueState="default"/>
+		<property xil_pn:name="RAM Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
+		<property xil_pn:name="RAM Style" xil_pn:value="Auto" xil_pn:valueState="default"/>
+		<property xil_pn:name="ROM Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
+		<property xil_pn:name="ROM Style" xil_pn:value="Auto" xil_pn:valueState="default"/>
+		<property xil_pn:name="Read Cores" xil_pn:value="true" xil_pn:valueState="default"/>
+		<property xil_pn:name="Reduce Control Sets" xil_pn:value="Auto" xil_pn:valueState="default"/>
+		<property xil_pn:name="Regenerate Core" xil_pn:value="Under Current Project Setting" xil_pn:valueState="default"/>
+		<property xil_pn:name="Register Balancing" xil_pn:value="No" xil_pn:valueState="default"/>
+		<property xil_pn:name="Register Duplication Map" xil_pn:value="Off" xil_pn:valueState="default"/>
+		<property xil_pn:name="Register Duplication Xst" xil_pn:value="true" xil_pn:valueState="default"/>
+		<property xil_pn:name="Register Ordering spartan6" xil_pn:value="4" xil_pn:valueState="default"/>
+		<property xil_pn:name="Release Write Enable (Output Events)" xil_pn:value="Default (6)" xil_pn:valueState="default"/>
+		<property xil_pn:name="Rename Design Instance in Testbench File to" xil_pn:value="UUT" xil_pn:valueState="default"/>
+		<property xil_pn:name="Rename Top Level Architecture To" xil_pn:value="Structure" xil_pn:valueState="default"/>
+		<property xil_pn:name="Rename Top Level Entity to" xil_pn:value="" xil_pn:valueState="default"/>
+		<property xil_pn:name="Rename Top Level Module To" xil_pn:value="" xil_pn:valueState="default"/>
+		<property xil_pn:name="Report Fastest Path(s) in Each Constraint" xil_pn:value="true" xil_pn:valueState="default"/>
+		<property xil_pn:name="Report Fastest Path(s) in Each Constraint Post Trace" xil_pn:value="true" xil_pn:valueState="default"/>
+		<property xil_pn:name="Report Paths by Endpoint" xil_pn:value="3" xil_pn:valueState="default"/>
+		<property xil_pn:name="Report Paths by Endpoint Post Trace" xil_pn:value="3" xil_pn:valueState="default"/>
+		<property xil_pn:name="Report Type" xil_pn:value="Verbose Report" xil_pn:valueState="default"/>
+		<property xil_pn:name="Report Type Post Trace" xil_pn:value="Verbose Report" xil_pn:valueState="default"/>
+		<property xil_pn:name="Report Unconstrained Paths" xil_pn:value="" xil_pn:valueState="default"/>
+		<property xil_pn:name="Report Unconstrained Paths Post Trace" xil_pn:value="" xil_pn:valueState="default"/>
+		<property xil_pn:name="Reset On Configuration Pulse Width" xil_pn:value="100" xil_pn:valueState="default"/>
+		<property xil_pn:name="Resource Sharing" xil_pn:value="true" xil_pn:valueState="default"/>
+		<property xil_pn:name="Retain Hierarchy" xil_pn:value="true" xil_pn:valueState="default"/>
+		<property xil_pn:name="Retry Configuration if CRC Error Occurs spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
+		<property xil_pn:name="Run Design Rules Checker (DRC)" xil_pn:value="false" xil_pn:valueState="non-default"/>
+		<property xil_pn:name="Run for Specified Time" xil_pn:value="true" xil_pn:valueState="default"/>
+		<property xil_pn:name="Run for Specified Time Map" xil_pn:value="true" xil_pn:valueState="default"/>
+		<property xil_pn:name="Run for Specified Time Par" xil_pn:value="true" xil_pn:valueState="default"/>
+		<property xil_pn:name="Run for Specified Time Translate" xil_pn:value="true" xil_pn:valueState="default"/>
+		<property xil_pn:name="Safe Implementation" xil_pn:value="No" xil_pn:valueState="default"/>
+		<property xil_pn:name="Security" xil_pn:value="Enable Readback and Reconfiguration" xil_pn:valueState="default"/>
+		<property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="" xil_pn:valueState="default"/>
+		<property xil_pn:name="Selected Simulation Root Source Node Post-Map" xil_pn:value="" xil_pn:valueState="default"/>
+		<property xil_pn:name="Selected Simulation Root Source Node Post-Route" xil_pn:value="" xil_pn:valueState="default"/>
+		<property xil_pn:name="Selected Simulation Root Source Node Post-Translate" xil_pn:value="" xil_pn:valueState="default"/>
+		<property xil_pn:name="Selected Simulation Source Node" xil_pn:value="UUT" xil_pn:valueState="default"/>
+		<property xil_pn:name="Set SPI Configuration Bus Width spartan6" xil_pn:value="1" xil_pn:valueState="default"/>
+		<property xil_pn:name="Setup External Master Clock Division spartan6" xil_pn:value="1" xil_pn:valueState="default"/>
+		<property xil_pn:name="Shift Register Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
+		<property xil_pn:name="Shift Register Minimum Size spartan6" xil_pn:value="2" xil_pn:valueState="default"/>
+		<property xil_pn:name="Show All Models" xil_pn:value="false" xil_pn:valueState="default"/>
+		<property xil_pn:name="Simulation Model Target" xil_pn:value="Verilog" xil_pn:valueState="default"/>
+		<property xil_pn:name="Simulation Run Time ISim" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
+		<property xil_pn:name="Simulation Run Time Map" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
+		<property xil_pn:name="Simulation Run Time Par" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
+		<property xil_pn:name="Simulation Run Time Translate" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
+		<property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)" xil_pn:valueState="default"/>
+		<property xil_pn:name="Slice Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
+		<property xil_pn:name="Specify 'define Macro Name and Value" xil_pn:value="" xil_pn:valueState="default"/>
+		<property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="Default" xil_pn:valueState="default"/>
+		<property xil_pn:name="Specify Top Level Instance Names Post-Map" xil_pn:value="Default" xil_pn:valueState="default"/>
+		<property xil_pn:name="Specify Top Level Instance Names Post-Route" xil_pn:value="Default" xil_pn:valueState="default"/>
+		<property xil_pn:name="Specify Top Level Instance Names Post-Translate" xil_pn:value="Default" xil_pn:valueState="default"/>
+		<property xil_pn:name="Speed Grade" xil_pn:value="-3" xil_pn:valueState="default"/>
+		<property xil_pn:name="Starting Placer Cost Table (1-100) Map spartan6" xil_pn:value="1" xil_pn:valueState="default"/>
+		<property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/>
+		<property xil_pn:name="Target Simulator" xil_pn:value="Please Specify" xil_pn:valueState="default"/>
+		<property xil_pn:name="Timing Mode Map" xil_pn:value="Performance Evaluation" xil_pn:valueState="default"/>
+		<property xil_pn:name="Timing Mode Par" xil_pn:value="Performance Evaluation" xil_pn:valueState="default"/>
+		<property xil_pn:name="Top-Level Module Name in Output Netlist" xil_pn:value="" xil_pn:valueState="default"/>
+		<property xil_pn:name="Top-Level Source Type" xil_pn:value="HDL" xil_pn:valueState="default"/>
+		<property xil_pn:name="Trim Unconnected Signals" xil_pn:value="true" xil_pn:valueState="default"/>
+		<property xil_pn:name="Tristate On Configuration Pulse Width" xil_pn:value="0" xil_pn:valueState="default"/>
+		<property xil_pn:name="Unused IOB Pins" xil_pn:value="Float" xil_pn:valueState="non-default"/>
+		<property xil_pn:name="Use 64-bit PlanAhead on 64-bit Systems" xil_pn:value="true" xil_pn:valueState="default"/>
+		<property xil_pn:name="Use Clock Enable" xil_pn:value="Auto" xil_pn:valueState="default"/>
+		<property xil_pn:name="Use Custom Project File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/>
+		<property xil_pn:name="Use Custom Project File Post-Map" xil_pn:value="false" xil_pn:valueState="default"/>
+		<property xil_pn:name="Use Custom Project File Post-Route" xil_pn:value="false" xil_pn:valueState="default"/>
+		<property xil_pn:name="Use Custom Project File Post-Translate" xil_pn:value="false" xil_pn:valueState="default"/>
+		<property xil_pn:name="Use Custom Simulation Command File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/>
+		<property xil_pn:name="Use Custom Simulation Command File Map" xil_pn:value="false" xil_pn:valueState="default"/>
+		<property xil_pn:name="Use Custom Simulation Command File Par" xil_pn:value="false" xil_pn:valueState="default"/>
+		<property xil_pn:name="Use Custom Simulation Command File Translate" xil_pn:value="false" xil_pn:valueState="default"/>
+		<property xil_pn:name="Use Custom Waveform Configuration File Behav" xil_pn:value="false" xil_pn:valueState="default"/>
+		<property xil_pn:name="Use Custom Waveform Configuration File Map" xil_pn:value="false" xil_pn:valueState="default"/>
+		<property xil_pn:name="Use Custom Waveform Configuration File Par" xil_pn:value="false" xil_pn:valueState="default"/>
+		<property xil_pn:name="Use Custom Waveform Configuration File Translate" xil_pn:value="false" xil_pn:valueState="default"/>
+		<property xil_pn:name="Use DSP Block spartan6" xil_pn:value="Auto" xil_pn:valueState="default"/>
+		<property xil_pn:name="Use LOC Constraints" xil_pn:value="true" xil_pn:valueState="default"/>
+		<property xil_pn:name="Use RLOC Constraints" xil_pn:value="Yes" xil_pn:valueState="default"/>
+		<property xil_pn:name="Use Smart Guide" xil_pn:value="false" xil_pn:valueState="default"/>
+		<property xil_pn:name="Use Synchronous Reset" xil_pn:value="Auto" xil_pn:valueState="default"/>
+		<property xil_pn:name="Use Synchronous Set" xil_pn:value="Auto" xil_pn:valueState="default"/>
+		<property xil_pn:name="Use Synthesis Constraints File" xil_pn:value="true" xil_pn:valueState="default"/>
+		<property xil_pn:name="User Browsed Strategy Files" xil_pn:value="" xil_pn:valueState="default"/>
+		<property xil_pn:name="UserID Code (8 Digit Hexadecimal)" xil_pn:value="0xFFFFFFFF" xil_pn:valueState="default"/>
+		<property xil_pn:name="VCCAUX Voltage Level spartan6" xil_pn:value="2.5V" xil_pn:valueState="default"/>
+		<property xil_pn:name="VHDL Source Analysis Standard" xil_pn:value="VHDL-93" xil_pn:valueState="default"/>
+		<property xil_pn:name="Value Range Check" xil_pn:value="false" xil_pn:valueState="default"/>
+		<property xil_pn:name="Verilog Macros" xil_pn:value="" xil_pn:valueState="default"/>
+		<property xil_pn:name="Wait for DCM and PLL Lock (Output Events) spartan6" xil_pn:value="Default (NoWait)" xil_pn:valueState="default"/>
+		<property xil_pn:name="Wakeup Clock spartan6" xil_pn:value="Startup Clock" xil_pn:valueState="default"/>
+		<property xil_pn:name="Watchdog Timer Value spartan6" xil_pn:value="0xFFFF" xil_pn:valueState="default"/>
+		<property xil_pn:name="Working Directory" xil_pn:value="." xil_pn:valueState="non-default"/>
+		<property xil_pn:name="Write Timing Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
+		<property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="" xil_pn:valueState="default"/>
+		<property xil_pn:name="PROP_DesignName" xil_pn:value="svec_fine_delay" xil_pn:valueState="non-default"/>
+		<property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="spartan6" xil_pn:valueState="default"/>
+		<property xil_pn:name="PROP_FPGAConfiguration" xil_pn:value="FPGAConfiguration" xil_pn:valueState="default"/>
+		<property xil_pn:name="PROP_PostMapSimTop" xil_pn:value="" xil_pn:valueState="default"/>
+		<property xil_pn:name="PROP_PostParSimTop" xil_pn:value="" xil_pn:valueState="default"/>
+		<property xil_pn:name="PROP_PostSynthSimTop" xil_pn:value="" xil_pn:valueState="default"/>
+		<property xil_pn:name="PROP_PostXlateSimTop" xil_pn:value="" xil_pn:valueState="default"/>
+		<property xil_pn:name="PROP_PreSynthesis" xil_pn:value="PreSynthesis" xil_pn:valueState="default"/>
+		<property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2012-06-15T01:54:52" xil_pn:valueState="non-default"/>
+		<property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="75490B2F46FDA56B834CEF144C627CBB" xil_pn:valueState="non-default"/>
+		<property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="Same" xil_pn:valueState="non-default"/>
+		<property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/>
+</properties>
+	<libraries/>
+	<files>
+		<file xil_pn:name="../../../top/svec/wr/svec_top.ucf" xil_pn:type="FILE_UCF">
+			<association xil_pn:name="Implementation" xil_pn:seqID="2"/>
+</file>
+		<file xil_pn:name="../../../platform/chipscope_icon.ngc" xil_pn:type="FILE_NGC">
+			<association xil_pn:name="Implementation" xil_pn:seqID="3"/>
+</file>
+		<file xil_pn:name="../../../platform/chipscope_ila.ngc" xil_pn:type="FILE_NGC">
+			<association xil_pn:name="Implementation" xil_pn:seqID="4"/>
+</file>
+		<file xil_pn:name="../../../ip_cores/general-cores/modules/genrams/genram_pkg.vhd" xil_pn:type="FILE_VHDL">
+			<association xil_pn:name="Implementation" xil_pn:seqID="5"/>
+</file>
+		<file xil_pn:name="../../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_pkg.vhd" xil_pn:type="FILE_VHDL">
+			<association xil_pn:name="Implementation" xil_pn:seqID="6"/>
+</file>
+		<file xil_pn:name="../../../top/svec/wr/bicolor_led_ctrl_pkg.vhd" xil_pn:type="FILE_VHDL">
+			<association xil_pn:name="Implementation" xil_pn:seqID="7"/>
+</file>
+		<file xil_pn:name="../../../top/svec/wr/bicolor_led_ctrl.vhd" xil_pn:type="FILE_VHDL">
+			<association xil_pn:name="Implementation" xil_pn:seqID="8"/>
+</file>
+		<file xil_pn:name="../../../platform/fd_ddr_driver.vhd" xil_pn:type="FILE_VHDL">
+			<association xil_pn:name="Implementation" xil_pn:seqID="9"/>
+</file>
+		<file xil_pn:name="../../../platform/fd_ddr_pll.vhd" xil_pn:type="FILE_VHDL">
+			<association xil_pn:name="Implementation" xil_pn:seqID="10"/>
+</file>
+		<file xil_pn:name="../../../ip_cores/general-cores/modules/wishbone/wishbone_pkg.vhd" xil_pn:type="FILE_VHDL">
+			<association xil_pn:name="Implementation" xil_pn:seqID="11"/>
+</file>
+		<file xil_pn:name="../../../rtl/fd_channel_wbgen2_pkg.vhd" xil_pn:type="FILE_VHDL">
+			<association xil_pn:name="Implementation" xil_pn:seqID="12"/>
+</file>
+		<file xil_pn:name="../../../rtl/fd_ts_adder.vhd" xil_pn:type="FILE_VHDL">
+			<association xil_pn:name="Implementation" xil_pn:seqID="13"/>
+</file>
+		<file xil_pn:name="../../../ip_cores/general-cores/modules/common/gencores_pkg.vhd" xil_pn:type="FILE_VHDL">
+			<association xil_pn:name="Implementation" xil_pn:seqID="14"/>
+</file>
+		<file xil_pn:name="../../../rtl/fd_main_wbgen2_pkg.vhd" xil_pn:type="FILE_VHDL">
+			<association xil_pn:name="Implementation" xil_pn:seqID="15"/>
+</file>
+		<file xil_pn:name="../../../rtl/fd_timestamper_stat_unit.vhd" xil_pn:type="FILE_VHDL">
+			<association xil_pn:name="Implementation" xil_pn:seqID="16"/>
+</file>
+		<file xil_pn:name="../../../rtl/fine_delay_pkg.vhd" xil_pn:type="FILE_VHDL">
+			<association xil_pn:name="Implementation" xil_pn:seqID="17"/>
+</file>
+		<file xil_pn:name="../../../rtl/fd_csync_generator.vhd" xil_pn:type="FILE_VHDL">
+			<association xil_pn:name="Implementation" xil_pn:seqID="18"/>
+</file>
+		<file xil_pn:name="../../../rtl/fd_delay_line_arbiter.vhd" xil_pn:type="FILE_VHDL">
+			<association xil_pn:name="Implementation" xil_pn:seqID="19"/>
+</file>
+		<file xil_pn:name="../../../rtl/fd_spi_master.vhd" xil_pn:type="FILE_VHDL">
+			<association xil_pn:name="Implementation" xil_pn:seqID="20"/>
+</file>
+		<file xil_pn:name="../../../rtl/fd_spi_dac_arbiter.vhd" xil_pn:type="FILE_VHDL">
+			<association xil_pn:name="Implementation" xil_pn:seqID="21"/>
+</file>
+		<file xil_pn:name="../../../top/svec/wr/synthesis_descriptor.vhd" xil_pn:type="FILE_VHDL">
+			<association xil_pn:name="Implementation" xil_pn:seqID="22"/>
+</file>
+		<file xil_pn:name="../../../rtl/fine_delay_core.vhd" xil_pn:type="FILE_VHDL">
+			<association xil_pn:name="Implementation" xil_pn:seqID="23"/>
+</file>
+		<file xil_pn:name="../../../rtl/fd_channel_wishbone_slave.vhd" xil_pn:type="FILE_VHDL">
+			<association xil_pn:name="Implementation" xil_pn:seqID="24"/>
+</file>
+		<file xil_pn:name="../../../rtl/fd_acam_timestamp_postprocessor.vhd" xil_pn:type="FILE_VHDL">
+			<association xil_pn:name="Implementation" xil_pn:seqID="25"/>
+</file>
+		<file xil_pn:name="../../../rtl/fd_delay_channel_driver.vhd" xil_pn:type="FILE_VHDL">
+			<association xil_pn:name="Implementation" xil_pn:seqID="26"/>
+</file>
+		<file xil_pn:name="../../../rtl/fd_acam_timestamper.vhd" xil_pn:type="FILE_VHDL">
+			<association xil_pn:name="Implementation" xil_pn:seqID="27"/>
+</file>
+		<file xil_pn:name="../../../rtl/fd_dmtd_insertion_calibrator.vhd" xil_pn:type="FILE_VHDL">
+			<association xil_pn:name="Implementation" xil_pn:seqID="28"/>
+</file>
+		<file xil_pn:name="../../../rtl/fd_dmtd_with_deglitcher.vhd" xil_pn:type="FILE_VHDL">
+			<association xil_pn:name="Implementation" xil_pn:seqID="29"/>
+</file>
+		<file xil_pn:name="../../../rtl/fd_reset_generator.vhd" xil_pn:type="FILE_VHDL">
+			<association xil_pn:name="Implementation" xil_pn:seqID="30"/>
+</file>
+		<file xil_pn:name="../../../ip_cores/general-cores/modules/common/gc_crc_gen.vhd" xil_pn:type="FILE_VHDL">
+			<association xil_pn:name="Implementation" xil_pn:seqID="31"/>
+</file>
+		<file xil_pn:name="../../../ip_cores/general-cores/modules/common/gc_moving_average.vhd" xil_pn:type="FILE_VHDL">
+			<association xil_pn:name="Implementation" xil_pn:seqID="32"/>
+</file>
+		<file xil_pn:name="../../../ip_cores/general-cores/modules/common/gc_extend_pulse.vhd" xil_pn:type="FILE_VHDL">
+			<association xil_pn:name="Implementation" xil_pn:seqID="33"/>
+</file>
+		<file xil_pn:name="../../../ip_cores/general-cores/modules/common/gc_delay_gen.vhd" xil_pn:type="FILE_VHDL">
+			<association xil_pn:name="Implementation" xil_pn:seqID="34"/>
+</file>
+		<file xil_pn:name="../../../ip_cores/general-cores/modules/common/gc_dual_pi_controller.vhd" xil_pn:type="FILE_VHDL">
+			<association xil_pn:name="Implementation" xil_pn:seqID="35"/>
+</file>
+		<file xil_pn:name="../../../ip_cores/general-cores/modules/common/gc_reset.vhd" xil_pn:type="FILE_VHDL">
+			<association xil_pn:name="Implementation" xil_pn:seqID="36"/>
+</file>
+		<file xil_pn:name="../../../ip_cores/general-cores/modules/common/gc_serial_dac.vhd" xil_pn:type="FILE_VHDL">
+			<association xil_pn:name="Implementation" xil_pn:seqID="37"/>
+</file>
+		<file xil_pn:name="../../../ip_cores/general-cores/modules/common/gc_sync_ffs.vhd" xil_pn:type="FILE_VHDL">
+			<association xil_pn:name="Implementation" xil_pn:seqID="38"/>
+</file>
+		<file xil_pn:name="../../../ip_cores/general-cores/modules/common/gc_arbitrated_mux.vhd" xil_pn:type="FILE_VHDL">
+			<association xil_pn:name="Implementation" xil_pn:seqID="39"/>
+</file>
+		<file xil_pn:name="../../../ip_cores/general-cores/modules/common/gc_pulse_synchronizer.vhd" xil_pn:type="FILE_VHDL">
+			<association xil_pn:name="Implementation" xil_pn:seqID="40"/>
+</file>
+		<file xil_pn:name="../../../ip_cores/general-cores/modules/common/gc_pulse_synchronizer2.vhd" xil_pn:type="FILE_VHDL">
+			<association xil_pn:name="Implementation" xil_pn:seqID="41"/>
+</file>
+		<file xil_pn:name="../../../ip_cores/general-cores/modules/common/gc_frequency_meter.vhd" xil_pn:type="FILE_VHDL">
+			<association xil_pn:name="Implementation" xil_pn:seqID="42"/>
+</file>
+		<file xil_pn:name="../../../ip_cores/general-cores/modules/common/gc_rr_arbiter.vhd" xil_pn:type="FILE_VHDL">
+			<association xil_pn:name="Implementation" xil_pn:seqID="43"/>
+</file>
+		<file xil_pn:name="../../../ip_cores/general-cores/modules/common/gc_prio_encoder.vhd" xil_pn:type="FILE_VHDL">
+			<association xil_pn:name="Implementation" xil_pn:seqID="44"/>
+</file>
+		<file xil_pn:name="../../../ip_cores/general-cores/modules/common/gc_word_packer.vhd" xil_pn:type="FILE_VHDL">
+			<association xil_pn:name="Implementation" xil_pn:seqID="45"/>
+</file>
+		<file xil_pn:name="../../../ip_cores/general-cores/modules/common/gc_i2c_slave.vhd" xil_pn:type="FILE_VHDL">
+			<association xil_pn:name="Implementation" xil_pn:seqID="46"/>
+</file>
+		<file xil_pn:name="../../../ip_cores/general-cores/modules/common/gc_glitch_filt.vhd" xil_pn:type="FILE_VHDL">
+			<association xil_pn:name="Implementation" xil_pn:seqID="47"/>
+</file>
+		<file xil_pn:name="../../../ip_cores/general-cores/modules/common/gc_big_adder.vhd" xil_pn:type="FILE_VHDL">
+			<association xil_pn:name="Implementation" xil_pn:seqID="48"/>
+</file>
+		<file xil_pn:name="../../../ip_cores/general-cores/modules/common/gc_fsm_watchdog.vhd" xil_pn:type="FILE_VHDL">
+			<association xil_pn:name="Implementation" xil_pn:seqID="49"/>
+</file>
+		<file xil_pn:name="../../../rtl/fd_ring_buffer.vhd" xil_pn:type="FILE_VHDL">
+			<association xil_pn:name="Implementation" xil_pn:seqID="50"/>
+</file>
+		<file xil_pn:name="../../../ip_cores/general-cores/modules/genrams/memory_loader_pkg.vhd" xil_pn:type="FILE_VHDL">
+			<association xil_pn:name="Implementation" xil_pn:seqID="51"/>
+</file>
+		<file xil_pn:name="../../../ip_cores/general-cores/modules/genrams/generic_shiftreg_fifo.vhd" xil_pn:type="FILE_VHDL">
+			<association xil_pn:name="Implementation" xil_pn:seqID="52"/>
+</file>
+		<file xil_pn:name="../../../ip_cores/general-cores/modules/genrams/inferred_sync_fifo.vhd" xil_pn:type="FILE_VHDL">
+			<association xil_pn:name="Implementation" xil_pn:seqID="53"/>
+</file>
+		<file xil_pn:name="../../../ip_cores/general-cores/modules/genrams/inferred_async_fifo.vhd" xil_pn:type="FILE_VHDL">
+			<association xil_pn:name="Implementation" xil_pn:seqID="54"/>
+</file>
+		<file xil_pn:name="../../../ip_cores/wr-cores/modules/fabric/wr_fabric_pkg.vhd" xil_pn:type="FILE_VHDL">
+			<association xil_pn:name="Implementation" xil_pn:seqID="55"/>
+</file>
+		<file xil_pn:name="../../../ip_cores/general-cores/modules/genrams/xilinx/generic_dpram.vhd" xil_pn:type="FILE_VHDL">
+			<association xil_pn:name="Implementation" xil_pn:seqID="56"/>
+</file>
+		<file xil_pn:name="../../../ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_sameclock.vhd" xil_pn:type="FILE_VHDL">
+			<association xil_pn:name="Implementation" xil_pn:seqID="57"/>
+</file>
+		<file xil_pn:name="../../../ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_dualclock.vhd" xil_pn:type="FILE_VHDL">
+			<association xil_pn:name="Implementation" xil_pn:seqID="58"/>
+</file>
+		<file xil_pn:name="../../../ip_cores/general-cores/modules/genrams/xilinx/generic_simple_dpram.vhd" xil_pn:type="FILE_VHDL">
+			<association xil_pn:name="Implementation" xil_pn:seqID="59"/>
+</file>
+		<file xil_pn:name="../../../ip_cores/general-cores/modules/genrams/xilinx/generic_spram.vhd" xil_pn:type="FILE_VHDL">
+			<association xil_pn:name="Implementation" xil_pn:seqID="60"/>
+</file>
+		<file xil_pn:name="../../../ip_cores/general-cores/modules/genrams/xilinx/gc_shiftreg.vhd" xil_pn:type="FILE_VHDL">
+			<association xil_pn:name="Implementation" xil_pn:seqID="61"/>
+</file>
+		<file xil_pn:name="../../../ip_cores/general-cores/modules/genrams/generic/generic_async_fifo.vhd" xil_pn:type="FILE_VHDL">
+			<association xil_pn:name="Implementation" xil_pn:seqID="62"/>
+</file>
+		<file xil_pn:name="../../../ip_cores/general-cores/modules/genrams/generic/generic_sync_fifo.vhd" xil_pn:type="FILE_VHDL">
+			<association xil_pn:name="Implementation" xil_pn:seqID="63"/>
+</file>
+		<file xil_pn:name="../../../ip_cores/general-cores/modules/wishbone/wb_async_bridge/wb_async_bridge.vhd" xil_pn:type="FILE_VHDL">
+			<association xil_pn:name="Implementation" xil_pn:seqID="64"/>
+</file>
+		<file xil_pn:name="../../../ip_cores/general-cores/modules/wishbone/wb_async_bridge/xwb_async_bridge.vhd" xil_pn:type="FILE_VHDL">
+			<association xil_pn:name="Implementation" xil_pn:seqID="65"/>
+</file>
+		<file xil_pn:name="../../../ip_cores/general-cores/modules/wishbone/wb_onewire_master/wb_onewire_master.vhd" xil_pn:type="FILE_VHDL">
+			<association xil_pn:name="Implementation" xil_pn:seqID="66"/>
+</file>
+		<file xil_pn:name="../../../ip_cores/general-cores/modules/wishbone/wb_onewire_master/xwb_onewire_master.vhd" xil_pn:type="FILE_VHDL">
+			<association xil_pn:name="Implementation" xil_pn:seqID="67"/>
+</file>
+		<file xil_pn:name="../../../ip_cores/general-cores/modules/wishbone/wb_onewire_master/sockit_owm.v" xil_pn:type="FILE_VERILOG">
+			<association xil_pn:name="Implementation" xil_pn:seqID="68"/>
+</file>
+		<file xil_pn:name="../../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/i2c_master_bit_ctrl.vhd" xil_pn:type="FILE_VHDL">
+			<association xil_pn:name="Implementation" xil_pn:seqID="69"/>
+</file>
+		<file xil_pn:name="../../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/i2c_master_byte_ctrl.vhd" xil_pn:type="FILE_VHDL">
+			<association xil_pn:name="Implementation" xil_pn:seqID="70"/>
+</file>
+		<file xil_pn:name="../../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/i2c_master_top.vhd" xil_pn:type="FILE_VHDL">
+			<association xil_pn:name="Implementation" xil_pn:seqID="71"/>
+</file>
+		<file xil_pn:name="../../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/wb_i2c_master.vhd" xil_pn:type="FILE_VHDL">
+			<association xil_pn:name="Implementation" xil_pn:seqID="72"/>
+</file>
+		<file xil_pn:name="../../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/xwb_i2c_master.vhd" xil_pn:type="FILE_VHDL">
+			<association xil_pn:name="Implementation" xil_pn:seqID="73"/>
+</file>
+		<file xil_pn:name="../../../ip_cores/general-cores/modules/wishbone/wb_bus_fanout/xwb_bus_fanout.vhd" xil_pn:type="FILE_VHDL">
+			<association xil_pn:name="Implementation" xil_pn:seqID="74"/>
+</file>
+		<file xil_pn:name="../../../ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd" xil_pn:type="FILE_VHDL">
+			<association xil_pn:name="Implementation" xil_pn:seqID="75"/>
+</file>
+		<file xil_pn:name="../../../ip_cores/general-cores/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd" xil_pn:type="FILE_VHDL">
+			<association xil_pn:name="Implementation" xil_pn:seqID="76"/>
+</file>
+		<file xil_pn:name="../../../ip_cores/general-cores/modules/wishbone/wb_gpio_port/xwb_gpio_port.vhd" xil_pn:type="FILE_VHDL">
+			<association xil_pn:name="Implementation" xil_pn:seqID="77"/>
+</file>
+		<file xil_pn:name="../../../ip_cores/general-cores/modules/wishbone/wb_simple_timer/wb_tics.vhd" xil_pn:type="FILE_VHDL">
+			<association xil_pn:name="Implementation" xil_pn:seqID="78"/>
+</file>
+		<file xil_pn:name="../../../ip_cores/general-cores/modules/wishbone/wb_simple_timer/xwb_tics.vhd" xil_pn:type="FILE_VHDL">
+			<association xil_pn:name="Implementation" xil_pn:seqID="79"/>
+</file>
+		<file xil_pn:name="../../../ip_cores/general-cores/modules/wishbone/wb_uart/uart_async_rx.vhd" xil_pn:type="FILE_VHDL">
+			<association xil_pn:name="Implementation" xil_pn:seqID="80"/>
+</file>
+		<file xil_pn:name="../../../ip_cores/general-cores/modules/wishbone/wb_uart/uart_async_tx.vhd" xil_pn:type="FILE_VHDL">
+			<association xil_pn:name="Implementation" xil_pn:seqID="81"/>
+</file>
+		<file xil_pn:name="../../../ip_cores/general-cores/modules/wishbone/wb_uart/uart_baud_gen.vhd" xil_pn:type="FILE_VHDL">
+			<association xil_pn:name="Implementation" xil_pn:seqID="82"/>
+</file>
+		<file xil_pn:name="../../../ip_cores/general-cores/modules/wishbone/wb_uart/simple_uart_pkg.vhd" xil_pn:type="FILE_VHDL">
+			<association xil_pn:name="Implementation" xil_pn:seqID="83"/>
+</file>
+		<file xil_pn:name="../../../ip_cores/general-cores/modules/wishbone/wb_uart/simple_uart_wb.vhd" xil_pn:type="FILE_VHDL">
+			<association xil_pn:name="Implementation" xil_pn:seqID="84"/>
+</file>
+		<file xil_pn:name="../../../ip_cores/general-cores/modules/wishbone/wb_uart/wb_simple_uart.vhd" xil_pn:type="FILE_VHDL">
+			<association xil_pn:name="Implementation" xil_pn:seqID="85"/>
+</file>
+		<file xil_pn:name="../../../ip_cores/general-cores/modules/wishbone/wb_uart/xwb_simple_uart.vhd" xil_pn:type="FILE_VHDL">
+			<association xil_pn:name="Implementation" xil_pn:seqID="86"/>
+</file>
+		<file xil_pn:name="../../../ip_cores/general-cores/modules/wishbone/wb_vic/vic_prio_enc.vhd" xil_pn:type="FILE_VHDL">
+			<association xil_pn:name="Implementation" xil_pn:seqID="87"/>
+</file>
+		<file xil_pn:name="../../../ip_cores/general-cores/modules/wishbone/wb_vic/wb_slave_vic.vhd" xil_pn:type="FILE_VHDL">
+			<association xil_pn:name="Implementation" xil_pn:seqID="88"/>
+</file>
+		<file xil_pn:name="../../../ip_cores/general-cores/modules/wishbone/wb_vic/wb_vic.vhd" xil_pn:type="FILE_VHDL">
+			<association xil_pn:name="Implementation" xil_pn:seqID="89"/>
+</file>
+		<file xil_pn:name="../../../ip_cores/general-cores/modules/wishbone/wb_vic/xwb_vic.vhd" xil_pn:type="FILE_VHDL">
+			<association xil_pn:name="Implementation" xil_pn:seqID="90"/>
+</file>
+		<file xil_pn:name="../../../ip_cores/general-cores/modules/wishbone/wb_spi/spi_clgen.v" xil_pn:type="FILE_VERILOG">
+			<association xil_pn:name="Implementation" xil_pn:seqID="91"/>
+</file>
+		<file xil_pn:name="../../../ip_cores/general-cores/modules/wishbone/wb_spi/spi_shift.v" xil_pn:type="FILE_VERILOG">
+			<association xil_pn:name="Implementation" xil_pn:seqID="92"/>
+</file>
+		<file xil_pn:name="../../../ip_cores/general-cores/modules/wishbone/wb_spi/spi_top.v" xil_pn:type="FILE_VERILOG">
+			<association xil_pn:name="Implementation" xil_pn:seqID="93"/>
+</file>
+		<file xil_pn:name="../../../ip_cores/general-cores/modules/wishbone/wb_spi/wb_spi.vhd" xil_pn:type="FILE_VHDL">
+			<association xil_pn:name="Implementation" xil_pn:seqID="94"/>
+</file>
+		<file xil_pn:name="../../../ip_cores/general-cores/modules/wishbone/wb_spi/xwb_spi.vhd" xil_pn:type="FILE_VHDL">
+			<association xil_pn:name="Implementation" xil_pn:seqID="95"/>
+</file>
+		<file xil_pn:name="../../../ip_cores/general-cores/modules/wishbone/wb_crossbar/sdb_rom.vhd" xil_pn:type="FILE_VHDL">
+			<association xil_pn:name="Implementation" xil_pn:seqID="96"/>
+</file>
+		<file xil_pn:name="../../../ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_crossbar.vhd" xil_pn:type="FILE_VHDL">
+			<association xil_pn:name="Implementation" xil_pn:seqID="97"/>
+</file>
+		<file xil_pn:name="../../../ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_sdb_crossbar.vhd" xil_pn:type="FILE_VHDL">
+			<association xil_pn:name="Implementation" xil_pn:seqID="98"/>
+</file>
+		<file xil_pn:name="../../../ip_cores/general-cores/modules/wishbone/wb_irq/wb_irq_pkg.vhd" xil_pn:type="FILE_VHDL">
+			<association xil_pn:name="Implementation" xil_pn:seqID="99"/>
+</file>
+		<file xil_pn:name="../../../ip_cores/general-cores/modules/wishbone/wb_irq/irqm_core.vhd" xil_pn:type="FILE_VHDL">
+			<association xil_pn:name="Implementation" xil_pn:seqID="100"/>
+</file>
+		<file xil_pn:name="../../../ip_cores/general-cores/modules/wishbone/wb_irq/wb_irq_lm32.vhd" xil_pn:type="FILE_VHDL">
+			<association xil_pn:name="Implementation" xil_pn:seqID="101"/>
+</file>
+		<file xil_pn:name="../../../ip_cores/general-cores/modules/wishbone/wb_irq/wb_irq_slave.vhd" xil_pn:type="FILE_VHDL">
+			<association xil_pn:name="Implementation" xil_pn:seqID="102"/>
+</file>
+		<file xil_pn:name="../../../ip_cores/general-cores/modules/wishbone/wb_irq/wb_irq_master.vhd" xil_pn:type="FILE_VHDL">
+			<association xil_pn:name="Implementation" xil_pn:seqID="103"/>
+</file>
+		<file xil_pn:name="../../../ip_cores/general-cores/modules/wishbone/wb_irq/wb_irq_timer.vhd" xil_pn:type="FILE_VHDL">
+			<association xil_pn:name="Implementation" xil_pn:seqID="104"/>
+</file>
+		<file xil_pn:name="../../../ip_cores/general-cores/modules/wishbone/wb_lm32/generated/xwb_lm32.vhd" xil_pn:type="FILE_VHDL">
+			<association xil_pn:name="Implementation" xil_pn:seqID="105"/>
+</file>
+		<file xil_pn:name="../../../ip_cores/general-cores/modules/wishbone/wb_lm32/generated/lm32_allprofiles.v" xil_pn:type="FILE_VERILOG">
+			<association xil_pn:name="Implementation" xil_pn:seqID="106"/>
+</file>
+		<file xil_pn:name="../../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_mc_arithmetic.v" xil_pn:type="FILE_VERILOG">
+			<association xil_pn:name="Implementation" xil_pn:seqID="107"/>
+</file>
+		<file xil_pn:name="../../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/jtag_cores.v" xil_pn:type="FILE_VERILOG">
+			<association xil_pn:name="Implementation" xil_pn:seqID="108"/>
+</file>
+		<file xil_pn:name="../../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_adder.v" xil_pn:type="FILE_VERILOG">
+			<association xil_pn:name="Implementation" xil_pn:seqID="109"/>
+</file>
+		<file xil_pn:name="../../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_addsub.v" xil_pn:type="FILE_VERILOG">
+			<association xil_pn:name="Implementation" xil_pn:seqID="110"/>
+</file>
+		<file xil_pn:name="../../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_dp_ram.vhd" xil_pn:type="FILE_VHDL">
+			<association xil_pn:name="Implementation" xil_pn:seqID="111"/>
+</file>
+		<file xil_pn:name="../../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_logic_op.v" xil_pn:type="FILE_VERILOG">
+			<association xil_pn:name="Implementation" xil_pn:seqID="112"/>
+</file>
+		<file xil_pn:name="../../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_ram.vhd" xil_pn:type="FILE_VHDL">
+			<association xil_pn:name="Implementation" xil_pn:seqID="113"/>
+</file>
+		<file xil_pn:name="../../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_shifter.v" xil_pn:type="FILE_VERILOG">
+			<association xil_pn:name="Implementation" xil_pn:seqID="114"/>
+</file>
+		<file xil_pn:name="../../../ip_cores/general-cores/modules/wishbone/wb_lm32/platform/spartan6/lm32_multiplier.v" xil_pn:type="FILE_VERILOG">
+			<association xil_pn:name="Implementation" xil_pn:seqID="115"/>
+</file>
+		<file xil_pn:name="../../../ip_cores/general-cores/modules/wishbone/wb_lm32/platform/spartan6/jtag_tap.v" xil_pn:type="FILE_VERILOG">
+			<association xil_pn:name="Implementation" xil_pn:seqID="116"/>
+</file>
+		<file xil_pn:name="../../../ip_cores/general-cores/modules/wishbone/wb_slave_adapter/wb_slave_adapter.vhd" xil_pn:type="FILE_VHDL">
+			<association xil_pn:name="Implementation" xil_pn:seqID="117"/>
+</file>
+		<file xil_pn:name="../../../ip_cores/general-cores/modules/wishbone/wb_clock_crossing/xwb_clock_crossing.vhd" xil_pn:type="FILE_VHDL">
+			<association xil_pn:name="Implementation" xil_pn:seqID="118"/>
+</file>
+		<file xil_pn:name="../../../ip_cores/general-cores/modules/wishbone/wb_dma/xwb_dma.vhd" xil_pn:type="FILE_VHDL">
+			<association xil_pn:name="Implementation" xil_pn:seqID="119"/>
+</file>
+		<file xil_pn:name="../../../ip_cores/general-cores/modules/wishbone/wb_dma/xwb_streamer.vhd" xil_pn:type="FILE_VHDL">
+			<association xil_pn:name="Implementation" xil_pn:seqID="120"/>
+</file>
+		<file xil_pn:name="../../../ip_cores/general-cores/modules/wishbone/wb_serial_lcd/wb_serial_lcd.vhd" xil_pn:type="FILE_VHDL">
+			<association xil_pn:name="Implementation" xil_pn:seqID="121"/>
+</file>
+		<file xil_pn:name="../../../ip_cores/general-cores/modules/wishbone/wb_spi_flash/wb_spi_flash.vhd" xil_pn:type="FILE_VHDL">
+			<association xil_pn:name="Implementation" xil_pn:seqID="122"/>
+</file>
+		<file xil_pn:name="../../../ip_cores/general-cores/modules/wishbone/wb_simple_pwm/simple_pwm_wbgen2_pkg.vhd" xil_pn:type="FILE_VHDL">
+			<association xil_pn:name="Implementation" xil_pn:seqID="123"/>
+</file>
+		<file xil_pn:name="../../../ip_cores/general-cores/modules/wishbone/wb_simple_pwm/simple_pwm_wb.vhd" xil_pn:type="FILE_VHDL">
+			<association xil_pn:name="Implementation" xil_pn:seqID="124"/>
+</file>
+		<file xil_pn:name="../../../ip_cores/general-cores/modules/wishbone/wb_simple_pwm/wb_simple_pwm.vhd" xil_pn:type="FILE_VHDL">
+			<association xil_pn:name="Implementation" xil_pn:seqID="125"/>
+</file>
+		<file xil_pn:name="../../../ip_cores/general-cores/modules/wishbone/wb_simple_pwm/xwb_simple_pwm.vhd" xil_pn:type="FILE_VHDL">
+			<association xil_pn:name="Implementation" xil_pn:seqID="126"/>
+</file>
+		<file xil_pn:name="../../../ip_cores/general-cores/modules/wishbone/wb_i2c_bridge/wb_i2c_bridge.vhd" xil_pn:type="FILE_VHDL">
+			<association xil_pn:name="Implementation" xil_pn:seqID="127"/>
+</file>
+		<file xil_pn:name="../../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_dpssram.vhd" xil_pn:type="FILE_VHDL">
+			<association xil_pn:name="Implementation" xil_pn:seqID="128"/>
+</file>
+		<file xil_pn:name="../../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_eic.vhd" xil_pn:type="FILE_VHDL">
+			<association xil_pn:name="Implementation" xil_pn:seqID="129"/>
+</file>
+		<file xil_pn:name="../../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_fifo_async.vhd" xil_pn:type="FILE_VHDL">
+			<association xil_pn:name="Implementation" xil_pn:seqID="130"/>
+</file>
+		<file xil_pn:name="../../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_fifo_sync.vhd" xil_pn:type="FILE_VHDL">
+			<association xil_pn:name="Implementation" xil_pn:seqID="131"/>
+</file>
+		<file xil_pn:name="../../../rtl/fd_main_wishbone_slave.vhd" xil_pn:type="FILE_VHDL">
+			<association xil_pn:name="Implementation" xil_pn:seqID="132"/>
+</file>
+		<file xil_pn:name="../../../ip_cores/general-cores/platform/xilinx/wb_xilinx_fpga_loader/xloader_registers_pkg.vhd" xil_pn:type="FILE_VHDL">
+			<association xil_pn:name="Implementation" xil_pn:seqID="133"/>
+</file>
+		<file xil_pn:name="../../../ip_cores/general-cores/platform/xilinx/wb_xilinx_fpga_loader/xwb_xilinx_fpga_loader.vhd" xil_pn:type="FILE_VHDL">
+			<association xil_pn:name="Implementation" xil_pn:seqID="134"/>
+</file>
+		<file xil_pn:name="../../../ip_cores/general-cores/platform/xilinx/wb_xilinx_fpga_loader/wb_xilinx_fpga_loader.vhd" xil_pn:type="FILE_VHDL">
+			<association xil_pn:name="Implementation" xil_pn:seqID="135"/>
+</file>
+		<file xil_pn:name="../../../ip_cores/general-cores/platform/xilinx/wb_xilinx_fpga_loader/xloader_wb.vhd" xil_pn:type="FILE_VHDL">
+			<association xil_pn:name="Implementation" xil_pn:seqID="136"/>
+</file>
+		<file xil_pn:name="../../../ip_cores/general-cores/platform/xilinx/wb_xil_multiboot/spi_master.vhd" xil_pn:type="FILE_VHDL">
+			<association xil_pn:name="Implementation" xil_pn:seqID="137"/>
+</file>
+		<file xil_pn:name="../../../ip_cores/general-cores/platform/xilinx/wb_xil_multiboot/multiboot_fsm.vhd" xil_pn:type="FILE_VHDL">
+			<association xil_pn:name="Implementation" xil_pn:seqID="138"/>
+</file>
+		<file xil_pn:name="../../../ip_cores/general-cores/platform/xilinx/wb_xil_multiboot/multiboot_regs.vhd" xil_pn:type="FILE_VHDL">
+			<association xil_pn:name="Implementation" xil_pn:seqID="139"/>
+</file>
+		<file xil_pn:name="../../../ip_cores/general-cores/platform/xilinx/wb_xil_multiboot/wb_xil_multiboot.vhd" xil_pn:type="FILE_VHDL">
+			<association xil_pn:name="Implementation" xil_pn:seqID="140"/>
+</file>
+		<file xil_pn:name="../../../ip_cores/wr-cores/modules/wr_softpll_ng/softpll_pkg.vhd" xil_pn:type="FILE_VHDL">
+			<association xil_pn:name="Implementation" xil_pn:seqID="141"/>
+</file>
+		<file xil_pn:name="../../../ip_cores/wr-cores/modules/fabric/xwb_fabric_sink.vhd" xil_pn:type="FILE_VHDL">
+			<association xil_pn:name="Implementation" xil_pn:seqID="142"/>
+</file>
+		<file xil_pn:name="../../../ip_cores/wr-cores/modules/fabric/xwb_fabric_source.vhd" xil_pn:type="FILE_VHDL">
+			<association xil_pn:name="Implementation" xil_pn:seqID="143"/>
+</file>
+		<file xil_pn:name="../../../ip_cores/wr-cores/modules/fabric/xwrf_mux.vhd" xil_pn:type="FILE_VHDL">
+			<association xil_pn:name="Implementation" xil_pn:seqID="144"/>
+</file>
+		<file xil_pn:name="../../../ip_cores/wr-cores/modules/wr_tbi_phy/dec_8b10b.vhd" xil_pn:type="FILE_VHDL">
+			<association xil_pn:name="Implementation" xil_pn:seqID="145"/>
+</file>
+		<file xil_pn:name="../../../ip_cores/wr-cores/modules/wr_tbi_phy/enc_8b10b.vhd" xil_pn:type="FILE_VHDL">
+			<association xil_pn:name="Implementation" xil_pn:seqID="146"/>
+</file>
+		<file xil_pn:name="../../../ip_cores/wr-cores/modules/wr_tbi_phy/wr_tbi_phy.vhd" xil_pn:type="FILE_VHDL">
+			<association xil_pn:name="Implementation" xil_pn:seqID="147"/>
+</file>
+		<file xil_pn:name="../../../ip_cores/wr-cores/modules/wr_tbi_phy/disparity_gen_pkg.vhd" xil_pn:type="FILE_VHDL">
+			<association xil_pn:name="Implementation" xil_pn:seqID="148"/>
+</file>
+		<file xil_pn:name="../../../ip_cores/wr-cores/modules/timing/dmtd_phase_meas.vhd" xil_pn:type="FILE_VHDL">
+			<association xil_pn:name="Implementation" xil_pn:seqID="149"/>
+</file>
+		<file xil_pn:name="../../../ip_cores/wr-cores/modules/timing/dmtd_with_deglitcher.vhd" xil_pn:type="FILE_VHDL">
+			<association xil_pn:name="Implementation" xil_pn:seqID="150"/>
+</file>
+		<file xil_pn:name="../../../ip_cores/wr-cores/modules/timing/multi_dmtd_with_deglitcher.vhd" xil_pn:type="FILE_VHDL">
+			<association xil_pn:name="Implementation" xil_pn:seqID="151"/>
+</file>
+		<file xil_pn:name="../../../ip_cores/wr-cores/modules/timing/hpll_period_detect.vhd" xil_pn:type="FILE_VHDL">
+			<association xil_pn:name="Implementation" xil_pn:seqID="152"/>
+</file>
+		<file xil_pn:name="../../../ip_cores/wr-cores/modules/timing/pulse_gen.vhd" xil_pn:type="FILE_VHDL">
+			<association xil_pn:name="Implementation" xil_pn:seqID="153"/>
+</file>
+		<file xil_pn:name="../../../ip_cores/wr-cores/modules/timing/pulse_stamper.vhd" xil_pn:type="FILE_VHDL">
+			<association xil_pn:name="Implementation" xil_pn:seqID="154"/>
+</file>
+		<file xil_pn:name="../../../ip_cores/wr-cores/modules/wr_mini_nic/minic_packet_buffer.vhd" xil_pn:type="FILE_VHDL">
+			<association xil_pn:name="Implementation" xil_pn:seqID="155"/>
+</file>
+		<file xil_pn:name="../../../ip_cores/wr-cores/modules/wr_mini_nic/minic_wbgen2_pkg.vhd" xil_pn:type="FILE_VHDL">
+			<association xil_pn:name="Implementation" xil_pn:seqID="156"/>
+</file>
+		<file xil_pn:name="../../../ip_cores/wr-cores/modules/wr_mini_nic/minic_wb_slave.vhd" xil_pn:type="FILE_VHDL">
+			<association xil_pn:name="Implementation" xil_pn:seqID="157"/>
+</file>
+		<file xil_pn:name="../../../ip_cores/wr-cores/modules/wr_mini_nic/wr_mini_nic.vhd" xil_pn:type="FILE_VHDL">
+			<association xil_pn:name="Implementation" xil_pn:seqID="158"/>
+</file>
+		<file xil_pn:name="../../../ip_cores/wr-cores/modules/wr_mini_nic/xwr_mini_nic.vhd" xil_pn:type="FILE_VHDL">
+			<association xil_pn:name="Implementation" xil_pn:seqID="159"/>
+</file>
+		<file xil_pn:name="../../../ip_cores/wr-cores/modules/wr_softpll_ng/spll_period_detect.vhd" xil_pn:type="FILE_VHDL">
+			<association xil_pn:name="Implementation" xil_pn:seqID="160"/>
+</file>
+		<file xil_pn:name="../../../ip_cores/wr-cores/modules/wr_softpll_ng/spll_bangbang_pd.vhd" xil_pn:type="FILE_VHDL">
+			<association xil_pn:name="Implementation" xil_pn:seqID="161"/>
+</file>
+		<file xil_pn:name="../../../ip_cores/wr-cores/modules/wr_softpll_ng/spll_wbgen2_pkg.vhd" xil_pn:type="FILE_VHDL">
+			<association xil_pn:name="Implementation" xil_pn:seqID="162"/>
+</file>
+		<file xil_pn:name="../../../ip_cores/wr-cores/modules/wr_endpoint/endpoint_pkg.vhd" xil_pn:type="FILE_VHDL">
+			<association xil_pn:name="Implementation" xil_pn:seqID="163"/>
+</file>
+		<file xil_pn:name="../../../ip_cores/wr-cores/modules/wr_softpll_ng/xwr_softpll_ng.vhd" xil_pn:type="FILE_VHDL">
+			<association xil_pn:name="Implementation" xil_pn:seqID="164"/>
+</file>
+		<file xil_pn:name="../../../ip_cores/wr-cores/modules/wr_softpll_ng/wr_softpll_ng.vhd" xil_pn:type="FILE_VHDL">
+			<association xil_pn:name="Implementation" xil_pn:seqID="165"/>
+</file>
+		<file xil_pn:name="../../../ip_cores/wr-cores/modules/wr_softpll_ng/spll_wb_slave.vhd" xil_pn:type="FILE_VHDL">
+			<association xil_pn:name="Implementation" xil_pn:seqID="166"/>
+</file>
+		<file xil_pn:name="../../../ip_cores/wr-cores/modules/wr_endpoint/ep_registers_pkg.vhd" xil_pn:type="FILE_VHDL">
+			<association xil_pn:name="Implementation" xil_pn:seqID="167"/>
+</file>
+		<file xil_pn:name="../../../ip_cores/wr-cores/modules/wr_endpoint/endpoint_private_pkg.vhd" xil_pn:type="FILE_VHDL">
+			<association xil_pn:name="Implementation" xil_pn:seqID="168"/>
+</file>
+		<file xil_pn:name="../../../ip_cores/wr-cores/modules/wr_endpoint/ep_tx_pcs_8bit.vhd" xil_pn:type="FILE_VHDL">
+			<association xil_pn:name="Implementation" xil_pn:seqID="169"/>
+</file>
+		<file xil_pn:name="../../../ip_cores/wr-cores/modules/wr_endpoint/ep_tx_pcs_16bit.vhd" xil_pn:type="FILE_VHDL">
+			<association xil_pn:name="Implementation" xil_pn:seqID="170"/>
+</file>
+		<file xil_pn:name="../../../ip_cores/wr-cores/modules/wr_endpoint/ep_rx_pcs_16bit.vhd" xil_pn:type="FILE_VHDL">
+			<association xil_pn:name="Implementation" xil_pn:seqID="171"/>
+</file>
+		<file xil_pn:name="../../../ip_cores/wr-cores/modules/wr_endpoint/ep_autonegotiation.vhd" xil_pn:type="FILE_VHDL">
+			<association xil_pn:name="Implementation" xil_pn:seqID="172"/>
+</file>
+		<file xil_pn:name="../../../ip_cores/wr-cores/modules/wr_endpoint/ep_pcs_tbi_mdio_wb.vhd" xil_pn:type="FILE_VHDL">
+			<association xil_pn:name="Implementation" xil_pn:seqID="173"/>
+</file>
+		<file xil_pn:name="../../../ip_cores/wr-cores/modules/wr_endpoint/ep_1000basex_pcs.vhd" xil_pn:type="FILE_VHDL">
+			<association xil_pn:name="Implementation" xil_pn:seqID="174"/>
+</file>
+		<file xil_pn:name="../../../ip_cores/wr-cores/modules/wr_endpoint/ep_crc32_pkg.vhd" xil_pn:type="FILE_VHDL">
+			<association xil_pn:name="Implementation" xil_pn:seqID="175"/>
+</file>
+		<file xil_pn:name="../../../ip_cores/wr-cores/modules/wr_endpoint/ep_rx_bypass_queue.vhd" xil_pn:type="FILE_VHDL">
+			<association xil_pn:name="Implementation" xil_pn:seqID="176"/>
+</file>
+		<file xil_pn:name="../../../ip_cores/wr-cores/modules/wr_endpoint/ep_rx_path.vhd" xil_pn:type="FILE_VHDL">
+			<association xil_pn:name="Implementation" xil_pn:seqID="177"/>
+</file>
+		<file xil_pn:name="../../../ip_cores/wr-cores/modules/wr_endpoint/ep_rx_wb_master.vhd" xil_pn:type="FILE_VHDL">
+			<association xil_pn:name="Implementation" xil_pn:seqID="178"/>
+</file>
+		<file xil_pn:name="../../../ip_cores/wr-cores/modules/wr_endpoint/ep_rx_oob_insert.vhd" xil_pn:type="FILE_VHDL">
+			<association xil_pn:name="Implementation" xil_pn:seqID="179"/>
+</file>
+		<file xil_pn:name="../../../ip_cores/wr-cores/modules/wr_endpoint/ep_rx_early_address_match.vhd" xil_pn:type="FILE_VHDL">
+			<association xil_pn:name="Implementation" xil_pn:seqID="180"/>
+</file>
+		<file xil_pn:name="../../../ip_cores/wr-cores/modules/wr_endpoint/ep_clock_alignment_fifo.vhd" xil_pn:type="FILE_VHDL">
+			<association xil_pn:name="Implementation" xil_pn:seqID="181"/>
+</file>
+		<file xil_pn:name="../../../ip_cores/wr-cores/modules/wr_endpoint/ep_tx_framer.vhd" xil_pn:type="FILE_VHDL">
+			<association xil_pn:name="Implementation" xil_pn:seqID="182"/>
+</file>
+		<file xil_pn:name="../../../ip_cores/wr-cores/modules/wr_endpoint/ep_packet_filter.vhd" xil_pn:type="FILE_VHDL">
+			<association xil_pn:name="Implementation" xil_pn:seqID="183"/>
+</file>
+		<file xil_pn:name="../../../ip_cores/wr-cores/modules/wr_endpoint/ep_rx_vlan_unit.vhd" xil_pn:type="FILE_VHDL">
+			<association xil_pn:name="Implementation" xil_pn:seqID="184"/>
+</file>
+		<file xil_pn:name="../../../ip_cores/wr-cores/modules/wr_endpoint/ep_ts_counter.vhd" xil_pn:type="FILE_VHDL">
+			<association xil_pn:name="Implementation" xil_pn:seqID="185"/>
+</file>
+		<file xil_pn:name="../../../ip_cores/wr-cores/modules/wr_endpoint/ep_rx_status_reg_insert.vhd" xil_pn:type="FILE_VHDL">
+			<association xil_pn:name="Implementation" xil_pn:seqID="186"/>
+</file>
+		<file xil_pn:name="../../../ip_cores/wr-cores/modules/wr_endpoint/ep_timestamping_unit.vhd" xil_pn:type="FILE_VHDL">
+			<association xil_pn:name="Implementation" xil_pn:seqID="187"/>
+</file>
+		<file xil_pn:name="../../../ip_cores/wr-cores/modules/wr_endpoint/ep_leds_controller.vhd" xil_pn:type="FILE_VHDL">
+			<association xil_pn:name="Implementation" xil_pn:seqID="188"/>
+</file>
+		<file xil_pn:name="../../../ip_cores/wr-cores/modules/wr_endpoint/ep_rtu_header_extract.vhd" xil_pn:type="FILE_VHDL">
+			<association xil_pn:name="Implementation" xil_pn:seqID="189"/>
+</file>
+		<file xil_pn:name="../../../ip_cores/wr-cores/modules/wr_endpoint/ep_rx_buffer.vhd" xil_pn:type="FILE_VHDL">
+			<association xil_pn:name="Implementation" xil_pn:seqID="190"/>
+</file>
+		<file xil_pn:name="../../../ip_cores/wr-cores/modules/wr_endpoint/ep_sync_detect.vhd" xil_pn:type="FILE_VHDL">
+			<association xil_pn:name="Implementation" xil_pn:seqID="191"/>
+</file>
+		<file xil_pn:name="../../../ip_cores/wr-cores/modules/wr_endpoint/ep_sync_detect_16bit.vhd" xil_pn:type="FILE_VHDL">
+			<association xil_pn:name="Implementation" xil_pn:seqID="192"/>
+</file>
+		<file xil_pn:name="../../../ip_cores/wr-cores/modules/wr_endpoint/ep_wishbone_controller.vhd" xil_pn:type="FILE_VHDL">
+			<association xil_pn:name="Implementation" xil_pn:seqID="193"/>
+</file>
+		<file xil_pn:name="../../../ip_cores/wr-cores/modules/wr_endpoint/ep_rx_pcs_8bit.vhd" xil_pn:type="FILE_VHDL">
+			<association xil_pn:name="Implementation" xil_pn:seqID="194"/>
+</file>
+		<file xil_pn:name="../../../ip_cores/wr-cores/modules/wr_endpoint/ep_rx_crc_size_check.vhd" xil_pn:type="FILE_VHDL">
+			<association xil_pn:name="Implementation" xil_pn:seqID="195"/>
+</file>
+		<file xil_pn:name="../../../ip_cores/wr-cores/modules/wrc_core/wrc_syscon_pkg.vhd" xil_pn:type="FILE_VHDL">
+			<association xil_pn:name="Implementation" xil_pn:seqID="196"/>
+</file>
+		<file xil_pn:name="../../../ip_cores/wr-cores/modules/wr_endpoint/wr_endpoint.vhd" xil_pn:type="FILE_VHDL">
+			<association xil_pn:name="Implementation" xil_pn:seqID="197"/>
+</file>
+		<file xil_pn:name="../../../ip_cores/wr-cores/modules/wr_endpoint/xwr_endpoint.vhd" xil_pn:type="FILE_VHDL">
+			<association xil_pn:name="Implementation" xil_pn:seqID="198"/>
+</file>
+		<file xil_pn:name="../../../ip_cores/wr-cores/modules/wr_pps_gen/pps_gen_wb.vhd" xil_pn:type="FILE_VHDL">
+			<association xil_pn:name="Implementation" xil_pn:seqID="199"/>
+</file>
+		<file xil_pn:name="../../../ip_cores/wr-cores/modules/wr_pps_gen/wr_pps_gen.vhd" xil_pn:type="FILE_VHDL">
+			<association xil_pn:name="Implementation" xil_pn:seqID="200"/>
+</file>
+		<file xil_pn:name="../../../ip_cores/wr-cores/modules/wr_pps_gen/xwr_pps_gen.vhd" xil_pn:type="FILE_VHDL">
+			<association xil_pn:name="Implementation" xil_pn:seqID="201"/>
+</file>
+		<file xil_pn:name="../../../ip_cores/wr-cores/modules/wr_dacs/spec_serial_dac_arb.vhd" xil_pn:type="FILE_VHDL">
+			<association xil_pn:name="Implementation" xil_pn:seqID="202"/>
+</file>
+		<file xil_pn:name="../../../ip_cores/wr-cores/modules/wr_dacs/spec_serial_dac.vhd" xil_pn:type="FILE_VHDL">
+			<association xil_pn:name="Implementation" xil_pn:seqID="203"/>
+</file>
+		<file xil_pn:name="../../../ip_cores/wr-cores/modules/wr_si57x_interface/si570_if_wbgen2_pkg.vhd" xil_pn:type="FILE_VHDL">
+			<association xil_pn:name="Implementation" xil_pn:seqID="204"/>
+</file>
+		<file xil_pn:name="../../../ip_cores/wr-cores/modules/wr_si57x_interface/si570_if_wb.vhd" xil_pn:type="FILE_VHDL">
+			<association xil_pn:name="Implementation" xil_pn:seqID="205"/>
+</file>
+		<file xil_pn:name="../../../ip_cores/wr-cores/modules/wr_si57x_interface/wr_si57x_interface.vhd" xil_pn:type="FILE_VHDL">
+			<association xil_pn:name="Implementation" xil_pn:seqID="206"/>
+</file>
+		<file xil_pn:name="../../../ip_cores/wr-cores/modules/wr_si57x_interface/xwr_si57x_interface.vhd" xil_pn:type="FILE_VHDL">
+			<association xil_pn:name="Implementation" xil_pn:seqID="207"/>
+</file>
+		<file xil_pn:name="../../../ip_cores/wr-cores/modules/wr_eca/eca_pkg.vhd" xil_pn:type="FILE_VHDL">
+			<association xil_pn:name="Implementation" xil_pn:seqID="208"/>
+</file>
+		<file xil_pn:name="../../../ip_cores/wr-cores/modules/wr_eca/eca_adder.vhd" xil_pn:type="FILE_VHDL">
+			<association xil_pn:name="Implementation" xil_pn:seqID="209"/>
+</file>
+		<file xil_pn:name="../../../ip_cores/wr-cores/modules/wr_eca/eca_channel.vhd" xil_pn:type="FILE_VHDL">
+			<association xil_pn:name="Implementation" xil_pn:seqID="210"/>
+</file>
+		<file xil_pn:name="../../../ip_cores/wr-cores/modules/wr_eca/eca_gpio_channel.vhd" xil_pn:type="FILE_VHDL">
+			<association xil_pn:name="Implementation" xil_pn:seqID="211"/>
+</file>
+		<file xil_pn:name="../../../ip_cores/wr-cores/modules/wr_eca/eca_offset.vhd" xil_pn:type="FILE_VHDL">
+			<association xil_pn:name="Implementation" xil_pn:seqID="212"/>
+</file>
+		<file xil_pn:name="../../../ip_cores/wr-cores/modules/wr_eca/eca.vhd" xil_pn:type="FILE_VHDL">
+			<association xil_pn:name="Implementation" xil_pn:seqID="213"/>
+</file>
+		<file xil_pn:name="../../../ip_cores/wr-cores/modules/wr_eca/eca_sdp.vhd" xil_pn:type="FILE_VHDL">
+			<association xil_pn:name="Implementation" xil_pn:seqID="214"/>
+</file>
+		<file xil_pn:name="../../../ip_cores/wr-cores/modules/wr_eca/eca_search.vhd" xil_pn:type="FILE_VHDL">
+			<association xil_pn:name="Implementation" xil_pn:seqID="215"/>
+</file>
+		<file xil_pn:name="../../../ip_cores/wr-cores/modules/wr_eca/eca_flags.vhd" xil_pn:type="FILE_VHDL">
+			<association xil_pn:name="Implementation" xil_pn:seqID="216"/>
+</file>
+		<file xil_pn:name="../../../ip_cores/wr-cores/modules/wr_eca/eca_queue_channel.vhd" xil_pn:type="FILE_VHDL">
+			<association xil_pn:name="Implementation" xil_pn:seqID="217"/>
+</file>
+		<file xil_pn:name="../../../ip_cores/wr-cores/modules/wr_eca/eca_walker.vhd" xil_pn:type="FILE_VHDL">
+			<association xil_pn:name="Implementation" xil_pn:seqID="218"/>
+</file>
+		<file xil_pn:name="../../../ip_cores/wr-cores/modules/wr_eca/eca_wb_channel.vhd" xil_pn:type="FILE_VHDL">
+			<association xil_pn:name="Implementation" xil_pn:seqID="219"/>
+</file>
+		<file xil_pn:name="../../../ip_cores/wr-cores/modules/wr_eca/eca_wb_event.vhd" xil_pn:type="FILE_VHDL">
+			<association xil_pn:name="Implementation" xil_pn:seqID="220"/>
+</file>
+		<file xil_pn:name="../../../ip_cores/wr-cores/modules/wr_eca/eca_wr_time.vhd" xil_pn:type="FILE_VHDL">
+			<association xil_pn:name="Implementation" xil_pn:seqID="221"/>
+</file>
+		<file xil_pn:name="../../../ip_cores/wr-cores/modules/wr_eca/wr_eca.vhd" xil_pn:type="FILE_VHDL">
+			<association xil_pn:name="Implementation" xil_pn:seqID="222"/>
+</file>
+		<file xil_pn:name="../../../ip_cores/wr-cores/modules/wr_tlu/wb_cores_pkg_gsi.vhd" xil_pn:type="FILE_VHDL">
+			<association xil_pn:name="Implementation" xil_pn:seqID="223"/>
+</file>
+		<file xil_pn:name="../../../ip_cores/wr-cores/modules/wr_tlu/wb_timestamp_latch.vhd" xil_pn:type="FILE_VHDL">
+			<association xil_pn:name="Implementation" xil_pn:seqID="224"/>
+</file>
+		<file xil_pn:name="../../../ip_cores/wr-cores/modules/wrc_core/wrcore_pkg.vhd" xil_pn:type="FILE_VHDL">
+			<association xil_pn:name="Implementation" xil_pn:seqID="225"/>
+</file>
+		<file xil_pn:name="../../../ip_cores/wr-cores/modules/wrc_core/wr_core.vhd" xil_pn:type="FILE_VHDL">
+			<association xil_pn:name="Implementation" xil_pn:seqID="226"/>
+</file>
+		<file xil_pn:name="../../../ip_cores/wr-cores/modules/wrc_core/wrc_dpram.vhd" xil_pn:type="FILE_VHDL">
+			<association xil_pn:name="Implementation" xil_pn:seqID="227"/>
+</file>
+		<file xil_pn:name="../../../ip_cores/wr-cores/platform/xilinx/wr_xilinx_pkg.vhd" xil_pn:type="FILE_VHDL">
+			<association xil_pn:name="Implementation" xil_pn:seqID="228"/>
+</file>
+		<file xil_pn:name="../../../ip_cores/wr-cores/modules/wrc_core/wrc_periph.vhd" xil_pn:type="FILE_VHDL">
+			<association xil_pn:name="Implementation" xil_pn:seqID="229"/>
+</file>
+		<file xil_pn:name="../../../ip_cores/wr-cores/modules/wrc_core/wb_reset.vhd" xil_pn:type="FILE_VHDL">
+			<association xil_pn:name="Implementation" xil_pn:seqID="230"/>
+</file>
+		<file xil_pn:name="../../../ip_cores/wr-cores/modules/wrc_core/wrc_syscon_wb.vhd" xil_pn:type="FILE_VHDL">
+			<association xil_pn:name="Implementation" xil_pn:seqID="231"/>
+</file>
+		<file xil_pn:name="../../../ip_cores/wr-cores/modules/wrc_core/xwr_core.vhd" xil_pn:type="FILE_VHDL">
+			<association xil_pn:name="Implementation" xil_pn:seqID="232"/>
+</file>
+		<file xil_pn:name="../../../ip_cores/wr-cores/modules/wrc_core/xwr_syscon_wb.vhd" xil_pn:type="FILE_VHDL">
+			<association xil_pn:name="Implementation" xil_pn:seqID="233"/>
+</file>
+		<file xil_pn:name="../../../top/svec/wr/svec_top.vhd" xil_pn:type="FILE_VHDL">
+			<association xil_pn:name="Implementation" xil_pn:seqID="234"/>
+</file>
+		<file xil_pn:name="../../../ip_cores/wr-cores/platform/xilinx/wr_gtp_phy/gtp_bitslide.vhd" xil_pn:type="FILE_VHDL">
+			<association xil_pn:name="Implementation" xil_pn:seqID="235"/>
+</file>
+		<file xil_pn:name="../../../ip_cores/wr-cores/platform/xilinx/wr_gtp_phy/gtp_phase_align.vhd" xil_pn:type="FILE_VHDL">
+			<association xil_pn:name="Implementation" xil_pn:seqID="236"/>
+</file>
+		<file xil_pn:name="../../../ip_cores/wr-cores/platform/xilinx/wr_gtp_phy/gtp_phase_align_virtex6.vhd" xil_pn:type="FILE_VHDL">
+			<association xil_pn:name="Implementation" xil_pn:seqID="237"/>
+</file>
+		<file xil_pn:name="../../../ip_cores/wr-cores/platform/xilinx/wr_gtp_phy/gtx_reset.vhd" xil_pn:type="FILE_VHDL">
+			<association xil_pn:name="Implementation" xil_pn:seqID="238"/>
+</file>
+		<file xil_pn:name="../../../ip_cores/wr-cores/platform/xilinx/wr_gtp_phy/whiterabbitgtx_wrapper_gtx.vhd" xil_pn:type="FILE_VHDL">
+			<association xil_pn:name="Implementation" xil_pn:seqID="239"/>
+</file>
+		<file xil_pn:name="../../../ip_cores/wr-cores/platform/xilinx/wr_gtp_phy/whiterabbitgtp_wrapper_tile.vhd" xil_pn:type="FILE_VHDL">
+			<association xil_pn:name="Implementation" xil_pn:seqID="240"/>
+</file>
+		<file xil_pn:name="../../../ip_cores/wr-cores/platform/xilinx/wr_gtp_phy/wr_gtp_phy_spartan6.vhd" xil_pn:type="FILE_VHDL">
+			<association xil_pn:name="Implementation" xil_pn:seqID="241"/>
+</file>
+		<file xil_pn:name="../../../ip_cores/wr-cores/platform/xilinx/wr_gtp_phy/wr_gtx_phy_virtex6.vhd" xil_pn:type="FILE_VHDL">
+			<association xil_pn:name="Implementation" xil_pn:seqID="242"/>
+</file>
+		<file xil_pn:name="../../../ip_cores/vme64x-core/hdl/vme64x-core/rtl/vme64x_pack.vhd" xil_pn:type="FILE_VHDL">
+			<association xil_pn:name="Implementation" xil_pn:seqID="243"/>
+</file>
+		<file xil_pn:name="../../../ip_cores/vme64x-core/hdl/vme64x-core/rtl/xvme64x_core_pkg.vhd" xil_pn:type="FILE_VHDL">
+			<association xil_pn:name="Implementation" xil_pn:seqID="244"/>
+</file>
+		<file xil_pn:name="../../../ip_cores/vme64x-core/hdl/vme64x-core/rtl/VME_CR_pack.vhd" xil_pn:type="FILE_VHDL">
+			<association xil_pn:name="Implementation" xil_pn:seqID="245"/>
+</file>
+		<file xil_pn:name="../../../ip_cores/vme64x-core/hdl/vme64x-core/rtl/xvme64x_core.vhd" xil_pn:type="FILE_VHDL">
+			<association xil_pn:name="Implementation" xil_pn:seqID="246"/>
+</file>
+		<file xil_pn:name="../../../ip_cores/vme64x-core/hdl/vme64x-core/rtl/VME_Access_Decode.vhd" xil_pn:type="FILE_VHDL">
+			<association xil_pn:name="Implementation" xil_pn:seqID="247"/>
+</file>
+		<file xil_pn:name="../../../ip_cores/vme64x-core/hdl/vme64x-core/rtl/VME_Am_Match.vhd" xil_pn:type="FILE_VHDL">
+			<association xil_pn:name="Implementation" xil_pn:seqID="248"/>
+</file>
+		<file xil_pn:name="../../../ip_cores/vme64x-core/hdl/vme64x-core/rtl/VME_bus.vhd" xil_pn:type="FILE_VHDL">
+			<association xil_pn:name="Implementation" xil_pn:seqID="249"/>
+</file>
+		<file xil_pn:name="../../../ip_cores/vme64x-core/hdl/vme64x-core/rtl/VME_CSR_pack.vhd" xil_pn:type="FILE_VHDL">
+			<association xil_pn:name="Implementation" xil_pn:seqID="250"/>
+</file>
+		<file xil_pn:name="../../../ip_cores/vme64x-core/hdl/vme64x-core/rtl/VME64xCore_Top.vhd" xil_pn:type="FILE_VHDL">
+			<association xil_pn:name="Implementation" xil_pn:seqID="251"/>
+</file>
+		<file xil_pn:name="../../../ip_cores/vme64x-core/hdl/vme64x-core/rtl/VME_CR_CSR_Space.vhd" xil_pn:type="FILE_VHDL">
+			<association xil_pn:name="Implementation" xil_pn:seqID="252"/>
+</file>
+		<file xil_pn:name="../../../ip_cores/vme64x-core/hdl/vme64x-core/rtl/VME_CRAM.vhd" xil_pn:type="FILE_VHDL">
+			<association xil_pn:name="Implementation" xil_pn:seqID="253"/>
+</file>
+		<file xil_pn:name="../../../ip_cores/vme64x-core/hdl/vme64x-core/rtl/VME_Funct_Match.vhd" xil_pn:type="FILE_VHDL">
+			<association xil_pn:name="Implementation" xil_pn:seqID="254"/>
+</file>
+		<file xil_pn:name="../../../ip_cores/vme64x-core/hdl/vme64x-core/rtl/VME_Init.vhd" xil_pn:type="FILE_VHDL">
+			<association xil_pn:name="Implementation" xil_pn:seqID="255"/>
+</file>
+		<file xil_pn:name="../../../ip_cores/vme64x-core/hdl/vme64x-core/rtl/VME_IRQ_Controller.vhd" xil_pn:type="FILE_VHDL">
+			<association xil_pn:name="Implementation" xil_pn:seqID="256"/>
+</file>
+		<file xil_pn:name="../../../ip_cores/vme64x-core/hdl/vme64x-core/rtl/VME_SharedComps.vhd" xil_pn:type="FILE_VHDL">
+			<association xil_pn:name="Implementation" xil_pn:seqID="257"/>
+</file>
+		<file xil_pn:name="../../../ip_cores/vme64x-core/hdl/vme64x-core/rtl/VME_swapper.vhd" xil_pn:type="FILE_VHDL">
+			<association xil_pn:name="Implementation" xil_pn:seqID="258"/>
+</file>
+		<file xil_pn:name="../../../ip_cores/vme64x-core/hdl/vme64x-core/rtl/VME_Wb_master.vhd" xil_pn:type="FILE_VHDL">
+			<association xil_pn:name="Implementation" xil_pn:seqID="259"/>
+</file>
+</files>
+	<bindings/>
+	<version xil_pn:ise_version="13.3" xil_pn:schema_version="2"/>
 </project>
-- 
2.18.1