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FMC DEL 1ns 4cha
Commit d27a3e3b authored by Tomasz Wlostowski's avatar Tomasz Wlostowski
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Merge branch 'master' of ohwr.org:fmc-projects/fmc-delay-1ns-8cha

parents b4495e8a 1a9fad9f
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Showing with 2126 additions and 16528 deletions
hdl/include/regs/fd_main_regs.vh
View file @ d27a3e3b
......@@ -62,22 +62,16 @@
`define FD_CALR_CAL_DMTD 32'h00000004
`define FD_CALR_PSEL_OFFSET 3
`define FD_CALR_PSEL 32'h00000078
`define FD_CALR_DMTD_FBSEL_OFFSET 7
`define FD_CALR_DMTD_FBSEL 32'h00000080
`define FD_CALR_DMTD_TAG_OFFSET 8
`define FD_CALR_DMTD_TAG 32'h7fffff00
`define FD_CALR_DMTD_TAG_RDY_OFFSET 31
`define FD_CALR_DMTD_TAG_RDY 32'h80000000
`define ADDR_FD_SPLLR 8'h28
`define FD_SPLLR_TAG_OFFSET 0
`define FD_SPLLR_TAG 32'h000fffff
`define FD_SPLLR_TAG_RDY_OFFSET 20
`define FD_SPLLR_TAG_RDY 32'h00100000
`define FD_SPLLR_MODE_OFFSET 21
`define FD_SPLLR_MODE 32'h00200000
`define ADDR_FD_SDACR 8'h2c
`define FD_SDACR_DAC_VAL_OFFSET 0
`define FD_SDACR_DAC_VAL 32'h0000ffff
`define ADDR_FD_DMTR_IN 8'h28
`define FD_DMTR_IN_TAG_OFFSET 0
`define FD_DMTR_IN_TAG 32'h7fffffff
`define FD_DMTR_IN_RDY_OFFSET 31
`define FD_DMTR_IN_RDY 32'h80000000
`define ADDR_FD_DMTR_OUT 8'h2c
`define FD_DMTR_OUT_TAG_OFFSET 0
`define FD_DMTR_OUT_TAG 32'h7fffffff
`define FD_DMTR_OUT_RDY_OFFSET 31
`define FD_DMTR_OUT_RDY 32'h80000000
`define ADDR_FD_ADSFR 8'h30
`define ADDR_FD_ATMCR 8'h34
`define FD_ATMCR_C_THR_OFFSET 0
......@@ -125,6 +119,8 @@
`define FD_TSBCR_EMPTY 32'h00000200
`define FD_TSBCR_COUNT_OFFSET 10
`define FD_TSBCR_COUNT 32'h003ffc00
`define FD_TSBCR_RAW_OFFSET 22
`define FD_TSBCR_RAW 32'h00400000
`define ADDR_FD_TSBIR 8'h54
`define FD_TSBIR_TIMEOUT_OFFSET 0
`define FD_TSBIR_TIMEOUT 32'h000003ff
......@@ -155,6 +151,10 @@
`define ADDR_FD_TDER2 8'h70
`define FD_TDER2_PELT_DRIVE_OFFSET 0
`define FD_TDER2_PELT_DRIVE 32'hffffffff
`define ADDR_FD_TSBR_DEBUG 8'h74
`define ADDR_FD_TSBR_ADVANCE 8'h78
`define FD_TSBR_ADVANCE_ADV_OFFSET 0
`define FD_TSBR_ADVANCE_ADV 32'h00000001
`define ADDR_FD_EIC_IDR 8'h80
`define FD_EIC_IDR_TS_BUF_NOTEMPTY_OFFSET 0
`define FD_EIC_IDR_TS_BUF_NOTEMPTY 32'h00000001
......
hdl/rtl/Manifest.py
View file @ d27a3e3b
......@@ -16,8 +16,7 @@ files = ["fd_acam_timestamper.vhd",
"fd_channel_wbgen2_pkg.vhd",
"fd_main_wbgen2_pkg.vhd",
"fd_dmtd_insertion_calibrator.vhd",
"timing/fd_dmtd_with_deglitcher.vhd",
"timing/fd_hpll_period_detect.vhd"
"fd_dmtd_with_deglitcher.vhd"
];
fetchto = "../ip_cores"
......
hdl/rtl/doc/fd_channel_regs.html
View file @ d27a3e3b
......@@ -470,6 +470,23 @@ fd_channel_dcr_no_fine_o
wb_ack_o
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
fd_channel_dcr_force_hi_o
</td>
<td class="td_arrow_right">
&rarr;
</td>
</tr>
<tr>
<td class="td_arrow_left">
&larr;
</td>
<td class="td_pblock_left">
wb_stall_o
</td>
<td class="td_sym_center">
&nbsp;
</td>
<td class="td_pblock_right">
......@@ -481,10 +498,10 @@ wb_ack_o
</tr>
<tr>
<td class="td_arrow_left">
&larr;
</td>
<td class="td_pblock_left">
wb_stall_o
</td>
<td class="td_sym_center">
......@@ -1338,8 +1355,8 @@ DCR
<td class="td_unused">
-
</td>
<td class="td_unused">
-
<td style="border: solid 1px black;" colspan=1 class="td_field">
FORCE_HI
</td>
</tr>
</table>
......@@ -1430,6 +1447,10 @@ FORCE_DLY
NO_FINE
</b>[<i>read/write</i>]: Disable Fine Part update
<br>write 1: disables updating of the fine part of the pulse delay to allow for producing faster signals (i.e. pulse width/spacing < 200 ns), at the cost of less accurate width/spacing control (multiple of 4 ms). <br>write 0: normal operation. Pulse width/spacing must be at least 200 ns.
<li><b>
FORCE_HI
</b>[<i>read/write</i>]: Force Output High
<br>write 1: Forces constant 1 on the output when the channel is disabled<br> write 0: Forces constant 0 on the output when the channel is disabled<br> Used for testing/calibration purposes.
</ul>
<a name="FRR"></a>
<h3><a name="sect_3_2">3.2. Fine Range Register</a></h3>
......
hdl/rtl/doc/fd_main_regs.html
View file @ d27a3e3b
This diff is collapsed.
hdl/rtl/fd_channel_wbgen2_pkg.vhd
View file @ d27a3e3b
......@@ -3,7 +3,7 @@
---------------------------------------------------------------------------------------
-- File : fd_channel_wbgen2_pkg.vhd
-- Author : auto-generated by wbgen2 from fd_channel_wishbone_slave.wb
-- Created : Wed Apr 11 11:05:22 2012
-- Created : Mon Jun 4 13:42:20 2012
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE fd_channel_wishbone_slave.wb
......@@ -38,6 +38,7 @@ package fd_channel_wbgen2_pkg is
dcr_update_o : std_logic;
dcr_force_dly_o : std_logic;
dcr_no_fine_o : std_logic;
dcr_force_hi_o : std_logic;
frr_o : std_logic_vector(9 downto 0);
u_starth_o : std_logic_vector(7 downto 0);
u_startl_o : std_logic_vector(31 downto 0);
......@@ -61,6 +62,7 @@ package fd_channel_wbgen2_pkg is
dcr_update_o => '0',
dcr_force_dly_o => '0',
dcr_no_fine_o => '0',
dcr_force_hi_o => '0',
frr_o => (others => '0'),
u_starth_o => (others => '0'),
u_startl_o => (others => '0'),
......
hdl/rtl/fd_channel_wishbone_slave.vhd
View file @ d27a3e3b
......@@ -3,7 +3,7 @@
---------------------------------------------------------------------------------------
-- File : fd_channel_wishbone_slave.vhd
-- Author : auto-generated by wbgen2 from fd_channel_wishbone_slave.wb
-- Created : Wed Apr 11 11:05:22 2012
-- Created : Mon Jun 4 13:42:20 2012
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE fd_channel_wishbone_slave.wb
......@@ -62,6 +62,7 @@ signal fd_channel_dcr_force_dly_sync0 : std_logic ;
signal fd_channel_dcr_force_dly_sync1 : std_logic ;
signal fd_channel_dcr_force_dly_sync2 : std_logic ;
signal fd_channel_dcr_no_fine_int : std_logic ;
signal fd_channel_dcr_force_hi_int : std_logic ;
signal fd_channel_frr_int : std_logic_vector(9 downto 0);
signal fd_channel_u_starth_int : std_logic_vector(7 downto 0);
signal fd_channel_u_startl_int : std_logic_vector(31 downto 0);
......@@ -112,6 +113,7 @@ begin
fd_channel_dcr_force_dly_int <= '0';
fd_channel_dcr_force_dly_int_delay <= '0';
fd_channel_dcr_no_fine_int <= '0';
fd_channel_dcr_force_hi_int <= '0';
fd_channel_frr_int <= "0000000000";
fd_channel_u_starth_int <= "00000000";
fd_channel_u_startl_int <= "00000000000000000000000000000000";
......@@ -155,6 +157,7 @@ begin
fd_channel_dcr_force_dly_int <= wrdata_reg(6);
fd_channel_dcr_force_dly_int_delay <= wrdata_reg(6);
fd_channel_dcr_no_fine_int <= wrdata_reg(7);
fd_channel_dcr_force_hi_int <= wrdata_reg(8);
end if;
rddata_reg(0) <= fd_channel_dcr_enable_int;
rddata_reg(1) <= fd_channel_dcr_mode_int;
......@@ -164,7 +167,7 @@ begin
rddata_reg(5) <= fd_channel_dcr_upd_done_sync1;
rddata_reg(6) <= 'X';
rddata_reg(7) <= fd_channel_dcr_no_fine_int;
rddata_reg(8) <= 'X';
rddata_reg(8) <= fd_channel_dcr_force_hi_int;
rddata_reg(9) <= 'X';
rddata_reg(10) <= 'X';
rddata_reg(11) <= 'X';
......@@ -580,6 +583,8 @@ begin
-- Disable Fine Part update
regs_o.dcr_no_fine_o <= fd_channel_dcr_no_fine_int;
-- Force Output High
regs_o.dcr_force_hi_o <= fd_channel_dcr_force_hi_int;
-- Fine Range
regs_o.frr_o <= fd_channel_frr_int;
-- TAI seconds (MSB)
......
hdl/rtl/fd_channel_wishbone_slave.wb
View file @ d27a3e3b
......@@ -135,6 +135,19 @@ write 0: normal operation. Pulse width/spacing must be at least 200 ns.";
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
name = "Force Output High";
prefix = "FORCE_HI";
description = "write 1: Forces constant 1 on the output when the channel is disabled\
write 0: Forces constant 0 on the output when the channel is disabled\
Used for testing/calibration purposes.";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
......
hdl/rtl/fd_delay_channel_driver.vhd
View file @ d27a3e3b
......@@ -6,7 +6,7 @@
-- Author : Tomasz Wlostowski
-- Company : CERN
-- Created : 2011-08-24
-- Last update: 2012-02-29
-- Last update: 2012-06-01
-- Platform : FPGA-generic
-- Standard : VHDL'93
-------------------------------------------------------------------------------
......@@ -481,8 +481,8 @@ begin
delay_load_o <= '0';
first_pulse <= '1';
first_pulse_till_hit <= '0';
delay_pulse1_o <= '0';
delay_pulse0_o <= '0';
delay_pulse1_o <= regs_in.dcr_force_hi_o;
delay_pulse0_o <= regs_in.dcr_force_hi_o;
delay_idle_o <= '1';
......
hdl/rtl/fd_dmtd_insertion_calibrator.vhd
View file @ d27a3e3b
This diff is collapsed.
hdl/rtl/fd_dmtd_with_deglitcher.vhd 0 → 100644
View file @ d27a3e3b
-------------------------------------------------------------------------------
-- Title : Digital DMTD Edge Tagger
-- Project : White Rabbit
-------------------------------------------------------------------------------
-- File : fd_dmtd_with_deglitcher.vhd
-- Author : Tomasz Wlostowski
-- Company : CERN BE-Co-HT
-- Created : 2010-02-25
-- Last update: 2012-06-04
-- Platform : FPGA-generic
-- Standard : VHDL '93
-------------------------------------------------------------------------------
-- Description: Single-channel DDMTD phase tagger with integrated bit-median
-- deglitcher. Contains a DDMTD detector, which output signal is deglitched and
-- tagged with a counter running in DMTD offset clock domain. Phase tags are
-- generated for each rising edge in DDMTD output with an internal counter
-------------------------------------------------------------------------------
--
-- Copyright (c) 2009 - 2011 CERN
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
-- Public License as published by the Free Software Foundation;
-- either version 2.1 of the License, or (at your option) any
-- later version.
--
-- This source is distributed in the hope that it will be
-- useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
-- PURPOSE. See the GNU Lesser General Public License for more
-- details.
--
-- You should have received a copy of the GNU Lesser General
-- Public License along with this source; if not, download it
-- from http://www.gnu.org/licenses/lgpl-2.1.html
--
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2009-01-24 1.0 twlostow Created
-- 2011-18-04 1.1 twlostow Bit-median type deglitcher, comments
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.gencores_pkg.all;
entity fd_dmtd_with_deglitcher is
generic(
-- Size of the phase tag counter. Must be big enough to cover at least one
-- full period of the DDMTD detector output. Given the frequencies of clk_in_i
-- and clk_dmtd_i are respectively f_in an f_dmtd, it can be calculated with
-- the following formula:
g_tag_bits : integer;
g_deglitch_threshold : integer);
port(
clk_sys_i : in std_logic;
clk_dmtd_i : in std_logic;
rst_n_i : in std_logic;
dmtd_fb_n_i : in std_logic;
tag_o : out std_logic_vector(g_tag_bits-1 downto 0);
tag_valid_o : out std_logic);
end fd_dmtd_with_deglitcher;
architecture rtl of fd_dmtd_with_deglitcher is
-- DMTD Deglitcher stuff
type t_state is (WAIT_STABLE_0, WAIT_EDGE, GOT_EDGE);
signal state : t_state;
signal stab_cntr : unsigned(g_tag_bits-1 downto 0);
signal free_cntr : unsigned(g_tag_bits-1 downto 0);
signal new_edge_sreg : std_logic_vector(5 downto 0);
signal new_edge_p : std_logic;
signal tag_int : unsigned(g_tag_bits-1 downto 0);
signal rst_n_dmtd : std_logic;
signal dmtd_fb_synced : std_logic;
begin -- rtl
U_DMTD_Reset : gc_sync_ffs
port map (
clk_i => clk_dmtd_i,
rst_n_i => '1',
data_i => rst_n_i,
synced_o => rst_n_dmtd);
U_Sync_in : gc_sync_ffs
port map (
clk_i => clk_dmtd_i,
rst_n_i => '1',
data_i => dmtd_fb_n_i,
synced_o => dmtd_fb_synced);
-- just a copy from dmtd_with_deglitcher.vhd
p_deglitch : process (clk_dmtd_i)
begin -- process deglitch
if rising_edge(clk_dmtd_i) then -- rising clock edge
if (rst_n_dmtd = '0') then -- synchronous reset (active low)
stab_cntr <= (others => '0');
state <= WAIT_STABLE_0;
free_cntr <= (others => '0');
new_edge_sreg <= (others => '0');
else
free_cntr <= free_cntr + 1;
case state is
when WAIT_STABLE_0 => -- out-of-sync
new_edge_sreg <= '0' & new_edge_sreg(new_edge_sreg'length-1 downto 1);
if dmtd_fb_synced /= '0' then
stab_cntr <= (others => '0');
else
stab_cntr <= stab_cntr + 1;
end if;
-- DMTD output stable counter hit the LOW level threshold?
if stab_cntr = g_deglitch_threshold then
state <= WAIT_EDGE;
end if;
when WAIT_EDGE =>
if (dmtd_fb_synced /= '0') then -- got a glitch?
state <= GOT_EDGE;
tag_int <= free_cntr;
stab_cntr <= (others => '0');
end if;
when GOT_EDGE =>
if (dmtd_fb_synced = '0') then
tag_int <= tag_int + 1;
end if;
if stab_cntr = g_deglitch_threshold then
state <= WAIT_STABLE_0;
--tag_int <= std_logic_vector(tag_int);
new_edge_sreg <= (others => '1');
stab_cntr <= (others => '0');
elsif (dmtd_fb_synced = '0') then
stab_cntr <= (others => '0');
else
stab_cntr <= stab_cntr + 1;
end if;
end case;
end if;
end if;
end process p_deglitch;
U_sync_tag_strobe : gc_sync_ffs
port map (
clk_i => clk_sys_i,
rst_n_i => rst_n_i,
data_i => new_edge_sreg(0),
synced_o => open,
npulse_o => open,
ppulse_o => tag_valid_o);
tag_o <= std_logic_vector(tag_int);
end rtl;
hdl/rtl/fd_main_wbgen2_pkg.vhd
View file @ d27a3e3b
......@@ -3,7 +3,7 @@
---------------------------------------------------------------------------------------
-- File : fd_main_wbgen2_pkg.vhd
-- Author : auto-generated by wbgen2 from fd_main_wishbone_slave.wb
-- Created : Mon May 21 20:09:49 2012
-- Created : Mon Jun 4 13:42:20 2012
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE fd_main_wishbone_slave.wb
......@@ -33,10 +33,10 @@ package fd_main_wbgen2_pkg is
tm_cycles_i : std_logic_vector(27 downto 0);
tdr_i : std_logic_vector(27 downto 0);
tdcsr_empty_i : std_logic;
calr_dmtd_tag_i : std_logic_vector(22 downto 0);
calr_dmtd_tag_rdy_i : std_logic;
spllr_tag_i : std_logic_vector(19 downto 0);
spllr_tag_rdy_i : std_logic;
dmtr_in_tag_i : std_logic_vector(30 downto 0);
dmtr_in_rdy_i : std_logic;
dmtr_out_tag_i : std_logic_vector(30 downto 0);
dmtr_out_rdy_i : std_logic;
iecraw_i : std_logic_vector(31 downto 0);
iectag_i : std_logic_vector(31 downto 0);
iepd_pdelay_i : std_logic_vector(7 downto 0);
......@@ -71,10 +71,10 @@ package fd_main_wbgen2_pkg is
tm_cycles_i => (others => '0'),
tdr_i => (others => '0'),
tdcsr_empty_i => '0',
calr_dmtd_tag_i => (others => '0'),
calr_dmtd_tag_rdy_i => '0',
spllr_tag_i => (others => '0'),
spllr_tag_rdy_i => '0',
dmtr_in_tag_i => (others => '0'),
dmtr_in_rdy_i => '0',
dmtr_out_tag_i => (others => '0'),
dmtr_out_rdy_i => '0',
iecraw_i => (others => '0'),
iectag_i => (others => '0'),
iepd_pdelay_i => (others => '0'),
......@@ -129,10 +129,6 @@ package fd_main_wbgen2_pkg is
calr_cal_pps_o : std_logic;
calr_cal_dmtd_o : std_logic;
calr_psel_o : std_logic_vector(3 downto 0);
calr_dmtd_fbsel_o : std_logic;
spllr_mode_o : std_logic;
sdacr_dac_val_o : std_logic_vector(15 downto 0);
sdacr_dac_val_wr_o : std_logic;
adsfr_o : std_logic_vector(17 downto 0);
atmcr_c_thr_o : std_logic_vector(3 downto 0);
atmcr_f_thr_o : std_logic_vector(22 downto 0);
......@@ -189,10 +185,6 @@ package fd_main_wbgen2_pkg is
calr_cal_pps_o => '0',
calr_cal_dmtd_o => '0',
calr_psel_o => (others => '0'),
calr_dmtd_fbsel_o => '0',
spllr_mode_o => '0',
sdacr_dac_val_o => (others => '0'),
sdacr_dac_val_wr_o => '0',
adsfr_o => (others => '0'),
atmcr_c_thr_o => (others => '0'),
atmcr_f_thr_o => (others => '0'),
......@@ -258,10 +250,10 @@ tmp.tm_secl_i := f_x_to_zero(left.tm_secl_i) or f_x_to_zero(right.tm_secl_i);
tmp.tm_cycles_i := f_x_to_zero(left.tm_cycles_i) or f_x_to_zero(right.tm_cycles_i);
tmp.tdr_i := f_x_to_zero(left.tdr_i) or f_x_to_zero(right.tdr_i);
tmp.tdcsr_empty_i := f_x_to_zero(left.tdcsr_empty_i) or f_x_to_zero(right.tdcsr_empty_i);
tmp.calr_dmtd_tag_i := f_x_to_zero(left.calr_dmtd_tag_i) or f_x_to_zero(right.calr_dmtd_tag_i);
tmp.calr_dmtd_tag_rdy_i := f_x_to_zero(left.calr_dmtd_tag_rdy_i) or f_x_to_zero(right.calr_dmtd_tag_rdy_i);
tmp.spllr_tag_i := f_x_to_zero(left.spllr_tag_i) or f_x_to_zero(right.spllr_tag_i);
tmp.spllr_tag_rdy_i := f_x_to_zero(left.spllr_tag_rdy_i) or f_x_to_zero(right.spllr_tag_rdy_i);
tmp.dmtr_in_tag_i := f_x_to_zero(left.dmtr_in_tag_i) or f_x_to_zero(right.dmtr_in_tag_i);
tmp.dmtr_in_rdy_i := f_x_to_zero(left.dmtr_in_rdy_i) or f_x_to_zero(right.dmtr_in_rdy_i);
tmp.dmtr_out_tag_i := f_x_to_zero(left.dmtr_out_tag_i) or f_x_to_zero(right.dmtr_out_tag_i);
tmp.dmtr_out_rdy_i := f_x_to_zero(left.dmtr_out_rdy_i) or f_x_to_zero(right.dmtr_out_rdy_i);
tmp.iecraw_i := f_x_to_zero(left.iecraw_i) or f_x_to_zero(right.iecraw_i);
tmp.iectag_i := f_x_to_zero(left.iectag_i) or f_x_to_zero(right.iectag_i);
tmp.iepd_pdelay_i := f_x_to_zero(left.iepd_pdelay_i) or f_x_to_zero(right.iepd_pdelay_i);
......
hdl/rtl/fd_main_wishbone_slave.vhd
View file @ d27a3e3b
......@@ -3,7 +3,7 @@
---------------------------------------------------------------------------------------
-- File : fd_main_wishbone_slave.vhd
-- Author : auto-generated by wbgen2 from fd_main_wishbone_slave.wb
-- Created : Mon May 21 20:09:49 2012
-- Created : Mon Jun 4 13:42:20 2012
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE fd_main_wishbone_slave.wb
......@@ -34,8 +34,8 @@ entity fd_main_wb_slave is
wb_int_o : out std_logic;
clk_ref_i : in std_logic;
tcr_rd_ack_o : out std_logic;
calr_rd_ack_o : out std_logic;
spllr_rd_ack_o : out std_logic;
dmtr_in_rd_ack_o : out std_logic;
dmtr_out_rd_ack_o : out std_logic;
tsbcr_read_ack_o : out std_logic;
fid_read_ack_o : out std_logic;
irq_ts_buf_notempty_i : in std_logic;
......@@ -155,8 +155,6 @@ signal fd_main_calr_psel_swb_delay : std_logic ;
signal fd_main_calr_psel_swb_s0 : std_logic ;
signal fd_main_calr_psel_swb_s1 : std_logic ;
signal fd_main_calr_psel_swb_s2 : std_logic ;
signal fd_main_calr_dmtd_fbsel_int : std_logic ;
signal fd_main_spllr_mode_int : std_logic ;
signal fd_main_adsfr_int : std_logic_vector(17 downto 0);
signal fd_main_adsfr_swb : std_logic ;
signal fd_main_adsfr_swb_delay : std_logic ;
......@@ -331,11 +329,8 @@ begin
fd_main_calr_psel_int <= "0000";
fd_main_calr_psel_swb <= '0';
fd_main_calr_psel_swb_delay <= '0';
fd_main_calr_dmtd_fbsel_int <= '0';
calr_rd_ack_o <= '0';
spllr_rd_ack_o <= '0';
fd_main_spllr_mode_int <= '0';
regs_o.sdacr_dac_val_wr_o <= '0';
dmtr_in_rd_ack_o <= '0';
dmtr_out_rd_ack_o <= '0';
fd_main_adsfr_int <= "000000000000000000";
fd_main_adsfr_swb <= '0';
fd_main_adsfr_swb_delay <= '0';
......@@ -397,9 +392,8 @@ begin
regs_o.rstr_rst_core_wr_o <= '0';
regs_o.rstr_lock_wr_o <= '0';
tcr_rd_ack_o <= '0';
calr_rd_ack_o <= '0';
spllr_rd_ack_o <= '0';
regs_o.sdacr_dac_val_wr_o <= '0';
dmtr_in_rd_ack_o <= '0';
dmtr_out_rd_ack_o <= '0';
regs_o.scr_data_load_o <= '0';
fd_main_scr_start_int <= '0';
fd_main_tsbcr_purge_int <= '0';
......@@ -460,7 +454,6 @@ begin
fd_main_calr_cal_pulse_int_delay <= '0';
fd_main_calr_psel_swb <= fd_main_calr_psel_swb_delay;
fd_main_calr_psel_swb_delay <= '0';
regs_o.sdacr_dac_val_wr_o <= '0';
fd_main_adsfr_swb <= fd_main_adsfr_swb_delay;
fd_main_adsfr_swb_delay <= '0';
fd_main_atmcr_c_thr_swb <= fd_main_atmcr_c_thr_swb_delay;
......@@ -788,49 +781,11 @@ begin
fd_main_calr_psel_int <= wrdata_reg(6 downto 3);
fd_main_calr_psel_swb <= '1';
fd_main_calr_psel_swb_delay <= '1';
fd_main_calr_dmtd_fbsel_int <= wrdata_reg(7);
end if;
rddata_reg(0) <= 'X';
rddata_reg(1) <= fd_main_calr_cal_pps_int;
rddata_reg(2) <= fd_main_calr_cal_dmtd_int;
rddata_reg(6 downto 3) <= fd_main_calr_psel_int;
rddata_reg(7) <= fd_main_calr_dmtd_fbsel_int;
rddata_reg(30 downto 8) <= regs_i.calr_dmtd_tag_i;
calr_rd_ack_o <= '1';
rddata_reg(31) <= regs_i.calr_dmtd_tag_rdy_i;
ack_sreg(4) <= '1';
ack_in_progress <= '1';
when "001010" =>
if (wb_we_i = '1') then
fd_main_spllr_mode_int <= wrdata_reg(21);
end if;
rddata_reg(19 downto 0) <= regs_i.spllr_tag_i;
spllr_rd_ack_o <= '1';
rddata_reg(20) <= regs_i.spllr_tag_rdy_i;
rddata_reg(21) <= fd_main_spllr_mode_int;
rddata_reg(22) <= 'X';
rddata_reg(23) <= 'X';
rddata_reg(24) <= 'X';
rddata_reg(25) <= 'X';
rddata_reg(26) <= 'X';
rddata_reg(27) <= 'X';
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "001011" =>
if (wb_we_i = '1') then
regs_o.sdacr_dac_val_wr_o <= '1';
end if;
rddata_reg(0) <= 'X';
rddata_reg(1) <= 'X';
rddata_reg(2) <= 'X';
rddata_reg(3) <= 'X';
rddata_reg(4) <= 'X';
rddata_reg(5) <= 'X';
rddata_reg(6) <= 'X';
rddata_reg(7) <= 'X';
rddata_reg(8) <= 'X';
rddata_reg(9) <= 'X';
......@@ -856,6 +811,22 @@ begin
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
ack_sreg(4) <= '1';
ack_in_progress <= '1';
when "001010" =>
if (wb_we_i = '1') then
end if;
rddata_reg(30 downto 0) <= regs_i.dmtr_in_tag_i;
dmtr_in_rd_ack_o <= '1';
rddata_reg(31) <= regs_i.dmtr_in_rdy_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "001011" =>
if (wb_we_i = '1') then
end if;
rddata_reg(30 downto 0) <= regs_i.dmtr_out_tag_i;
dmtr_out_rd_ack_o <= '1';
rddata_reg(31) <= regs_i.dmtr_out_rdy_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "001100" =>
......@@ -1735,8 +1706,8 @@ begin
end process;
-- Triggers calibration pulses
-- synchronizer chain for field : Triggers calibration pulses (type RW/RO, clk_sys_i <-> clk_ref_i)
-- Produce DDMTD calibration pattern
-- synchronizer chain for field : Produce DDMTD calibration pattern (type RW/RO, clk_sys_i <-> clk_ref_i)
process (clk_ref_i, rst_n_i)
begin
if (rst_n_i = '0') then
......@@ -1771,17 +1742,10 @@ begin
end process;
-- DMTD Feedback Channel Select
regs_o.calr_dmtd_fbsel_o <= fd_main_calr_dmtd_fbsel_int;
-- DMTD Tag
-- DMTD Tag Ready
-- Frequency/Phase tag
-- Tag Ready
-- Freq/Phase mode select
regs_o.spllr_mode_o <= fd_main_spllr_mode_int;
-- DAC Value
-- pass-through field: DAC Value in register: Softpll DAC Register
regs_o.sdacr_dac_val_o <= wrdata_reg(15 downto 0);
-- DMTD Tag
-- DMTD Tag Ready
-- ADFSR Value
-- asynchronous std_logic_vector register : ADFSR Value (type RW/RO, clk_ref_i <-> clk_sys_i)
process (clk_ref_i, rst_n_i)
......
hdl/rtl/fd_main_wishbone_slave.wb
View file @ d27a3e3b
......@@ -374,7 +374,6 @@ peripheral {
reg {
prefix = "CALR";
name = "Calibration register";
field {
clock = "clk_ref_i";
......@@ -397,8 +396,8 @@ peripheral {
};
field {
clock = "clk_ref_i";
name = "Triggers calibration pulses";
-- clock = "clk_ref_i";
name = "Produce DDMTD calibration pattern";
description = "write 1: Enables DMTD test pattern generation on Delay chain input and output selected in PSEL.\
write 0: DMTD pattern generation disabled.";
prefix = "CAL_DMTD";
......@@ -418,23 +417,18 @@ write 0: DMTD pattern generation disabled.";
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
reg {
prefix = "DMTR_IN";
name = "DMTD Input Tag Register";
field {
name = "DMTD Feedback Channel Select";
prefix = "DMTD_FBSEL";
type = BIT;
description = "0: samples DDMTD pattern on the delay input\
1: samples DDMTD pattern on the delay output";
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
ack_read = "calr_rd_ack_o";
ack_read = "dmtr_in_rd_ack_o";
name = "DMTD Tag";
prefix = "DMTD_TAG";
size = 23;
prefix = "TAG";
size = 31;
type = SLV;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
......@@ -442,64 +436,37 @@ write 0: DMTD pattern generation disabled.";
field {
name = "DMTD Tag Ready";
prefix = "DMTD_TAG_RDY";
prefix = "RDY";
type = BIT;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "Softpll Register";
prefix = "SPLLR";
description = "Minimal SoftPLL register required to calibrate the card if it there's no WR core in the design";
reg {
prefix = "DMTR_OUT";
name = "DMTD Output Tag Register";
field {
ack_read = "spllr_rd_ack_o";
ack_read = "dmtr_out_rd_ack_o";
name = "Frequency/Phase tag";
name = "DMTD Tag";
prefix = "TAG";
size = 31;
type = SLV;
size = 20;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
field {
name = "Tag Ready";
prefix = "TAG_RDY";
name = "DMTD Tag Ready";
prefix = "RDY";
type = BIT;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
field {
name = "Freq/Phase mode select";
description = "0: sample frequency (pre-locking)\
1: sample phase";
prefix = "MODE";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
reg {
name = "Softpll DAC Register";
prefix = "SDACR";
description = "DMTD Dac Control register, used for calibration when there's no associated WR core";
field {
name = "DAC Value";
prefix = "DAC_VAL";
type = PASS_THROUGH;
size = 16;
};
};
reg {
prefix = "ADSFR";
name = "Acam to Delay line fractional part Scale Factor Register";
......
hdl/rtl/fine_delay_core.vhd
View file @ d27a3e3b
......@@ -6,7 +6,7 @@
-- Author : Tomasz Wlostowski
-- Company : CERN
-- Created : 2011-08-24
-- Last update: 2012-05-21
-- Last update: 2012-06-06
-- Platform : FPGA-generic
-- Standard : VHDL'93
-------------------------------------------------------------------------------
......@@ -179,14 +179,6 @@ entity fine_delay_core is
tm_dac_value_i : in std_logic_vector(23 downto 0);
tm_dac_wr_i : in std_logic;
---------------------------------------------------------------------------
-- DMTD DAC drive, used for calibration purposes only when not associated
-- with a WR Core
---------------------------------------------------------------------------
dmtd_dac_value_o : out std_logic_vector(23 downto 0);
dmtd_dac_wr_o : out std_logic;
---------------------------------------------------------------------------
-- Temeperature sensor (1-wire)
---------------------------------------------------------------------------
......@@ -205,7 +197,7 @@ entity fine_delay_core is
i2c_sda_oen_o : out std_logic;
i2c_sda_i : in std_logic;
fmc_present_n_i: in std_logic;
fmc_present_n_i : in std_logic;
---------------------------------------------------------------------------
......@@ -311,17 +303,18 @@ architecture rtl of fine_delay_core is
signal tag_valid_masked : std_logic;
signal dmtd_pattern : std_logic;
signal calr_rd_ack, spllr_rd_ack : std_logic;
signal csync_pps : std_logic;
signal tdc_cal_pulse : std_logic;
signal dmtd_pattern : std_logic;
signal csync_pps : std_logic;
signal tdc_cal_pulse : std_logic;
signal dmtr_in_rd_ack, dmtr_out_rd_ack : std_logic;
signal pwm_count : unsigned(11 downto 0);
signal pwm_out : std_logic;
signal spi_cs_dac_n, spi_cs_pll_n, spi_cs_gpio_n, spi_mosi : std_logic;
signal dmtd_tag_stb, dbg_tag_in, dbg_tag_out : std_logic;
begin -- rtl
......@@ -462,15 +455,12 @@ begin -- rtl
regs_o => regs_fromwb,
regs_i => regs_towb,
irq_ts_buf_notempty_i => irq_rbuf,
irq_dmtd_spll_i => irq_spll,
irq_dmtd_spll_i => '0',
irq_sync_status_i => irq_sync,
tsbcr_read_ack_o => tsbcr_read_ack,
fid_read_ack_o => fid_read_ack,
spllr_rd_ack_o => spllr_rd_ack,
calr_rd_ack_o => calr_rd_ack
dmtr_out_rd_ack_o => dmtr_out_rd_ack,
dmtr_in_rd_ack_o => dmtr_in_rd_ack
);
irq_spll <= '0';
U_Acam_TSU : fd_acam_timestamper
generic map (
......@@ -626,26 +616,23 @@ begin -- rtl
delay_len_o => delay_len_o);
U_DMTD_Calibrator : fd_dmtd_insertion_calibrator
generic map (
g_with_wr_core => g_with_wr_core)
port map (
clk_ref_i => clk_ref_0_i,
clk_dmtd_i => clk_dmtd_i,
clk_sys_i => clk_sys_i,
rst_n_sys_i => rst_n_sys,
rst_n_ref_i => rst_n_ref,
regs_i => regs_fromwb,
regs_o => regs_towb_dmtd,
dmtd_fb_in_i => dmtd_fb_in_i,
dmtd_fb_out_i => dmtd_fb_out_i,
dmtd_samp_o => dmtd_samp_o,
dmtd_pattern_o => dmtd_pattern,
calr_rd_ack_i => calr_rd_ack,
spllr_rd_ack_i => spllr_rd_ack,
wr_clk_dmtd_locked_i => tm_clk_dmtd_locked_i,
dmtd_dac_wr_o => dmtd_dac_wr_o,
dmtd_dac_value_o => dmtd_dac_value_o);
clk_ref_i => clk_ref_0_i,
clk_dmtd_i => clk_dmtd_i,
clk_sys_i => clk_sys_i,
rst_n_sys_i => rst_n_sys,
rst_n_ref_i => rst_n_ref,
regs_i => regs_fromwb,
regs_o => regs_towb_dmtd,
dmtd_fb_in_i => dmtd_fb_in_i,
dmtd_fb_out_i => dmtd_fb_out_i,
dmtd_samp_o => dmtd_samp_o,
dmtd_pattern_o => dmtd_pattern,
dmtr_in_rd_ack_i => dmtr_in_rd_ack,
dmtr_out_rd_ack_i => dmtr_out_rd_ack,
dbg_tag_in_o => dbg_tag_in,
dbg_tag_out_o => dbg_tag_out
);
tag_valid_masked <= tag_valid when unsigned(not chx_delay_idle) = 0 else '0';
......
hdl/rtl/fine_delay_pkg.vhd
View file @ d27a3e3b
......@@ -6,7 +6,7 @@
-- Author : Tomasz Wlostowski
-- Company : CERN
-- Created : 2011-08-24
-- Last update: 2012-05-21
-- Last update: 2012-06-06
-- Platform : FPGA-generic
-- Standard : VHDL'93
-------------------------------------------------------------------------------
......@@ -73,10 +73,10 @@ package fine_delay_pkg is
constant c_FD_NUM_OUTPUTS : integer := 4;
-- Number of reference clock cycles per one DDMTD calibration period
constant c_FD_DMTD_CALIBRATION_PERIOD : integer := 125;
constant c_FD_DMTD_CALIBRATION_PERIOD : integer := 144;
-- Calibration pulse width
constant c_FD_DMTD_CALIBRATION_PWIDTH : integer := 3;
constant c_FD_DMTD_CALIBRATION_PWIDTH : integer := 10;
constant c_fine_delay_core_sdwb : t_sdwb_device := (
......@@ -253,10 +253,10 @@ package fine_delay_pkg is
wb_int_o : out std_logic;
clk_ref_i : in std_logic;
tcr_rd_ack_o : out std_logic;
calr_rd_ack_o : out std_logic;
spllr_rd_ack_o : out std_logic;
tsbcr_read_ack_o : out std_logic;
fid_read_ack_o: out std_logic;
dmtr_in_rd_ack_o : out std_logic;
dmtr_out_rd_ack_o : out std_logic;
tsbcr_read_ack_o : out std_logic;
fid_read_ack_o : out std_logic;
irq_ts_buf_notempty_i : in std_logic;
irq_dmtd_spll_i : in std_logic;
irq_sync_status_i : in std_logic;
......@@ -308,29 +308,25 @@ package fine_delay_pkg is
wb_o : out t_wishbone_slave_out);
end component;
component fd_dmtd_insertion_calibrator
generic (
g_with_wr_core : boolean);
port (
clk_ref_i : in std_logic;
clk_dmtd_i : in std_logic;
clk_sys_i : in std_logic;
rst_n_sys_i : in std_logic;
rst_n_ref_i : in std_logic;
regs_i : in t_fd_main_out_registers;
regs_o : out t_fd_main_in_registers;
dmtd_fb_in_i : in std_logic;
dmtd_fb_out_i : in std_logic;
dmtd_samp_o : out std_logic;
dmtd_pattern_o : out std_logic;
calr_rd_ack_i : in std_logic;
spllr_rd_ack_i : in std_logic;
wr_clk_dmtd_locked_i : in std_logic;
dmtd_dac_value_o : out std_logic_vector(23 downto 0);
dmtd_dac_wr_o : out std_logic);
clk_ref_i : in std_logic;
clk_dmtd_i : in std_logic;
clk_sys_i : in std_logic;
rst_n_sys_i : in std_logic;
rst_n_ref_i : in std_logic;
regs_i : in t_fd_main_out_registers;
regs_o : out t_fd_main_in_registers;
dmtd_fb_in_i : in std_logic;
dmtd_fb_out_i : in std_logic;
dmtd_samp_o : out std_logic;
dmtd_pattern_o : out std_logic;
dmtr_in_rd_ack_i : in std_logic;
dmtr_out_rd_ack_i : in std_logic;
dbg_tag_in_o : out std_logic;
dbg_tag_out_o : out std_logic);
end component;
component fd_ring_buffer
generic (
g_size_log2 : integer);
......@@ -429,8 +425,6 @@ package fine_delay_pkg is
tm_clk_dmtd_locked_i : in std_logic;
tm_dac_value_i : in std_logic_vector(23 downto 0);
tm_dac_wr_i : in std_logic;
dmtd_dac_value_o : out std_logic_vector(23 downto 0);
dmtd_dac_wr_o : out std_logic;
owr_en_o : out std_logic;
owr_i : in std_logic;
i2c_scl_o : out std_logic;
......
hdl/syn/spec/non_wr/spec_fine_delay.xise deleted 100644 → 0
View file @ b4495e8a
This diff is collapsed.
hdl/syn/spec/non_wr/Manifest.py → hdl/syn/spec/wr/Manifest.py
View file @ d27a3e3b
......@@ -9,4 +9,4 @@ syn_package = "fgg484"
syn_top = "spec_top"
syn_project = "spec_fine_delay.xise"
modules = { "local" : [ "../../../top/spec/non_wr", "../../../platform" ] }
modules = { "local" : [ "../../../top/spec/wr", "../../../platform" ] }
hdl/syn/spec_wr_demo/Manifest.py deleted 100644 → 0
View file @ b4495e8a
target = "xilinx"
action = "synthesis"
fetchto = "../../ip_cores"
syn_device = "xc6slx45t"
syn_grade = "-3"
syn_package = "fgg484"
syn_top = "spec_top"
syn_project = "spec_fine_delay.xise"
files = "wrc_stub.ram"
modules = { "local" : [ "../../top/spec_wr_demo" ] }
hdl/syn/spec_wr_demo/wrc_stub.ram deleted 100644 → 0
View file @ b4495e8a
This diff is collapsed.
hdl/top/spec/non_wr/Manifest.py deleted 100644 → 0
View file @ b4495e8a
files = [
"spec_top.vhd",
"spec_top.ucf",
"spec_serial_dac.vhd",
"spec_serial_dac_arb.vhd"
];
fetchto = "../../../ip_cores"
modules = {"local" : [ "../../../rtl", "../../../platform" ],
"svn" : "http://svn.ohwr.org/gn4124-core/branches/hdlmake-compliant/rtl" }
hdl/top/spec/non_wr/spec_serial_dac.vhd deleted 100644 → 0
View file @ b4495e8a
-------------------------------------------------------------------------------
-- Title : Serial DAC interface
-- Project : White Rabbit Switch
-------------------------------------------------------------------------------
-- File : serial_dac.vhd
-- Author : paas, slayer
-- Company : CERN BE-Co-HT
-- Created : 2010-02-25
-- Last update: 2011-05-10
-- Platform : fpga-generic
-- Standard : VHDL'87
-------------------------------------------------------------------------------
-- Description: The dac unit provides an interface to a 16 bit serial Digita to Analogue converter (max5441, SPI?/QSPI?/MICROWIRE? compatible)
--
-------------------------------------------------------------------------------
-- Copyright (c) 2010 CERN
-------------------------------------------------------------------------------
-- Revisions :1
-- Date Version Author Description
-- 2009-01-24 1.0 paas Created
-- 2010-02-25 1.1 slayer Modified for rev 1.1 switch
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity spec_serial_dac is
generic (
g_num_data_bits : integer := 16;
g_num_extra_bits : integer := 8;
g_num_cs_select : integer := 2
);
port (
-- clock & reset
clk_i : in std_logic;
rst_n_i : in std_logic;
-- channel 1 value and value load strobe
value_i : in std_logic_vector(g_num_data_bits-1 downto 0);
cs_sel_i : in std_logic_vector(g_num_cs_select-1 downto 0);
load_i : in std_logic;
-- SCLK divider: 000 = clk_i/8 ... 111 = clk_i/1024
sclk_divsel_i : in std_logic_vector(2 downto 0);
-- DAC I/F
dac_cs_n_o : out std_logic_vector(g_num_cs_select-1 downto 0);
dac_sclk_o : out std_logic;
dac_sdata_o : out std_logic;
xdone_o : out std_logic
);
end spec_serial_dac;
architecture syn of spec_serial_dac is
signal divider : unsigned(11 downto 0);
signal dataSh : std_logic_vector(g_num_data_bits + g_num_extra_bits-1 downto 0);
signal bitCounter : std_logic_vector(g_num_data_bits + g_num_extra_bits+1 downto 0);
signal endSendingData : std_logic;
signal sendingData : std_logic;
signal iDacClk : std_logic;
signal iValidValue : std_logic;
signal divider_muxed : std_logic;
signal cs_sel_reg : std_logic_vector(g_num_cs_select-1 downto 0);
begin
select_divider : process (divider, sclk_divsel_i)
begin -- process
case sclk_divsel_i is
when "000" => divider_muxed <= divider(1); -- sclk = clk_i/8
when "001" => divider_muxed <= divider(2); -- sclk = clk_i/16
when "010" => divider_muxed <= divider(3); -- sclk = clk_i/32
when "011" => divider_muxed <= divider(4); -- sclk = clk_i/64
when "100" => divider_muxed <= divider(5); -- sclk = clk_i/128
when "101" => divider_muxed <= divider(6); -- sclk = clk_i/256
when "110" => divider_muxed <= divider(7); -- sclk = clk_i/512
when "111" => divider_muxed <= divider(8); -- sclk = clk_i/1024
when others => null;
end case;
end process;
iValidValue <= load_i;
process(clk_i, rst_n_i)
begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
sendingData <= '0';
else
if iValidValue = '1' and sendingData = '0' then
sendingData <= '1';
elsif endSendingData = '1' then
sendingData <= '0';
end if;
end if;
end if;
end process;
process(clk_i)
begin
if rising_edge(clk_i) then
if iValidValue = '1' then
divider <= (others => '0');
elsif sendingData = '1' then
if(divider_muxed = '1') then
divider <= (others => '0');
else
divider <= divider + 1;
end if;
elsif endSendingData = '1' then
divider <= (others => '0');
end if;
end if;
end process;
process(clk_i, rst_n_i)
begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
iDacClk <= '1'; -- 0
else
if iValidValue = '1' then
iDacClk <= '1'; -- 0
elsif divider_muxed = '1' then
iDacClk <= not(iDacClk);
elsif endSendingData = '1' then
iDacClk <= '1'; -- 0
end if;
end if;
end if;
end process;
process(clk_i, rst_n_i)
begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
dataSh <= (others => '0');
else
if iValidValue = '1' and sendingData = '0' then
cs_sel_reg <= cs_sel_i;
dataSh(g_num_data_bits-1 downto 0) <= value_i;
dataSh(dataSh'left downto g_num_data_bits) <= (others => '0');
elsif sendingData = '1' and divider_muxed = '1' and iDacClk = '0' then
dataSh(0) <= dataSh(dataSh'left);
dataSh(dataSh'left downto 1) <= dataSh(dataSh'left - 1 downto 0);
end if;
end if;
end if;
end process;
process(clk_i)
begin
if rising_edge(clk_i) then
if iValidValue = '1' and sendingData = '0' then
bitCounter(0) <= '1';
bitCounter(bitCounter'left downto 1) <= (others => '0');
elsif sendingData = '1' and to_integer(divider) = 0 and iDacClk = '1' then
bitCounter(0) <= '0';
bitCounter(bitCounter'left downto 1) <= bitCounter(bitCounter'left - 1 downto 0);
end if;
end if;
end process;
endSendingData <= bitCounter(bitCounter'left);
xdone_o <= not SendingData;
dac_sdata_o <= dataSh(dataSh'left);
gen_cs_out : for i in 0 to g_num_cs_select-1 generate
dac_cs_n_o(i) <= not(sendingData) or (not cs_sel_reg(i));
end generate gen_cs_out;
dac_sclk_o <= iDacClk;
end syn;
hdl/top/spec/non_wr/spec_serial_dac_arb.vhd deleted 100644 → 0
View file @ b4495e8a
library ieee;
use ieee.std_logic_1164.all;
entity spec_serial_dac_arb is
generic(
g_invert_sclk : boolean;
g_num_extra_bits : integer
);
port(
clk_i : in std_logic;
rst_n_i : in std_logic;
val1_i : in std_logic_vector(15 downto 0);
load1_i : in std_logic;
val2_i : in std_logic_vector(15 downto 0);
load2_i : in std_logic;
dac_cs_n_o : out std_logic_vector(1 downto 0);
dac_clr_n_o : out std_logic;
dac_sclk_o : out std_logic;
dac_din_o : out std_logic);
end spec_serial_dac_arb;
architecture behavioral of spec_serial_dac_arb is
component spec_serial_dac
generic (
g_num_data_bits : integer;
g_num_extra_bits : integer;
g_num_cs_select : integer);
port (
clk_i : in std_logic;
rst_n_i : in std_logic;
value_i : in std_logic_vector(g_num_data_bits-1 downto 0);
cs_sel_i : in std_logic_vector(g_num_cs_select-1 downto 0);
load_i : in std_logic;
sclk_divsel_i : in std_logic_vector(2 downto 0);
dac_cs_n_o : out std_logic_vector(g_num_cs_select-1 downto 0);
dac_sclk_o : out std_logic;
dac_sdata_o : out std_logic;
xdone_o : out std_logic);
end component;
signal d1, d2 : std_logic_vector(15 downto 0);
signal d1_ready, d2_ready : std_logic;
signal dac_data : std_logic_vector(15 downto 0);
signal dac_load : std_logic;
signal dac_cs_sel : std_logic_vector(1 downto 0);
signal dac_done : std_logic;
signal dac_sclk_int : std_logic;
type t_state is (WAIT_DONE, LOAD_DAC, WAIT_DATA);
signal state : t_state;
signal trig0 : std_logic_vector(31 downto 0);
signal trig1 : std_logic_vector(31 downto 0);
signal trig2 : std_logic_vector(31 downto 0);
signal trig3 : std_logic_vector(31 downto 0);
signal CONTROL0 : std_logic_vector(35 downto 0);
begin -- behavioral
dac_clr_n_o <= '1';
U_DAC : spec_serial_dac
generic map (
g_num_data_bits => 16,
g_num_extra_bits => g_num_extra_bits,
g_num_cs_select => 2)
port map (
clk_i => clk_i,
rst_n_i => rst_n_i,
value_i => dac_data,
cs_sel_i => dac_cs_sel,
load_i => dac_load,
sclk_divsel_i => "001",
dac_cs_n_o => dac_cs_n_o,
dac_sclk_o => dac_sclk_int,
dac_sdata_o => dac_din_o,
xdone_o => dac_done);
p_drive_sclk: process(dac_sclk_int)
begin
if(g_invert_sclk) then
dac_sclk_o <= not dac_sclk_int;
else
dac_sclk_o <= dac_sclk_int;
end if;
end process;
process(clk_i)
begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
d1 <= (others => '0');
d1_ready <= '0';
d2 <= (others => '0');
d2_ready <= '0';
dac_load <= '0';
dac_cs_sel <= (others => '0');
state <= WAIT_DATA;
else
if(load1_i = '1' or load2_i = '1') then
if(load1_i = '1') then
d1_ready <= '1';
d1 <= val1_i;
end if;
if(load2_i = '1') then
d2_ready <= '1';
d2 <= val2_i;
end if;
else
case state is
when WAIT_DATA =>
if(d1_ready = '1') then
dac_cs_sel <= "01";
dac_data <= d1;
dac_load <= '1';
d1_ready <= '0';
state <= LOAD_DAC;
elsif(d2_ready = '1') then
dac_cs_sel <= "10";
dac_data <= d2;
dac_load <= '1';
d2_ready <= '0';
state <= LOAD_DAC;
end if;
when LOAD_DAC=>
dac_load <= '0';
state <= WAIT_DONE;
when WAIT_DONE =>
if(dac_done = '1') then
state <= WAIT_DATA;
end if;
when others => null;
end case;
end if;
end if;
end if;
end process;
end behavioral;
hdl/top/spec/non_wr/spec_top.ucf deleted 100644 → 0
View file @ b4495e8a
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hdl/top/spec/non_wr/spec_top.vhd deleted 100644 → 0
View file @ b4495e8a
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hdl/top/spec/wr/mini_bone/Manifest.py 0 → 100644
View file @ d27a3e3b
files = ["mini_bone.vhd", "xmini_bone.vhd"];
hdl/top/spec/wr/mini_bone/mini_bone.vhd 0 → 100644
View file @ d27a3e3b
library ieee;
use ieee.std_logic_1164.all;
use work.Wishbone_pkg.all;
use work.wr_fabric_pkg.all;
entity mini_bone is
generic(
g_class_mask : std_logic_vector(7 downto 0) := x"ff";
g_our_ethertype : std_logic_vector(15 downto 0) := x"a0a0");
port (
clk_sys_i : in std_logic;
rst_n_i : in std_logic;
snk_cyc_i : in std_logic;
snk_stb_i : in std_logic;
snk_sel_i : in std_logic_vector(1 downto 0);
snk_adr_i : in std_logic_vector(1 downto 0);
snk_dat_i : in std_logic_vector(15 downto 0);
snk_we_i : in std_logic;
snk_stall_o : out std_logic;
snk_ack_o : out std_logic;
snk_err_o : out std_logic;
src_cyc_o : out std_logic;
src_stb_o : out std_logic;
src_dat_o : out std_logic_vector(15 downto 0);
src_adr_o : out std_logic_vector(1 downto 0);
src_we_o : out std_logic;
src_ack_i : in std_logic;
src_err_i : in std_logic;
src_sel_o : out std_logic_vector(1 downto 0);
src_stall_i : in std_logic;
master_cyc_o : out std_logic;
master_we_o : out std_logic;
master_stb_o : out std_logic;
master_sel_o : out std_logic_vector(3 downto 0);
master_adr_o : out std_logic_vector(31 downto 0);
master_dat_o : out std_logic_vector(31 downto 0);
master_dat_i : in std_logic_vector(31 downto 0);
master_ack_i : in std_logic
);
end mini_bone;
architecture wrapper of mini_bone is
component xmini_bone
generic (
g_class_mask : std_logic_vector(7 downto 0);
g_our_ethertype : std_logic_vector(15 downto 0));
port (
clk_sys_i : in std_logic;
rst_n_i : in std_logic;
src_o : out t_wrf_source_out;
src_i : in t_wrf_source_in;
snk_o : out t_wrf_sink_out;
snk_i : in t_wrf_sink_in;
master_o : out t_wishbone_master_out;
master_i : in t_wishbone_master_in);
end component;
signal src_out : t_wrf_source_out;
signal src_in : t_wrf_source_in;
signal snk_out : t_wrf_sink_out;
signal snk_in : t_wrf_sink_in;
signal master_out : t_wishbone_master_out;
signal master_in : t_wishbone_master_in;
begin -- wrapper
U_Wrapped_MB : xmini_bone
generic map (
g_class_mask => g_class_mask,
g_our_ethertype => g_our_ethertype)
port map (
clk_sys_i => clk_sys_i,
rst_n_i => rst_n_i,
src_o => src_out,
src_i => src_in,
snk_o => snk_out,
snk_i => snk_in,
master_o => master_out,
master_i => master_in);
src_cyc_o <= src_out.cyc;
src_stb_o <= src_out.stb;
src_we_o <= src_out.we;
src_adr_o <= src_out.adr;
src_dat_o <= src_out.dat;
src_sel_o <= src_out.sel;
src_in.ack <= src_ack_i;
src_in.stall <= src_stall_i;
snk_in.cyc <= snk_cyc_i;
snk_in.stb <= snk_stb_i;
snk_in.we <= snk_we_i;
snk_in.sel <= snk_sel_i;
snk_in.adr <= snk_adr_i;
snk_in.dat <= snk_dat_i;
snk_ack_o <= snk_out.ack;
snk_stall_o <= snk_out.stall;
master_cyc_o <= master_out.cyc;
master_stb_o <= master_out.stb;
master_we_o <= master_out.we;
master_sel_o <= master_out.sel;
master_adr_o <= master_out.adr;
master_dat_o <= master_out.dat;
master_in.dat <= master_dat_i;
master_in.ack <= master_ack_i;
end wrapper;
hdl/top/spec/wr/mini_bone/xmini_bone.vhd 0 → 100644
View file @ d27a3e3b
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