Commit c2353fcd authored by Tomasz Wlostowski's avatar Tomasz Wlostowski

hdl/[top,syn]: updated manifests and ISE projects to the latest submodule versions

parent 68cd7428
target = "xilinx"
action = "synthesis"
fetchto = "../../../ip_cores"
fetchto = "../../ip_cores"
syn_device = "xc6slx45t"
syn_grade = "-3"
......@@ -9,6 +9,6 @@ syn_package = "fgg484"
syn_top = "spec_top"
syn_project = "spec_fine_delay.xise"
modules = { "local" : [ "../../../top/spec/wr", "../../../platform" ] }
modules = { "local" : [ "../../top/spec", "../../platform" ] }
files = "wrc.ram"
\ No newline at end of file
files = "wrc-release.ram"
\ No newline at end of file
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target = "xilinx"
action = "synthesis"
fetchto = "../../../ip_cores"
fetchto = "../../ip_cores"
syn_device = "xc6slx150t"
syn_grade = "-3"
......@@ -10,4 +10,4 @@ syn_top = "svec_top"
syn_project = "svec_fine_delay.xise"
files = [ "wrc-release.ram" ]
modules = { "local" : [ "../../../top/svec/wr", "../../../platform" ] }
modules = { "local" : [ "../../top/svec", "../../platform" ] }
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files = ["synthesis_descriptor.vhd", "spec_top.vhd", "spec_top.ucf", "spec_serial_dac.vhd", "spec_serial_dac_arb.vhd", "spec_reset_gen.vhd"]
files = ["synthesis_descriptor.vhd", "spec_top.vhd", "spec_top.ucf", "spec_reset_gen.vhd"]
fetchto = "../../../ip_cores"
fetchto = "../../ip_cores"
modules = {
"local" : ["../../../rtl", "../../../platform" ],
"local" : ["../../rtl", "../../platform" ],
"git" : [ "git://ohwr.org/hdl-core-lib/wr-cores.git",
"git://ohwr.org/hdl-core-lib/etherbone-core.git",
"git://ohwr.org/hdl-core-lib/gn4124-core.git" ]
}
......@@ -42,11 +42,11 @@ package synthesis_descriptor is
constant c_sdb_synthesis_info : t_sdb_synthesis :=
(
syn_module_name => "fine-delay-spec ",
syn_module_name => "spec-fine-delay ",
syn_commit_id => "00000000000000000000000000000000",
syn_tool_name => "ISE ",
syn_tool_version => x"00000133",
syn_date => x"00000000",
syn_date => x"20140318",
syn_username => "twlostow ");
constant c_sdb_repo_url : t_sdb_repo_url :=
......
files = [ "synthesis_descriptor.vhd", "svec_top.vhd", "svec_top.ucf", "bicolor_led_ctrl.vhd", "bicolor_led_ctrl_pkg.vhd" ]
fetchto = "../../../ip_cores"
fetchto = "../../ip_cores"
modules = {
"local" : ["../../../rtl", "../../../platform" ],
"local" : ["../../rtl", "../../platform" ],
"git" : [ "git://ohwr.org/hdl-core-lib/wr-cores.git",
"git://ohwr.org/hdl-core-lib/vme64x-core.git" ]
}
......@@ -6,7 +6,7 @@
-- Author : Tomasz Wlostowski
-- Company : CERN
-- Created : 2013-04-16
-- Last update: 2013-04-16
-- Last update: 2014-03-18
-- Platform : FPGA-generic
-- Standard : VHDL'93
-------------------------------------------------------------------------------
......@@ -42,11 +42,11 @@ package synthesis_descriptor is
constant c_sdb_synthesis_info : t_sdb_synthesis :=
(
syn_module_name => "fine-delay-svec ",
syn_commit_id => "00000000000000000000000000000000",
syn_module_name => "svec-fine-delay ",
syn_commit_id => "70c0e0331fcf94f3067f5f677c01b59e",
syn_tool_name => "ISE ",
syn_tool_version => x"00000133",
syn_date => x"00000000",
syn_date => x"20140318",
syn_username => "twlostow ");
constant c_sdb_repo_url : t_sdb_repo_url :=
......
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