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FMC DEL 1ns 4cha
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FMC DEL 1ns 4cha
Commits
be2a5d7b
Commit
be2a5d7b
authored
Oct 15, 2019
by
Tomasz Wlostowski
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rtl: expose g_fmc_slot_id parameter in component declaration
parent
fbf84871
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6 changed files
with
1678 additions
and
2119 deletions
+1678
-2119
fine_delay_pkg.vhd
hdl/rtl/fine_delay_pkg.vhd
+3
-2
Manifest.py
hdl/syn/svec/Manifest.py
+31
-8
svec_fine_delay.xise
hdl/syn/svec/svec_fine_delay.xise
+616
-343
Manifest.py
hdl/top/svec/Manifest.py
+11
-4
svec_top.ucf
hdl/top/svec/svec_top.ucf
+389
-774
svec_top.vhd
hdl/top/svec/svec_top.vhd
+628
-988
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hdl/rtl/fine_delay_pkg.vhd
View file @
be2a5d7b
...
@@ -6,7 +6,7 @@
...
@@ -6,7 +6,7 @@
-- Author : Tomasz Wlostowski
-- Author : Tomasz Wlostowski
-- Company : CERN
-- Company : CERN
-- Created : 2011-08-24
-- Created : 2011-08-24
-- Last update: 2019-
03-21
-- Last update: 2019-
10-15
-- Platform : FPGA-generic
-- Platform : FPGA-generic
-- Standard : VHDL'93
-- Standard : VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
...
@@ -356,7 +356,8 @@ package fine_delay_pkg is
...
@@ -356,7 +356,8 @@ package fine_delay_pkg is
g_simulation
:
boolean
:
=
false
;
g_simulation
:
boolean
:
=
false
;
g_with_direct_timestamp_io
:
boolean
:
=
false
;
g_with_direct_timestamp_io
:
boolean
:
=
false
;
g_interface_mode
:
t_wishbone_interface_mode
;
g_interface_mode
:
t_wishbone_interface_mode
;
g_address_granularity
:
t_wishbone_address_granularity
);
g_address_granularity
:
t_wishbone_address_granularity
;
g_fmc_slot_id
:
integer
:
=
0
);
port
(
port
(
clk_ref_0_i
:
in
std_logic
;
clk_ref_0_i
:
in
std_logic
;
clk_ref_180_i
:
in
std_logic
;
clk_ref_180_i
:
in
std_logic
;
...
...
hdl/syn/svec/Manifest.py
View file @
be2a5d7b
board
=
"svec"
target
=
"xilinx"
target
=
"xilinx"
action
=
"synthesis"
action
=
"synthesis"
fetchto
=
"../../ip_cores"
syn_device
=
"xc6slx150t"
syn_grade
=
"-3"
syn_device
=
"xc6slx150t"
syn_grade
=
"-3"
syn_package
=
"fgg900"
syn_package
=
"fgg900"
syn_top
=
"svec_top"
syn_top
=
"svec_top"
syn_project
=
"svec_fine_delay.xise"
syn_project
=
"svec_fine_delay.xise"
syn_tool
=
"ise"
syn_tool
=
"ise"
# Allow the user to override fetchto using:
# hdlmake -p "fetchto='xxx'"
if
locals
()
.
get
(
'fetchto'
,
None
)
is
None
:
fetchto
=
"../../ip_cores"
files
=
[
"buildinfo_pkg.vhd"
,
]
modules
=
{
"local"
:
[
"../../top/svec"
,
],
}
# Do not fail during hdlmake fetch
try
:
exec
(
open
(
fetchto
+
"/general-cores/tools/gen_buildinfo.py"
)
.
read
())
except
:
pass
syn_post_project_cmd
=
"$(TCL_INTERPRETER) syn_extra_steps.tcl $(PROJECT_FILE)"
svec_base_ucf
=
[
'wr'
,
'led'
,
'gpio'
]
#files = [ "wrc-release.ram" ]
ctrls
=
[
"bank4_64b_32b"
,
"bank5_64b_32b"
]
modules
=
{
"local"
:
[
"../../top/svec"
,
"../../platform"
]
}
hdl/syn/svec/svec_fine_delay.xise
View file @
be2a5d7b
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hdl/top/svec/Manifest.py
View file @
be2a5d7b
files
=
[
"synthesis_descriptor.vhd"
,
"svec_top.vhd"
,
"svec_top.ucf"
,
"bicolor_led_ctrl.vhd"
,
"bicolor_led_ctrl_pkg.vhd"
]
files
=
[
"svec_top.vhd"
,
"svec_top.ucf"
]
fetchto
=
"../../ip_cores"
fetchto
=
"../../ip_cores"
modules
=
{
modules
=
{
"local"
:
[
"../../rtl"
,
"../../platform"
],
"local"
:
[
"git"
:
[
"git://ohwr.org/hdl-core-lib/wr-cores.git"
,
"../../rtl"
,
"git://ohwr.org/hdl-core-lib/vme64x-core.git"
]
"../../platform"
,
"../../ip_cores/general-cores"
,
"../../ip_cores/wr-cores"
,
"../../ip_cores/wr-cores/board/svec"
,
"../../ip_cores/vme64x-core"
,
"../../ip_cores/svec"
,
"../../ip_cores/ddr3-sp6-core"
]
}
}
hdl/top/svec/svec_top.ucf
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be2a5d7b
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hdl/top/svec/svec_top.vhd
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be2a5d7b
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