Commit be2a5d7b authored by Tomasz Wlostowski's avatar Tomasz Wlostowski

rtl: expose g_fmc_slot_id parameter in component declaration

parent fbf84871
......@@ -6,7 +6,7 @@
-- Author : Tomasz Wlostowski
-- Company : CERN
-- Created : 2011-08-24
-- Last update: 2019-03-21
-- Last update: 2019-10-15
-- Platform : FPGA-generic
-- Standard : VHDL'93
-------------------------------------------------------------------------------
......@@ -356,7 +356,8 @@ package fine_delay_pkg is
g_simulation : boolean := false;
g_with_direct_timestamp_io : boolean := false;
g_interface_mode : t_wishbone_interface_mode;
g_address_granularity : t_wishbone_address_granularity);
g_address_granularity : t_wishbone_address_granularity;
g_fmc_slot_id : integer := 0);
port (
clk_ref_0_i : in std_logic;
clk_ref_180_i : in std_logic;
......
board = "svec"
target = "xilinx"
action = "synthesis"
fetchto = "../../ip_cores"
syn_device = "xc6slx150t"
syn_grade = "-3"
syn_device = "xc6slx150t"
syn_grade = "-3"
syn_package = "fgg900"
syn_top = "svec_top"
syn_top = "svec_top"
syn_project = "svec_fine_delay.xise"
syn_tool="ise"
syn_tool = "ise"
# Allow the user to override fetchto using:
# hdlmake -p "fetchto='xxx'"
if locals().get('fetchto', None) is None:
fetchto = "../../ip_cores"
files = [
"buildinfo_pkg.vhd",
]
modules = {
"local" : [
"../../top/svec",
],
}
# Do not fail during hdlmake fetch
try:
exec(open(fetchto + "/general-cores/tools/gen_buildinfo.py").read())
except:
pass
syn_post_project_cmd = "$(TCL_INTERPRETER) syn_extra_steps.tcl $(PROJECT_FILE)"
svec_base_ucf = ['wr', 'led', 'gpio']
#files = [ "wrc-release.ram" ]
modules = { "local" : [ "../../top/svec", "../../platform" ] }
ctrls = ["bank4_64b_32b", "bank5_64b_32b"]
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files = [ "synthesis_descriptor.vhd", "svec_top.vhd", "svec_top.ucf", "bicolor_led_ctrl.vhd", "bicolor_led_ctrl_pkg.vhd" ]
files = ["svec_top.vhd", "svec_top.ucf"]
fetchto = "../../ip_cores"
modules = {
"local" : ["../../rtl", "../../platform" ],
"git" : [ "git://ohwr.org/hdl-core-lib/wr-cores.git",
"git://ohwr.org/hdl-core-lib/vme64x-core.git" ]
"local" : [
"../../rtl",
"../../platform",
"../../ip_cores/general-cores",
"../../ip_cores/wr-cores",
"../../ip_cores/wr-cores/board/svec",
"../../ip_cores/vme64x-core",
"../../ip_cores/svec",
"../../ip_cores/ddr3-sp6-core"
]
}
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