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FMC DEL 1ns 4cha
Commit b29188b3 authored by Tomasz Wlostowski's avatar Tomasz Wlostowski
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rtl: added FMC_SLOT_ID register

parent 4a39c5d8
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Showing with 64 additions and 7 deletions
hdl/rtl/fd_main_wbgen2_pkg.vhd
View file @ b29188b3
......@@ -3,7 +3,7 @@
---------------------------------------------------------------------------------------
-- File : fd_main_wbgen2_pkg.vhd
-- Author : auto-generated by wbgen2 from fd_main_wishbone_slave.wb
-- Created : Wed Mar 20 23:27:12 2019
-- Created : Wed Sep 11 15:18:56 2019
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE fd_main_wishbone_slave.wb
......@@ -56,6 +56,7 @@ package fd_main_wbgen2_pkg is
i2cr_sda_in_i : std_logic;
tder1_vcxo_freq_i : std_logic_vector(31 downto 0);
tsbr_debug_i : std_logic_vector(31 downto 0);
fmc_slot_id_slot_id_i : std_logic_vector(3 downto 0);
end record;
constant c_fd_main_in_registers_init_value: t_fd_main_in_registers := (
......@@ -93,7 +94,8 @@ package fd_main_wbgen2_pkg is
i2cr_scl_in_i => '0',
i2cr_sda_in_i => '0',
tder1_vcxo_freq_i => (others => '0'),
tsbr_debug_i => (others => '0')
tsbr_debug_i => (others => '0'),
fmc_slot_id_slot_id_i => (others => '0')
);
-- Output registers (WB slave -> user design)
......@@ -315,6 +317,7 @@ begin
tmp.i2cr_sda_in_i := f_x_to_zero(left.i2cr_sda_in_i) or f_x_to_zero(right.i2cr_sda_in_i);
tmp.tder1_vcxo_freq_i := f_x_to_zero(left.tder1_vcxo_freq_i) or f_x_to_zero(right.tder1_vcxo_freq_i);
tmp.tsbr_debug_i := f_x_to_zero(left.tsbr_debug_i) or f_x_to_zero(right.tsbr_debug_i);
tmp.fmc_slot_id_slot_id_i := f_x_to_zero(left.fmc_slot_id_slot_id_i) or f_x_to_zero(right.fmc_slot_id_slot_id_i);
return tmp;
end function;
......
hdl/rtl/fd_main_wishbone_slave.vhd
View file @ b29188b3
......@@ -3,7 +3,7 @@
---------------------------------------------------------------------------------------
-- File : fd_main_wishbone_slave.vhd
-- Author : auto-generated by wbgen2 from fd_main_wishbone_slave.wb
-- Created : Wed Mar 20 23:27:12 2019
-- Created : Wed Sep 11 15:18:56 2019
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE fd_main_wishbone_slave.wb
......@@ -1193,6 +1193,40 @@ begin
rddata_reg(31) <= 'X';
ack_sreg(2) <= '1';
ack_in_progress <= '1';
when "011111" =>
if (wb_we_i = '1') then
end if;
rddata_reg(3 downto 0) <= regs_i.fmc_slot_id_slot_id_i;
rddata_reg(4) <= 'X';
rddata_reg(5) <= 'X';
rddata_reg(6) <= 'X';
rddata_reg(7) <= 'X';
rddata_reg(8) <= 'X';
rddata_reg(9) <= 'X';
rddata_reg(10) <= 'X';
rddata_reg(11) <= 'X';
rddata_reg(12) <= 'X';
rddata_reg(13) <= 'X';
rddata_reg(14) <= 'X';
rddata_reg(15) <= 'X';
rddata_reg(16) <= 'X';
rddata_reg(17) <= 'X';
rddata_reg(18) <= 'X';
rddata_reg(19) <= 'X';
rddata_reg(20) <= 'X';
rddata_reg(21) <= 'X';
rddata_reg(22) <= 'X';
rddata_reg(23) <= 'X';
rddata_reg(24) <= 'X';
rddata_reg(25) <= 'X';
rddata_reg(26) <= 'X';
rddata_reg(27) <= 'X';
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "100000" =>
if (wb_we_i = '1') then
eic_idr_write_int <= '1';
......@@ -2105,6 +2139,7 @@ begin
end process;
-- Slot ID
-- extra code for reg/fifo/mem: Interrupt disable register
eic_idr_int(2 downto 0) <= wrdata_reg(2 downto 0);
-- extra code for reg/fifo/mem: Interrupt enable register
......
hdl/rtl/fd_main_wishbone_slave.wb
View file @ b29188b3
......@@ -1072,7 +1072,21 @@ peripheral {
};
};
reg {
name = "FMC Slot ID Register";
description = "Index of the hardware FMC slot the card is in.";
prefix = "FMC_SLOT_ID";
field {
name = "Slot ID";
prefix = "SLOT_ID";
type = SLV;
size = 4;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
irq {
name = "Timestamp Buffer interrupt.";
description = "Triggers when there are timestamps in the readout buffer";
......
hdl/rtl/fine_delay_core.vhd
View file @ b29188b3
......@@ -6,7 +6,7 @@
-- Author : Tomasz Wlostowski
-- Company : CERN
-- Created : 2011-08-24
-- Last update: 2019-03-21
-- Last update: 2019-09-11
-- Platform : FPGA-generic
-- Standard : VHDL'93
-------------------------------------------------------------------------------
......@@ -65,7 +65,11 @@ entity fine_delay_core is
g_interface_mode : t_wishbone_interface_mode := PIPELINED;
g_address_granularity : t_wishbone_address_granularity := WORD;
g_with_debug_output : boolean := false
g_with_debug_output : boolean := false;
-- index of the slot the core is assigned to, written to
-- FMC_SLOT_ID register
g_fmc_slot_id : integer := 0
);
port (
......@@ -790,7 +794,8 @@ begin -- rtl
regs_towb_local.gcr_ddr_locked_i <= pll_status_i;
regs_towb_local.gcr_fmc_present_i <= not fmc_present_n_i;
regs_towb_local.fmc_slot_id_slot_id_i <= std_logic_vector(to_unsigned(g_fmc_slot_id, 4 ));
-- Debug PWM driver for adjusting Peltier temperature. Drivers SPI MOSI line
-- with PWM waveform when none of the SPI peripherals is in use (we have no
-- spare pins in the FMC connector left)
......
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