Skip to content
Projects
Groups
Snippets
Help
Loading...
Sign in
Toggle navigation
F
FMC DEL 1ns 4cha
Project
Project
Details
Activity
Cycle Analytics
Repository
Repository
Files
Commits
Branches
Tags
Contributors
Graph
Compare
Charts
Issues
2
Issues
2
List
Board
Labels
Milestones
Merge Requests
0
Merge Requests
0
Wiki
Wiki
image/svg+xml
Discourse
Discourse
Members
Members
Collapse sidebar
Close sidebar
Activity
Graph
Charts
Create a new issue
Commits
Issue Boards
Open sidebar
Projects
FMC DEL 1ns 4cha
Commits
b1c4c30c
Commit
b1c4c30c
authored
Jun 05, 2011
by
Tomasz Wlostowski
Browse files
Options
Browse Files
Download
Email Patches
Plain Diff
added ISE SPEC 1.1 project
parent
99bea106
Hide whitespace changes
Inline
Side-by-side
Showing
3 changed files
with
1354 additions
and
0 deletions
+1354
-0
Makefile
hdl/syn/spec_1_1/Makefile
+268
-0
Manifest.py
hdl/syn/spec_1_1/Manifest.py
+12
-0
finedelay_spec_1_1.xise
hdl/syn/spec_1_1/finedelay_spec_1_1.xise
+1074
-0
No files found.
hdl/syn/spec_1_1/Makefile
0 → 100644
View file @
b1c4c30c
####################################
# This file was generated by hdlmake
# http://ohwr.org/projects/hdl-make/
####################################
PROJECT
:=
finedelay_spec_1_1.xise
ISE_CRAP
:=
*
.bgn
*
.html
*
.tcl
*
.bld
*
.cmd_log
*
.drc
*
.lso
*
.ncd
*
.ngc
*
.ngd
*
.ngr
*
.pad
*
.par
*
.pcf
*
.prj
*
.ptwx
*
.stx
*
.syr
*
.twr
*
.twx
*
.gise
*
.unroutes
*
.ut
*
.xpi
*
.xst
*
_bitgen.xwbt
*
_envsettings.html
*
_guide.ncd
*
_map.map
*
_map.mrp
*
_map.ncd
*
_map.ngm
*
_map.xrpt
*
_ngdbuild.xrpt
*
_pad.csv
*
_pad.txt
*
_par.xrpt
*
_summary.html
*
_summary.xml
*
_usage.xml
*
_xst.xrpt usage_statistics_webtalk.html webtalk.log webtalk_pn.xml run.tcl
#target for performing local synthesis
local
:
echo
"project open
$(PROJECT)
"
>
run.tcl
echo
"process run {Generate Programming File} -force rerun_all"
>>
run.tcl
xtclsh run.tcl
#target for cleaing all intermediate stuff
clean
:
rm
-f
$(ISE_CRAP)
rm
-rf
xst xlnx_auto_
*
_xdb iseconfig _xmsgs _ngo
#target for cleaning final files
mrproper
:
rm
-f
*
.bit
*
.bin
*
.mcs
USER
:=
$(HDLMAKE_USER)
SERVER
:=
$(HDLMAKE_SERVER)
R_NAME
:=
finedelay_spec_1_1
CWD
:=
$(
shell
pwd
)
FILES
:=
../../top/spec_1_1/spec_top_finedelay.vhd
\
../../top/spec_1_1/spec_top_finedelay.ucf
\
../../top/spec_1_1/wb_gpio_port_notristates.vhd
\
../../rtl/fd_acam_timestamper.vhd
\
../../rtl/fd_cal_pulse_gen.vhd
\
../../rtl/fd_delay_line_driver.vhd
\
../../rtl/fd_wbgen2_pkg.vhd
\
../../rtl/fine_delay_core.vhd
\
../../rtl/fine_delay_pkg.vhd
\
../../rtl/fine_delay_wb.vhd
\
../../ip_cores/rtl/clock_generator_ddr_s2_diff.vhd
\
../../ip_cores/rtl/clock_generator_pll_s2_diff.vhd
\
../../ip_cores/rtl/dma_controller.vhd
\
../../ip_cores/rtl/dma_controller_wb_slave.vhd
\
../../ip_cores/rtl/gn4124_core_pkg.vhd
\
../../ip_cores/rtl/l2p_arbiter.vhd
\
../../ip_cores/rtl/l2p_dma_master.vhd
\
../../ip_cores/rtl/p2l_decode32.vhd
\
../../ip_cores/rtl/p2l_dma_master.vhd
\
../../ip_cores/rtl/serdes_1_to_n_clk_ddr_s2_diff.vhd
\
../../ip_cores/rtl/serdes_1_to_n_clk_pll_s2_diff.vhd
\
../../ip_cores/rtl/serdes_1_to_n_data_ddr_s2_se.vhd
\
../../ip_cores/rtl/serdes_1_to_n_data_s2_se.vhd
\
../../ip_cores/rtl/serdes_n_to_1_ddr_s2_diff.vhd
\
../../ip_cores/rtl/serdes_n_to_1_ddr_s2_se.vhd
\
../../ip_cores/rtl/serdes_n_to_1_s2_diff.vhd
\
../../ip_cores/rtl/serdes_n_to_1_s2_se.vhd
\
../../ip_cores/rtl/wbmaster32.vhd
\
../../ip_cores/rtl/spartan6/gn4124_core.vhd
\
../../ip_cores/rtl/spartan6/gn4124_core_private_pkg.vhd
\
../../ip_cores/rtl/spartan6/l2p_ser.vhd
\
../../ip_cores/rtl/spartan6/p2l_des.vhd
\
../../ip_cores/general-cores/modules/common/gencores_pkg.vhd
\
../../ip_cores/general-cores/modules/common/gc_crc_gen.vhd
\
../../ip_cores/general-cores/modules/common/gc_moving_average.vhd
\
../../ip_cores/general-cores/modules/common/gc_extend_pulse.vhd
\
../../ip_cores/general-cores/modules/common/gc_delay_gen.vhd
\
../../ip_cores/general-cores/modules/common/gc_dual_pi_controller.vhd
\
../../ip_cores/general-cores/modules/common/gc_serial_dac.vhd
\
../../ip_cores/general-cores/modules/common/gc_sync_ffs.vhd
\
../../ip_cores/general-cores/modules/genrams/genram_pkg.vhd
\
../../ip_cores/general-cores/modules/wishbone/wishbone_pkg.vhd
\
../../ip_cores/general-cores/modules/wishbone/wb_async_bridge/wb_cpu_bridge.vhd
\
../../ip_cores/general-cores/modules/wishbone/wb_conmax/wb_conmax_pri_dec.vhd
\
../../ip_cores/general-cores/modules/wishbone/wb_conmax/wb_conmax_pri_enc.vhd
\
../../ip_cores/general-cores/modules/wishbone/wb_conmax/wb_conmax_arb.vhd
\
../../ip_cores/general-cores/modules/wishbone/wb_conmax/wb_conmax_msel.vhd
\
../../ip_cores/general-cores/modules/wishbone/wb_conmax/wbconmax_pkg.vhd
\
../../ip_cores/general-cores/modules/wishbone/wb_conmax/wb_conmax_slave_if.vhd
\
../../ip_cores/general-cores/modules/wishbone/wb_conmax/wb_conmax_master_if.vhd
\
../../ip_cores/general-cores/modules/wishbone/wb_conmax/wb_conmax_rf.vhd
\
../../ip_cores/general-cores/modules/wishbone/wb_conmax/wb_conmax_top.vhd
\
../../ip_cores/general-cores/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd
\
../../ip_cores/general-cores/modules/wishbone/wb_simple_timer/wb_tics.vhd
\
../../ip_cores/general-cores/modules/wishbone/wb_uart/uart_async_rx.vhd
\
../../ip_cores/general-cores/modules/wishbone/wb_uart/uart_async_tx.vhd
\
../../ip_cores/general-cores/modules/wishbone/wb_uart/uart_baud_gen.vhd
\
../../ip_cores/general-cores/modules/wishbone/wb_uart/uart_wb_slave.vhd
\
../../ip_cores/general-cores/modules/wishbone/wb_uart/wb_simple_uart.vhd
\
../../ip_cores/general-cores/modules/wishbone/wb_vic/vic_prio_enc.vhd
\
../../ip_cores/general-cores/modules/wishbone/wb_vic/wb_slave_vic.wb
\
../../ip_cores/general-cores/modules/wishbone/wb_vic/wb_vic.vhd
\
../../ip_cores/general-cores/modules/wishbone/wb_spi/spi_clgen.v
\
../../ip_cores/general-cores/modules/wishbone/wb_spi/spi_shift.v
\
../../ip_cores/general-cores/modules/wishbone/wb_spi/spi_top.v
\
../../ip_cores/general-cores/modules/wishbone/wb_virtual_uart/wb_virtual_uart.vhd
\
../../ip_cores/general-cores/modules/wishbone/wb_virtual_uart/wb_virtual_uart_slave.vhd
\
../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_dpssram.vhd
\
../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_eic.vhd
\
../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_fifo_async.vhd
\
../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_fifo_sync.vhd
\
../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_pkg.vhd
\
../../ip_cores/general-cores/modules/genrams/xilinx/generic_async_fifo.vhd
\
../../ip_cores/general-cores/modules/genrams/xilinx/generic_dpram.vhd
\
../../ip_cores/general-cores/modules/genrams/xilinx/generic_spram.vhd
\
../../ip_cores/general-cores/modules/genrams/xilinx/generic_sync_fifo.vhd
\
../../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_v4_1_xst_comp.vhd
\
../../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_v4_1_defaults.vhd
\
../../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_v4_1_pkg.vhd
\
../../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_getinit_pkg.vhd
\
../../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_min_area_pkg.vhd
\
../../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_bindec.vhd
\
../../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_mux.vhd
\
../../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_wrapper_s6.vhd
\
../../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_wrapper_s6_init.vhd
\
../../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_wrapper_s3adsp.vhd
\
../../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_wrapper_s3adsp_init.vhd
\
../../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_wrapper_s3a.vhd
\
../../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_wrapper_s3a_init.vhd
\
../../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_wrapper_v6.vhd
\
../../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_wrapper_v6_init.vhd
\
../../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_wrapper_v5.vhd
\
../../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_wrapper_v5_init.vhd
\
../../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_wrapper_v4.vhd
\
../../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_wrapper_v4_init.vhd
\
../../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_wrapper_s3.vhd
\
../../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_wrapper_s3_init.vhd
\
../../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_width.vhd
\
../../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_generic_cstr.vhd
\
../../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_ecc_encoder.vhd
\
../../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_ecc_decoder.vhd
\
../../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_input_block.vhd
\
../../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_output_block.vhd
\
../../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_top.vhd
\
../../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_v4_1_xst.vhd
\
../../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/fifo_generator_v6_1_pkg.vhd
\
../../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/fifo_generator_v6_1_defaults.vhd
\
../../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/fifo_generator_v6_1_xst_comp.vhd
\
../../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/input_blk.vhd
\
../../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/output_blk.vhd
\
../../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/shft_wrapper.vhd
\
../../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/shft_ram.vhd
\
../../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/dmem.vhd
\
../../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/memory.vhd
\
../../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/compare.vhd
\
../../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/wr_bin_cntr.vhd
\
../../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/rd_bin_cntr.vhd
\
../../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/updn_cntr.vhd
\
../../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/rd_status_flags_as.vhd
\
../../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/rd_status_flags_ss.vhd
\
../../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/rd_pe_as.vhd
\
../../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/rd_pe_ss.vhd
\
../../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/rd_handshaking_flags.vhd
\
../../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/rd_dc_as.vhd
\
../../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/rd_dc_fwft_ext_as.vhd
\
../../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/dc_ss.vhd
\
../../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/dc_ss_fwft.vhd
\
../../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/rd_fwft.vhd
\
../../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/rd_logic.vhd
\
../../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/reset_blk_ramfifo.vhd
\
../../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/clk_x_pntrs.vhd
\
../../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/wr_status_flags_as.vhd
\
../../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/wr_status_flags_ss.vhd
\
../../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/wr_pf_as.vhd
\
../../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/wr_pf_ss.vhd
\
../../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/wr_handshaking_flags.vhd
\
../../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/wr_dc_as.vhd
\
../../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/wr_dc_fwft_ext_as.vhd
\
../../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/wr_logic.vhd
\
../../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/wr_status_flags_sshft.vhd
\
../../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/rd_status_flags_sshft.vhd
\
../../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/wr_pf_sshft.vhd
\
../../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/rd_pe_sshft.vhd
\
../../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/logic_sshft.vhd
\
../../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/fifo_generator_ramfifo.vhd
\
../../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/fifo_generator_v6_1_comps_builtin.vhd
\
../../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/delay.vhd
\
../../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/clk_x_pntrs_builtin.vhd
\
../../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/bin_cntr.vhd
\
../../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/logic_builtin.vhd
\
../../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/reset_builtin.vhd
\
../../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/builtin_prim.vhd
\
../../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/builtin_extdepth.vhd
\
../../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/builtin_top.vhd
\
../../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/builtin_prim_v6.vhd
\
../../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/builtin_extdepth_v6.vhd
\
../../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/builtin_top_v6.vhd
\
../../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/fifo_generator_v6_1_builtin.vhd
\
../../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/rgtw.vhd
\
../../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/wgtr.vhd
\
../../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/input_block_fifo16_patch.vhd
\
../../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/output_block_fifo16_patch.vhd
\
../../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/fifo16_patch_top.vhd
\
../../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/fifo_generator_v6_1_fifo16_patch.vhd
\
../../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/fifo_generator_v6_1_xst.vhd
\
../../ip_cores/wr-cores/platform/xilinx/wr_gtp_phy/gtp_bitslide.vhd
\
../../ip_cores/wr-cores/platform/xilinx/wr_gtp_phy/gtp_phase_align.vhd
\
../../ip_cores/wr-cores/platform/xilinx/wr_gtp_phy/whiterabbitgtp_wrapper.vhd
\
../../ip_cores/wr-cores/platform/xilinx/wr_gtp_phy/whiterabbitgtp_wrapper_tile.vhd
\
../../ip_cores/wr-cores/platform/xilinx/wr_gtp_phy/wr_gtp_phy_spartan6.vhd
\
../../ip_cores/wr-cores/modules/timing/dmtd_phase_meas.vhd
\
../../ip_cores/wr-cores/modules/timing/dmtd_with_deglitcher.vhd
\
../../ip_cores/wr-cores/modules/timing/multi_dmtd_with_deglitcher.vhd
\
../../ip_cores/wr-cores/modules/timing/hpll_period_detect.vhd
\
../../ip_cores/wr-cores/modules/wr_mini_nic/minic_packet_buffer.vhd
\
../../ip_cores/wr-cores/modules/wr_mini_nic/minic_wb_slave.vhd
\
../../ip_cores/wr-cores/modules/wr_mini_nic/wr_mini_nic.vhd
\
../../ip_cores/wr-cores/modules/wr_softpll/softpll_wb.vhd
\
../../ip_cores/wr-cores/modules/wr_softpll/wr_softpll.vhd
\
../../ip_cores/wr-cores/modules/wrc_lm32/wrc_lm32.vhd
\
../../ip_cores/wr-cores/modules/wrc_lm32/lm32_cpu.v
\
../../ip_cores/wr-cores/modules/wrc_lm32/lm32_addsub.v
\
../../ip_cores/wr-cores/modules/wrc_lm32/lm32_top.v
\
../../ip_cores/wr-cores/modules/wrc_lm32/lm32_instruction_unit.v
\
../../ip_cores/wr-cores/modules/wrc_lm32/lm32_decoder.v
\
../../ip_cores/wr-cores/modules/wrc_lm32/lm32_load_store_unit.v
\
../../ip_cores/wr-cores/modules/wrc_lm32/lm32_adder.v
\
../../ip_cores/wr-cores/modules/wrc_lm32/lm32_logic_op.v
\
../../ip_cores/wr-cores/modules/wrc_lm32/lm32_shifter.v
\
../../ip_cores/wr-cores/modules/wrc_lm32/lm32_multiplier.v
\
../../ip_cores/wr-cores/modules/wrc_lm32/lm32_interrupt.v
\
../../ip_cores/wr-cores/modules/wrc_lm32/lm32_dp_ram.v
\
../../ip_cores/wr-cores/modules/wrsw_endpoint/endpoint_pkg.vhd
\
../../ip_cores/wr-cores/modules/wrsw_endpoint/ep_enc_8b10b.vhd
\
../../ip_cores/wr-cores/modules/wrsw_endpoint/ep_dec_8b10b.vhd
\
../../ip_cores/wr-cores/modules/wrsw_endpoint/ep_rx_pcs_tbi.vhd
\
../../ip_cores/wr-cores/modules/wrsw_endpoint/ep_tx_pcs_tbi.vhd
\
../../ip_cores/wr-cores/modules/wrsw_endpoint/ep_autonegotiation.vhd
\
../../ip_cores/wr-cores/modules/wrsw_endpoint/ep_pcs_tbi_mdio_wb.vhd
\
../../ip_cores/wr-cores/modules/wrsw_endpoint/ep_1000basex_pcs.vhd
\
../../ip_cores/wr-cores/modules/wrsw_endpoint/ep_rx_crc_size_check.vhd
\
../../ip_cores/wr-cores/modules/wrsw_endpoint/ep_rx_deframer.vhd
\
../../ip_cores/wr-cores/modules/wrsw_endpoint/ep_tx_framer.vhd
\
../../ip_cores/wr-cores/modules/wrsw_endpoint/ep_flow_control.vhd
\
../../ip_cores/wr-cores/modules/wrsw_endpoint/ep_timestamping_unit.vhd
\
../../ip_cores/wr-cores/modules/wrsw_endpoint/ep_rmon_counters.vhd
\
../../ip_cores/wr-cores/modules/wrsw_endpoint/ep_rx_buffer.vhd
\
../../ip_cores/wr-cores/modules/wrsw_endpoint/ep_sync_detect.vhd
\
../../ip_cores/wr-cores/modules/wrsw_endpoint/ep_wishbone_controller.vhd
\
../../ip_cores/wr-cores/modules/wrsw_endpoint/ep_ts_counter.vhd
\
../../ip_cores/wr-cores/modules/wrsw_endpoint/wrsw_endpoint.vhd
\
../../ip_cores/wr-cores/modules/wrsw_pps_gen/pps_gen_wb.vhd
\
../../ip_cores/wr-cores/modules/wrsw_pps_gen/wrsw_pps_gen.vhd
\
../../ip_cores/wr-cores/modules/wrc_lm32/lm32_include.v
\
../../ip_cores/wr-cores/modules/wrc_lm32/system_conf.v
\
../../ip_cores/wr-cores/modules/wrc_lm32/lm32_functions.v
\
../../ip_cores/general-cores/modules/wishbone/wb_spi/timescale.v
\
../../ip_cores/general-cores/modules/wishbone/wb_spi/spi_defines.v
\
run.tcl
\
finedelay_spec_1_1.xise
#target for running simulation in the remote location
remote
:
__send __do_synthesis __send_back
__send_back
:
__do_synthesis
__do_synthesis
:
__send
__send
:
ssh
$(USER)
@
$(SERVER)
'mkdir -p
$(R_NAME)
'
rsync
-Rav
$
(
foreach file,
$(FILES)
,
$(
shell
readlink
-f
$(file))
)
$(USER)
@
$(SERVER)
:
$(R_NAME)
__do_synthesis
:
ssh
$(USER)
@
$(SERVER)
'cd
$(R_NAME)$(CWD)
&& xtclsh run.tcl'
__send_back
:
cd
..
&&
rsync
-av
$(USER)
@
$(SERVER)
:
$(R_NAME)$(CWD)
.
&&
cd
$(CWD)
#target for removing stuff from the remote location
cleanremote
:
ssh
$(USER)
@
$(SERVER)
'rm -rf
$(R_NAME)
'
hdl/syn/spec_1_1/Manifest.py
0 → 100644
View file @
b1c4c30c
target
=
"xilinx"
action
=
"synthesis"
fetchto
=
"../../ip_cores"
syn_device
=
"xc6slx45t"
syn_grade
=
"-3"
syn_package
=
"fgg484"
syn_top
=
"spec_top"
syn_project
=
"finedelay_spec_1_1.xise"
modules
=
{
"local"
:
[
"../../top/spec_1_1"
]
}
hdl/syn/spec_1_1/finedelay_spec_1_1.xise
0 → 100644
View file @
b1c4c30c
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
<project
xmlns=
"http://www.xilinx.com/XMLSchema"
xmlns:xil_pn=
"http://www.xilinx.com/XMLSchema"
>
<header>
<!-- ISE source project file created by Project Navigator. -->
<!-- -->
<!-- This file contains project source information including a list of -->
<!-- project source files, project and process properties. This file, -->
<!-- along with the project source files, is sufficient to open and -->
<!-- implement in ISE Project Navigator. -->
<!-- -->
<!-- Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved. -->
</header>
<version
xil_pn:ise_version=
"13.1"
xil_pn:schema_version=
"2"
/>
<autoManagedFiles>
<!-- The following files are identified by `include statements in verilog -->
<!-- source files and are automatically managed by Project Navigator. -->
<!-- -->
<!-- Do not hand-edit this section, as it will be overwritten when the -->
<!-- project is analyzed based on files automatically identified as -->
<!-- include files. -->
</autoManagedFiles>
<bindings/>
<properties>
<property
xil_pn:name=
"AES Initial Vector spartan6"
xil_pn:value=
""
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"AES Key (Hex String) spartan6"
xil_pn:value=
""
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Add I/O Buffers"
xil_pn:value=
"true"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Allow Logic Optimization Across Hierarchy"
xil_pn:value=
"false"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Allow SelectMAP Pins to Persist"
xil_pn:value=
"false"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Allow Unexpanded Blocks"
xil_pn:value=
"false"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Allow Unmatched LOC Constraints"
xil_pn:value=
"false"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Allow Unmatched Timing Group Constraints"
xil_pn:value=
"false"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Analysis Effort Level"
xil_pn:value=
"Standard"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Asynchronous To Synchronous"
xil_pn:value=
"false"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Auto Implementation Compile Order"
xil_pn:value=
"false"
xil_pn:valueState=
"non-default"
/>
<property
xil_pn:name=
"Auto Implementation Top"
xil_pn:value=
"false"
xil_pn:valueState=
"non-default"
/>
<property
xil_pn:name=
"Automatic BRAM Packing"
xil_pn:value=
"false"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Automatically Insert glbl Module in the Netlist"
xil_pn:value=
"true"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Automatically Run Generate Target PROM/ACE File"
xil_pn:value=
"false"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"BRAM Utilization Ratio"
xil_pn:value=
"100"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Bring Out Global Set/Reset Net as a Port"
xil_pn:value=
"false"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Bring Out Global Tristate Net as a Port"
xil_pn:value=
"false"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Bus Delimiter"
xil_pn:value=
"<>"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Case"
xil_pn:value=
"Maintain"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Case Implementation Style"
xil_pn:value=
"None"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Change Device Speed To"
xil_pn:value=
"-3"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Change Device Speed To Post Trace"
xil_pn:value=
"-3"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Combinatorial Logic Optimization"
xil_pn:value=
"false"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Compile EDK Simulation Library"
xil_pn:value=
"false"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Compile SIMPRIM (Timing) Simulation Library"
xil_pn:value=
"true"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Compile UNISIM (Functional) Simulation Library"
xil_pn:value=
"true"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Compile XilinxCoreLib (CORE Generator) Simulation Library"
xil_pn:value=
"true"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Compile for HDL Debugging"
xil_pn:value=
"true"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Configuration Pin Done"
xil_pn:value=
"Pull Up"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Configuration Pin Program"
xil_pn:value=
"Pull Up"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Configuration Rate spartan6"
xil_pn:value=
"2"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Correlate Output to Input Design"
xil_pn:value=
"false"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Create ASCII Configuration File"
xil_pn:value=
"false"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Create Binary Configuration File"
xil_pn:value=
"true"
xil_pn:valueState=
"non-default"
/>
<property
xil_pn:name=
"Create Bit File"
xil_pn:value=
"true"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Create I/O Pads from Ports"
xil_pn:value=
"false"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Create IEEE 1532 Configuration File spartan6"
xil_pn:value=
"false"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Create Logic Allocation File"
xil_pn:value=
"false"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Create Mask File"
xil_pn:value=
"false"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Create ReadBack Data Files"
xil_pn:value=
"false"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Cross Clock Analysis"
xil_pn:value=
"false"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"DSP Utilization Ratio"
xil_pn:value=
"100"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Delay Values To Be Read from SDF"
xil_pn:value=
"Setup Time"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Device"
xil_pn:value=
"xc6slx45t"
xil_pn:valueState=
"non-default"
/>
<property
xil_pn:name=
"Device Family"
xil_pn:value=
"Spartan6"
xil_pn:valueState=
"non-default"
/>
<property
xil_pn:name=
"Device Speed Grade/Select ABS Minimum"
xil_pn:value=
"-3"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Disable Detailed Package Model Insertion"
xil_pn:value=
"false"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Do Not Escape Signal and Instance Names in Netlist"
xil_pn:value=
"false"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Done (Output Events)"
xil_pn:value=
"Default (4)"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Drive Awake Pin During Suspend/Wake Sequence spartan6"
xil_pn:value=
"false"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Drive Done Pin High"
xil_pn:value=
"false"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Enable BitStream Compression"
xil_pn:value=
"true"
xil_pn:valueState=
"non-default"
/>
<property
xil_pn:name=
"Enable Cyclic Redundancy Checking (CRC) spartan6"
xil_pn:value=
"true"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Enable Debugging of Serial Mode BitStream"
xil_pn:value=
"false"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Enable External Master Clock spartan6"
xil_pn:value=
"false"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Enable Internal Done Pipe"
xil_pn:value=
"false"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Enable Message Filtering"
xil_pn:value=
"false"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Enable Multi-Pin Wake-Up Suspend Mode spartan6"
xil_pn:value=
"false"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Enable Multi-Threading"
xil_pn:value=
"2"
xil_pn:valueState=
"non-default"
/>
<property
xil_pn:name=
"Enable Multi-Threading par spartan6"
xil_pn:value=
"Off"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Enable Outputs (Output Events)"
xil_pn:value=
"Default (5)"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Enable Suspend/Wake Global Set/Reset spartan6"
xil_pn:value=
"false"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Encrypt Bitstream spartan6"
xil_pn:value=
"false"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Encrypt Key Select spartan6"
xil_pn:value=
"BBRAM"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Equivalent Register Removal Map"
xil_pn:value=
"true"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Equivalent Register Removal XST"
xil_pn:value=
"true"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Exclude Compilation of Deprecated EDK Cores"
xil_pn:value=
"true"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Exclude Compilation of EDK Sub-Libraries"
xil_pn:value=
"false"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Extra Cost Tables Map"
xil_pn:value=
"0"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Extra Effort (Highest PAR level only)"
xil_pn:value=
"None"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"FPGA Start-Up Clock"
xil_pn:value=
"CCLK"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"FSM Encoding Algorithm"
xil_pn:value=
"Auto"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"FSM Style"
xil_pn:value=
"LUT"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Filter Files From Compile Order"
xil_pn:value=
"true"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Flatten Output Netlist"
xil_pn:value=
"false"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Functional Model Target Language ArchWiz"
xil_pn:value=
"Verilog"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Functional Model Target Language Coregen"
xil_pn:value=
"Verilog"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Functional Model Target Language Schematic"
xil_pn:value=
"Verilog"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"GTS Cycle During Suspend/Wakeup Sequence spartan6"
xil_pn:value=
"4"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"GWE Cycle During Suspend/Wakeup Sequence spartan6"
xil_pn:value=
"5"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Generate Architecture Only (No Entity Declaration)"
xil_pn:value=
"false"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Generate Asynchronous Delay Report"
xil_pn:value=
"false"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Generate Clock Region Report"
xil_pn:value=
"false"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Generate Constraints Interaction Report"
xil_pn:value=
"false"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Generate Constraints Interaction Report Post Trace"
xil_pn:value=
"false"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Generate Datasheet Section"
xil_pn:value=
"true"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Generate Datasheet Section Post Trace"
xil_pn:value=
"true"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Generate Detailed MAP Report"
xil_pn:value=
"false"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Generate Multiple Hierarchical Netlist Files"
xil_pn:value=
"false"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Generate Post-Place & Route Power Report"
xil_pn:value=
"false"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Generate Post-Place & Route Simulation Model"
xil_pn:value=
"false"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Generate RTL Schematic"
xil_pn:value=
"Yes"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Generate SAIF File for Power Optimization/Estimation Par"
xil_pn:value=
"false"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Generate Testbench File"
xil_pn:value=
"false"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Generate Timegroups Section"
xil_pn:value=
"false"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Generate Timegroups Section Post Trace"
xil_pn:value=
"false"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Generics, Parameters"
xil_pn:value=
""
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Global Optimization Goal"
xil_pn:value=
"AllClockNets"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Global Optimization map"
xil_pn:value=
"Off"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Global Set/Reset Port Name"
xil_pn:value=
"GSR_PORT"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Global Tristate Port Name"
xil_pn:value=
"GTS_PORT"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Hierarchy Separator"
xil_pn:value=
"/"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"ISim UUT Instance Name"
xil_pn:value=
"UUT"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Ignore User Timing Constraints Map"
xil_pn:value=
"false"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Ignore User Timing Constraints Par"
xil_pn:value=
"false"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Implementation Top"
xil_pn:value=
"Architecture|spec_top"
xil_pn:valueState=
"non-default"
/>
<property
xil_pn:name=
"Implementation Top Instance Path"
xil_pn:value=
"/spec_top"
xil_pn:valueState=
"non-default"
/>
<property
xil_pn:name=
"Include 'uselib Directive in Verilog File"
xil_pn:value=
"false"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Include SIMPRIM Models in Verilog File"
xil_pn:value=
"false"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Include UNISIM Models in Verilog File"
xil_pn:value=
"false"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Include sdf_annotate task in Verilog File"
xil_pn:value=
"true"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Incremental Compilation"
xil_pn:value=
"true"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Insert Buffers to Prevent Pulse Swallowing"
xil_pn:value=
"true"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Instantiation Template Target Language Xps"
xil_pn:value=
"Verilog"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"JTAG Pin TCK"
xil_pn:value=
"Pull Up"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"JTAG Pin TDI"
xil_pn:value=
"Pull Up"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"JTAG Pin TDO"
xil_pn:value=
"Pull Up"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"JTAG Pin TMS"
xil_pn:value=
"Pull Up"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Keep Hierarchy"
xil_pn:value=
"No"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"LUT Combining Map"
xil_pn:value=
"Off"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"LUT Combining Xst"
xil_pn:value=
"Auto"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Language"
xil_pn:value=
"VHDL"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Last Applied Goal"
xil_pn:value=
"Balanced"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Last Applied Strategy"
xil_pn:value=
"Xilinx Default (unlocked)"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Last Unlock Status"
xil_pn:value=
"false"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Launch SDK after Export"
xil_pn:value=
"true"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Library for Verilog Sources"
xil_pn:value=
""
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Load glbl"
xil_pn:value=
"true"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Manual Implementation Compile Order"
xil_pn:value=
"true"
xil_pn:valueState=
"non-default"
/>
<property
xil_pn:name=
"Map Slice Logic into Unused Block RAMs"
xil_pn:value=
"false"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Mask Pins for Multi-Pin Wake-Up Suspend Mode spartan6"
xil_pn:value=
"0x00"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Max Fanout"
xil_pn:value=
"100000"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Maximum Compression"
xil_pn:value=
"false"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Maximum Number of Lines in Report"
xil_pn:value=
"1000"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Maximum Signal Name Length"
xil_pn:value=
"20"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Move First Flip-Flop Stage"
xil_pn:value=
"true"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Move Last Flip-Flop Stage"
xil_pn:value=
"true"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"MultiBoot: Next Configuration Mode spartan6"
xil_pn:value=
"001"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"MultiBoot: Starting Address for Golden Configuration spartan6"
xil_pn:value=
"0x00000000"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"MultiBoot: Starting Address for Next Configuration spartan6"
xil_pn:value=
"0x00000000"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"MultiBoot: Use New Mode for Next Configuration spartan6"
xil_pn:value=
"true"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"MultiBoot: User-Defined Register for Failsafe Scheme spartan6"
xil_pn:value=
"0x0000"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Netlist Hierarchy"
xil_pn:value=
"As Optimized"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Netlist Translation Type"
xil_pn:value=
"Timestamp"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Number of Clock Buffers"
xil_pn:value=
"16"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Number of Paths in Error/Verbose Report"
xil_pn:value=
"3"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Number of Paths in Error/Verbose Report Post Trace"
xil_pn:value=
"3"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Optimization Effort spartan6"
xil_pn:value=
"Normal"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Optimization Goal"
xil_pn:value=
"Speed"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Optimize Instantiated Primitives"
xil_pn:value=
"false"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Other Bitgen Command Line Options spartan6"
xil_pn:value=
""
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Other Compiler Options"
xil_pn:value=
""
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Other Compiler Options Map"
xil_pn:value=
""
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Other Compiler Options Par"
xil_pn:value=
""
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Other Compiler Options Translate"
xil_pn:value=
""
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Other Compxlib Command Line Options"
xil_pn:value=
""
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Other Map Command Line Options"
xil_pn:value=
""
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Other NETGEN Command Line Options"
xil_pn:value=
""
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Other Ngdbuild Command Line Options"
xil_pn:value=
""
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Other Place & Route Command Line Options"
xil_pn:value=
""
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Other Simulator Commands Behavioral"
xil_pn:value=
""
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Other Simulator Commands Post-Map"
xil_pn:value=
""
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Other Simulator Commands Post-Route"
xil_pn:value=
""
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Other Simulator Commands Post-Translate"
xil_pn:value=
""
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Other XPWR Command Line Options"
xil_pn:value=
""
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Other XST Command Line Options"
xil_pn:value=
""
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Output Extended Identifiers"
xil_pn:value=
"false"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Output File Name"
xil_pn:value=
"spec_top"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Overwrite Compiled Libraries"
xil_pn:value=
"false"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Pack I/O Registers into IOBs"
xil_pn:value=
"Auto"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Pack I/O Registers/Latches into IOBs"
xil_pn:value=
"Off"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Package"
xil_pn:value=
"fgg484"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Perform Advanced Analysis"
xil_pn:value=
"false"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Perform Advanced Analysis Post Trace"
xil_pn:value=
"false"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Perform Timing-Driven Packing and Placement"
xil_pn:value=
"false"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Place & Route Effort Level (Overall)"
xil_pn:value=
"High"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Place And Route Mode"
xil_pn:value=
"Normal Place and Route"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Place MultiBoot Settings into Bitstream spartan6"
xil_pn:value=
"false"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Placer Effort Level Map"
xil_pn:value=
"High"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Placer Extra Effort Map"
xil_pn:value=
"None"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Port to be used"
xil_pn:value=
"Auto - default"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Post Map Simulation Model Name"
xil_pn:value=
"spec_top_map.v"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Post Place & Route Simulation Model Name"
xil_pn:value=
"spec_top_timesim.v"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Post Synthesis Simulation Model Name"
xil_pn:value=
"spec_top_synthesis.v"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Post Translate Simulation Model Name"
xil_pn:value=
"spec_top_translate.v"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Power Reduction Map spartan6"
xil_pn:value=
"Off"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Power Reduction Par"
xil_pn:value=
"false"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Power Reduction Xst"
xil_pn:value=
"false"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Preferred Language"
xil_pn:value=
"Verilog"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Produce Verbose Report"
xil_pn:value=
"false"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Property Specification in Project File"
xil_pn:value=
"Store all values"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"RAM Extraction"
xil_pn:value=
"true"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"RAM Style"
xil_pn:value=
"Auto"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"ROM Extraction"
xil_pn:value=
"true"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"ROM Style"
xil_pn:value=
"Auto"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Read Cores"
xil_pn:value=
"true"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Reduce Control Sets"
xil_pn:value=
"Auto"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Regenerate Core"
xil_pn:value=
"Under Current Project Setting"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Register Balancing"
xil_pn:value=
"No"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Register Duplication Map"
xil_pn:value=
"Off"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Register Duplication Xst"
xil_pn:value=
"true"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Register Ordering spartan6"
xil_pn:value=
"4"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Release Write Enable (Output Events)"
xil_pn:value=
"Default (6)"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Rename Design Instance in Testbench File to"
xil_pn:value=
"UUT"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Rename Top Level Architecture To"
xil_pn:value=
"Structure"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Rename Top Level Entity to"
xil_pn:value=
""
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Rename Top Level Module To"
xil_pn:value=
""
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Report Fastest Path(s) in Each Constraint"
xil_pn:value=
"true"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Report Fastest Path(s) in Each Constraint Post Trace"
xil_pn:value=
"true"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Report Paths by Endpoint"
xil_pn:value=
"3"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Report Paths by Endpoint Post Trace"
xil_pn:value=
"3"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Report Type"
xil_pn:value=
"Verbose Report"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Report Type Post Trace"
xil_pn:value=
"Verbose Report"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Report Unconstrained Paths"
xil_pn:value=
""
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Report Unconstrained Paths Post Trace"
xil_pn:value=
""
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Reset On Configuration Pulse Width"
xil_pn:value=
"100"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Resource Sharing"
xil_pn:value=
"true"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Retain Hierarchy"
xil_pn:value=
"true"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Retiming Map"
xil_pn:value=
"false"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Retry Configuration if CRC Error Occurs spartan6"
xil_pn:value=
"false"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Run Design Rules Checker (DRC)"
xil_pn:value=
"true"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Run for Specified Time"
xil_pn:value=
"true"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Run for Specified Time Map"
xil_pn:value=
"true"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Run for Specified Time Par"
xil_pn:value=
"true"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Run for Specified Time Translate"
xil_pn:value=
"true"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Safe Implementation"
xil_pn:value=
"No"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Security"
xil_pn:value=
"Enable Readback and Reconfiguration"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Selected Simulation Root Source Node Behavioral"
xil_pn:value=
""
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Selected Simulation Root Source Node Post-Map"
xil_pn:value=
""
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Selected Simulation Root Source Node Post-Route"
xil_pn:value=
""
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Selected Simulation Root Source Node Post-Translate"
xil_pn:value=
""
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Selected Simulation Source Node"
xil_pn:value=
"UUT"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Set SPI Configuration Bus Width spartan6"
xil_pn:value=
"1"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Setup External Master Clock Division spartan6"
xil_pn:value=
"1"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Shift Register Extraction"
xil_pn:value=
"true"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Shift Register Minimum Size spartan6"
xil_pn:value=
"2"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Show All Models"
xil_pn:value=
"false"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Simulation Model Target"
xil_pn:value=
"Verilog"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Simulation Run Time ISim"
xil_pn:value=
"1000 ns"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Simulation Run Time Map"
xil_pn:value=
"1000 ns"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Simulation Run Time Par"
xil_pn:value=
"1000 ns"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Simulation Run Time Translate"
xil_pn:value=
"1000 ns"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Simulator"
xil_pn:value=
"ISim (VHDL/Verilog)"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Slice Utilization Ratio"
xil_pn:value=
"100"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Specify 'define Macro Name and Value"
xil_pn:value=
""
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Specify Top Level Instance Names Behavioral"
xil_pn:value=
"Default"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Specify Top Level Instance Names Post-Map"
xil_pn:value=
"Default"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Specify Top Level Instance Names Post-Route"
xil_pn:value=
"Default"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Specify Top Level Instance Names Post-Translate"
xil_pn:value=
"Default"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Speed Grade"
xil_pn:value=
"-3"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Starting Placer Cost Table (1-100) Map spartan6"
xil_pn:value=
"1"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Synthesis Tool"
xil_pn:value=
"XST (VHDL/Verilog)"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Target Simulator"
xil_pn:value=
"Please Specify"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Timing Mode Map"
xil_pn:value=
"Performance Evaluation"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Timing Mode Par"
xil_pn:value=
"Performance Evaluation"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Top-Level Module Name in Output Netlist"
xil_pn:value=
""
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Top-Level Source Type"
xil_pn:value=
"HDL"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Trim Unconnected Signals"
xil_pn:value=
"true"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Tristate On Configuration Pulse Width"
xil_pn:value=
"0"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Unused IOB Pins"
xil_pn:value=
"Pull Down"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Use 64-bit PlanAhead on 64-bit Systems"
xil_pn:value=
"true"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Use Clock Enable"
xil_pn:value=
"Auto"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Use Custom Project File Behavioral"
xil_pn:value=
"false"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Use Custom Project File Post-Map"
xil_pn:value=
"false"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Use Custom Project File Post-Route"
xil_pn:value=
"false"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Use Custom Project File Post-Translate"
xil_pn:value=
"false"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Use Custom Simulation Command File Behavioral"
xil_pn:value=
"false"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Use Custom Simulation Command File Map"
xil_pn:value=
"false"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Use Custom Simulation Command File Par"
xil_pn:value=
"false"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Use Custom Simulation Command File Translate"
xil_pn:value=
"false"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Use Custom Waveform Configuration File Behav"
xil_pn:value=
"false"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Use Custom Waveform Configuration File Map"
xil_pn:value=
"false"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Use Custom Waveform Configuration File Par"
xil_pn:value=
"false"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Use Custom Waveform Configuration File Translate"
xil_pn:value=
"false"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Use DSP Block spartan6"
xil_pn:value=
"Auto"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Use LOC Constraints"
xil_pn:value=
"true"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Use RLOC Constraints"
xil_pn:value=
"Yes"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Use Smart Guide"
xil_pn:value=
"false"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Use Synchronous Reset"
xil_pn:value=
"Auto"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Use Synchronous Set"
xil_pn:value=
"Auto"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Use Synthesis Constraints File"
xil_pn:value=
"true"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"User Browsed Strategy Files"
xil_pn:value=
""
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"UserID Code (8 Digit Hexadecimal)"
xil_pn:value=
"0xFFFFFFFF"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"VCCAUX Voltage Level spartan6"
xil_pn:value=
"2.5V"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"VHDL Source Analysis Standard"
xil_pn:value=
"VHDL-93"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Value Range Check"
xil_pn:value=
"false"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Verilog Macros"
xil_pn:value=
""
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Wait for DCM and PLL Lock (Output Events) spartan6"
xil_pn:value=
"Default (NoWait)"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Wakeup Clock spartan6"
xil_pn:value=
"Startup Clock"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Watchdog Timer Value spartan6"
xil_pn:value=
"0xFFFF"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Working Directory"
xil_pn:value=
"."
xil_pn:valueState=
"non-default"
/>
<property
xil_pn:name=
"Write Timing Constraints"
xil_pn:value=
"false"
xil_pn:valueState=
"default"
/>
<!-- -->
<!-- The following properties are for internal use only. These should not be modified.-->
<!-- -->
<property
xil_pn:name=
"PROP_BehavioralSimTop"
xil_pn:value=
""
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"PROP_DesignName"
xil_pn:value=
"finedelay_spec_1_1"
xil_pn:valueState=
"non-default"
/>
<property
xil_pn:name=
"PROP_DevFamilyPMName"
xil_pn:value=
"spartan6"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"PROP_FPGAConfiguration"
xil_pn:value=
"FPGAConfiguration"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"PROP_PostMapSimTop"
xil_pn:value=
""
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"PROP_PostParSimTop"
xil_pn:value=
""
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"PROP_PostSynthSimTop"
xil_pn:value=
""
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"PROP_PostXlateSimTop"
xil_pn:value=
""
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"PROP_PreSynthesis"
xil_pn:value=
"PreSynthesis"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"PROP_intProjectCreationTimestamp"
xil_pn:value=
"2011-06-01T17:22:55"
xil_pn:valueState=
"non-default"
/>
<property
xil_pn:name=
"PROP_intWbtProjectID"
xil_pn:value=
"F847B25A7A1F69D9DE3E99AD4776B79D"
xil_pn:valueState=
"non-default"
/>
<property
xil_pn:name=
"PROP_intWorkingDirLocWRTProjDir"
xil_pn:value=
"Same"
xil_pn:valueState=
"non-default"
/>
<property
xil_pn:name=
"PROP_intWorkingDirUsed"
xil_pn:value=
"No"
xil_pn:valueState=
"non-default"
/>
</properties>
<libraries>
<library
xil_pn:name=
"blk_mem_gen_v4_1"
/>
<library
xil_pn:name=
"fifo_generator_v6_1"
/>
</libraries>
<files>
<file
xil_pn:name=
"../../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_v4_1_xst_comp.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"1"
/>
<library
xil_pn:name=
"blk_mem_gen_v4_1"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_v4_1_defaults.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"2"
/>
<library
xil_pn:name=
"blk_mem_gen_v4_1"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_v4_1_pkg.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"3"
/>
<library
xil_pn:name=
"blk_mem_gen_v4_1"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_getinit_pkg.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"4"
/>
<library
xil_pn:name=
"blk_mem_gen_v4_1"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_min_area_pkg.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"5"
/>
<library
xil_pn:name=
"blk_mem_gen_v4_1"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_bindec.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"6"
/>
<library
xil_pn:name=
"blk_mem_gen_v4_1"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_mux.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"7"
/>
<library
xil_pn:name=
"blk_mem_gen_v4_1"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_wrapper_s6.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"8"
/>
<library
xil_pn:name=
"blk_mem_gen_v4_1"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_wrapper_s6_init.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"9"
/>
<library
xil_pn:name=
"blk_mem_gen_v4_1"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_wrapper_s3adsp.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"10"
/>
<library
xil_pn:name=
"blk_mem_gen_v4_1"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_wrapper_s3adsp_init.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"11"
/>
<library
xil_pn:name=
"blk_mem_gen_v4_1"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_wrapper_s3a.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"12"
/>
<library
xil_pn:name=
"blk_mem_gen_v4_1"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_wrapper_s3a_init.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"13"
/>
<library
xil_pn:name=
"blk_mem_gen_v4_1"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_wrapper_v6.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"14"
/>
<library
xil_pn:name=
"blk_mem_gen_v4_1"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_wrapper_v6_init.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"15"
/>
<library
xil_pn:name=
"blk_mem_gen_v4_1"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_wrapper_v5.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"16"
/>
<library
xil_pn:name=
"blk_mem_gen_v4_1"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_wrapper_v5_init.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"17"
/>
<library
xil_pn:name=
"blk_mem_gen_v4_1"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_wrapper_v4.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"18"
/>
<library
xil_pn:name=
"blk_mem_gen_v4_1"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_wrapper_v4_init.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"19"
/>
<library
xil_pn:name=
"blk_mem_gen_v4_1"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_wrapper_s3.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"20"
/>
<library
xil_pn:name=
"blk_mem_gen_v4_1"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_wrapper_s3_init.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"21"
/>
<library
xil_pn:name=
"blk_mem_gen_v4_1"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_width.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"22"
/>
<library
xil_pn:name=
"blk_mem_gen_v4_1"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_generic_cstr.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"23"
/>
<library
xil_pn:name=
"blk_mem_gen_v4_1"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_ecc_encoder.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"24"
/>
<library
xil_pn:name=
"blk_mem_gen_v4_1"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_ecc_decoder.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"25"
/>
<library
xil_pn:name=
"blk_mem_gen_v4_1"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_input_block.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"26"
/>
<library
xil_pn:name=
"blk_mem_gen_v4_1"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_output_block.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"27"
/>
<library
xil_pn:name=
"blk_mem_gen_v4_1"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_top.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"28"
/>
<library
xil_pn:name=
"blk_mem_gen_v4_1"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_v4_1_xst.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"29"
/>
<library
xil_pn:name=
"blk_mem_gen_v4_1"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/fifo_generator_v6_1_pkg.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"30"
/>
<library
xil_pn:name=
"fifo_generator_v6_1"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/fifo_generator_v6_1_defaults.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"31"
/>
<library
xil_pn:name=
"fifo_generator_v6_1"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/fifo_generator_v6_1_xst_comp.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"32"
/>
<library
xil_pn:name=
"fifo_generator_v6_1"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/input_blk.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"33"
/>
<library
xil_pn:name=
"fifo_generator_v6_1"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/output_blk.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"34"
/>
<library
xil_pn:name=
"fifo_generator_v6_1"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/shft_wrapper.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"35"
/>
<library
xil_pn:name=
"fifo_generator_v6_1"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/shft_ram.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"36"
/>
<library
xil_pn:name=
"fifo_generator_v6_1"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/dmem.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"37"
/>
<library
xil_pn:name=
"fifo_generator_v6_1"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/memory.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"38"
/>
<library
xil_pn:name=
"fifo_generator_v6_1"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/compare.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"39"
/>
<library
xil_pn:name=
"fifo_generator_v6_1"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/wr_bin_cntr.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"40"
/>
<library
xil_pn:name=
"fifo_generator_v6_1"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/rd_bin_cntr.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"41"
/>
<library
xil_pn:name=
"fifo_generator_v6_1"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/updn_cntr.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"42"
/>
<library
xil_pn:name=
"fifo_generator_v6_1"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/rd_status_flags_as.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"43"
/>
<library
xil_pn:name=
"fifo_generator_v6_1"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/rd_status_flags_ss.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"44"
/>
<library
xil_pn:name=
"fifo_generator_v6_1"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/rd_pe_as.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"45"
/>
<library
xil_pn:name=
"fifo_generator_v6_1"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/rd_pe_ss.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"46"
/>
<library
xil_pn:name=
"fifo_generator_v6_1"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/rd_handshaking_flags.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"47"
/>
<library
xil_pn:name=
"fifo_generator_v6_1"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/rd_dc_as.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"48"
/>
<library
xil_pn:name=
"fifo_generator_v6_1"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/rd_dc_fwft_ext_as.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"49"
/>
<library
xil_pn:name=
"fifo_generator_v6_1"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/dc_ss.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"50"
/>
<library
xil_pn:name=
"fifo_generator_v6_1"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/dc_ss_fwft.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"51"
/>
<library
xil_pn:name=
"fifo_generator_v6_1"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/rd_fwft.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"52"
/>
<library
xil_pn:name=
"fifo_generator_v6_1"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/rd_logic.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"53"
/>
<library
xil_pn:name=
"fifo_generator_v6_1"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/reset_blk_ramfifo.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"54"
/>
<library
xil_pn:name=
"fifo_generator_v6_1"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/clk_x_pntrs.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"55"
/>
<library
xil_pn:name=
"fifo_generator_v6_1"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/wr_status_flags_as.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"56"
/>
<library
xil_pn:name=
"fifo_generator_v6_1"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/wr_status_flags_ss.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"57"
/>
<library
xil_pn:name=
"fifo_generator_v6_1"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/wr_pf_as.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"58"
/>
<library
xil_pn:name=
"fifo_generator_v6_1"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/wr_pf_ss.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"59"
/>
<library
xil_pn:name=
"fifo_generator_v6_1"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/wr_handshaking_flags.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"60"
/>
<library
xil_pn:name=
"fifo_generator_v6_1"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/wr_dc_as.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"61"
/>
<library
xil_pn:name=
"fifo_generator_v6_1"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/wr_dc_fwft_ext_as.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"62"
/>
<library
xil_pn:name=
"fifo_generator_v6_1"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/wr_logic.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"63"
/>
<library
xil_pn:name=
"fifo_generator_v6_1"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/wr_status_flags_sshft.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"64"
/>
<library
xil_pn:name=
"fifo_generator_v6_1"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/rd_status_flags_sshft.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"65"
/>
<library
xil_pn:name=
"fifo_generator_v6_1"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/wr_pf_sshft.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"66"
/>
<library
xil_pn:name=
"fifo_generator_v6_1"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/rd_pe_sshft.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"67"
/>
<library
xil_pn:name=
"fifo_generator_v6_1"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/logic_sshft.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"68"
/>
<library
xil_pn:name=
"fifo_generator_v6_1"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/fifo_generator_ramfifo.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"69"
/>
<library
xil_pn:name=
"fifo_generator_v6_1"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/fifo_generator_v6_1_comps_builtin.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"70"
/>
<library
xil_pn:name=
"fifo_generator_v6_1"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/delay.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"71"
/>
<library
xil_pn:name=
"fifo_generator_v6_1"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/clk_x_pntrs_builtin.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"72"
/>
<library
xil_pn:name=
"fifo_generator_v6_1"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/bin_cntr.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"73"
/>
<library
xil_pn:name=
"fifo_generator_v6_1"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/logic_builtin.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"74"
/>
<library
xil_pn:name=
"fifo_generator_v6_1"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/reset_builtin.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"75"
/>
<library
xil_pn:name=
"fifo_generator_v6_1"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/builtin_prim.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"76"
/>
<library
xil_pn:name=
"fifo_generator_v6_1"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/builtin_extdepth.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"77"
/>
<library
xil_pn:name=
"fifo_generator_v6_1"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/builtin_top.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"78"
/>
<library
xil_pn:name=
"fifo_generator_v6_1"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/builtin_prim_v6.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"79"
/>
<library
xil_pn:name=
"fifo_generator_v6_1"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/builtin_extdepth_v6.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"80"
/>
<library
xil_pn:name=
"fifo_generator_v6_1"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/builtin_top_v6.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"81"
/>
<library
xil_pn:name=
"fifo_generator_v6_1"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/fifo_generator_v6_1_builtin.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"82"
/>
<library
xil_pn:name=
"fifo_generator_v6_1"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/rgtw.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"83"
/>
<library
xil_pn:name=
"fifo_generator_v6_1"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/wgtr.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"84"
/>
<library
xil_pn:name=
"fifo_generator_v6_1"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/input_block_fifo16_patch.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"85"
/>
<library
xil_pn:name=
"fifo_generator_v6_1"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/output_block_fifo16_patch.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"86"
/>
<library
xil_pn:name=
"fifo_generator_v6_1"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/fifo16_patch_top.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"87"
/>
<library
xil_pn:name=
"fifo_generator_v6_1"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/fifo_generator_v6_1_fifo16_patch.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"88"
/>
<library
xil_pn:name=
"fifo_generator_v6_1"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/fifo_generator_v6_1_xst.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"89"
/>
<library
xil_pn:name=
"fifo_generator_v6_1"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/rtl/gn4124_core_pkg.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"90"
/>
</file>
<file
xil_pn:name=
"../../top/spec_1_1/spec_top_finedelay.ucf"
xil_pn:type=
"FILE_UCF"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"91"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/general-cores/modules/common/gencores_pkg.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"92"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_pkg.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"93"
/>
</file>
<file
xil_pn:name=
"../../rtl/fd_cal_pulse_gen.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"94"
/>
</file>
<file
xil_pn:name=
"../../rtl/fine_delay_pkg.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"95"
/>
</file>
<file
xil_pn:name=
"../../rtl/fd_wbgen2_pkg.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"96"
/>
</file>
<file
xil_pn:name=
"../../rtl/fine_delay_core.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"97"
/>
</file>
<file
xil_pn:name=
"../../rtl/fd_delay_line_driver.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"98"
/>
</file>
<file
xil_pn:name=
"../../rtl/fd_acam_timestamper.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"99"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/rtl/clock_generator_ddr_s2_diff.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"100"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/rtl/clock_generator_pll_s2_diff.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"101"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/rtl/spartan6/gn4124_core_private_pkg.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"102"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/rtl/dma_controller_wb_slave.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"103"
/>
</file>
<file
xil_pn:name=
"../../top/spec_1_1/spec_top_finedelay.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"104"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/rtl/l2p_arbiter.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"105"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/general-cores/modules/genrams/genram_pkg.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"106"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/rtl/p2l_decode32.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"107"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/rtl/p2l_dma_master.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"108"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/rtl/serdes_1_to_n_clk_ddr_s2_diff.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"109"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/rtl/serdes_1_to_n_clk_pll_s2_diff.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"110"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/rtl/serdes_1_to_n_data_ddr_s2_se.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"111"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/rtl/serdes_1_to_n_data_s2_se.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"112"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/rtl/serdes_n_to_1_ddr_s2_diff.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"113"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/rtl/serdes_n_to_1_ddr_s2_se.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"114"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/rtl/serdes_n_to_1_s2_diff.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"115"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/rtl/serdes_n_to_1_s2_se.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"116"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/rtl/wbmaster32.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"117"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/rtl/spartan6/gn4124_core.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"118"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/rtl/dma_controller.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"119"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/rtl/spartan6/l2p_ser.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"120"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/rtl/spartan6/p2l_des.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"121"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/general-cores/modules/wishbone/wishbone_pkg.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"122"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/general-cores/modules/common/gc_crc_gen.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"123"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/general-cores/modules/common/gc_moving_average.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"124"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/general-cores/modules/common/gc_extend_pulse.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"125"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/general-cores/modules/common/gc_delay_gen.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"126"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/general-cores/modules/common/gc_dual_pi_controller.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"127"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/general-cores/modules/common/gc_serial_dac.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"128"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/general-cores/modules/common/gc_sync_ffs.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"129"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/rtl/l2p_dma_master.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"130"
/>
</file>
<file
xil_pn:name=
"../../top/spec_1_1/wb_gpio_port_notristates.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"131"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/general-cores/modules/wishbone/wb_async_bridge/wb_cpu_bridge.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"132"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/general-cores/modules/wishbone/wb_conmax/wb_conmax_pri_dec.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"133"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/general-cores/modules/wishbone/wb_conmax/wb_conmax_pri_enc.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"134"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/general-cores/modules/wishbone/wb_conmax/wb_conmax_arb.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"135"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/general-cores/modules/wishbone/wb_conmax/wb_conmax_msel.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"136"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/general-cores/modules/wishbone/wb_conmax/wbconmax_pkg.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"137"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/general-cores/modules/wishbone/wb_conmax/wb_conmax_slave_if.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"138"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/general-cores/modules/wishbone/wb_conmax/wb_conmax_master_if.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"139"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/general-cores/modules/wishbone/wb_conmax/wb_conmax_rf.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"140"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/general-cores/modules/wishbone/wb_conmax/wb_conmax_top.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"141"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/general-cores/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"142"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/general-cores/modules/wishbone/wb_simple_timer/wb_tics.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"143"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/general-cores/modules/wishbone/wb_uart/uart_async_rx.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"144"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/general-cores/modules/wishbone/wb_uart/uart_async_tx.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"145"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/general-cores/modules/wishbone/wb_uart/uart_baud_gen.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"146"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/general-cores/modules/wishbone/wb_uart/uart_wb_slave.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"147"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/general-cores/modules/wishbone/wb_uart/wb_simple_uart.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"148"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/general-cores/modules/wishbone/wb_vic/vic_prio_enc.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"149"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/general-cores/modules/wishbone/wb_vic/wb_slave_vic.wb"
xil_pn:type=
"FILE_USERDOC"
/>
<file
xil_pn:name=
"../../ip_cores/general-cores/modules/wishbone/wb_vic/wb_vic.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"151"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/general-cores/modules/wishbone/wb_spi/spi_clgen.v"
xil_pn:type=
"FILE_VERILOG"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"152"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/general-cores/modules/wishbone/wb_spi/spi_shift.v"
xil_pn:type=
"FILE_VERILOG"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"153"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/general-cores/modules/wishbone/wb_spi/spi_top.v"
xil_pn:type=
"FILE_VERILOG"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"154"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/general-cores/modules/wishbone/wb_virtual_uart/wb_virtual_uart.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"155"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/general-cores/modules/wishbone/wb_virtual_uart/wb_virtual_uart_slave.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"156"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_dpssram.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"157"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_eic.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"158"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_fifo_async.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"159"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_fifo_sync.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"160"
/>
</file>
<file
xil_pn:name=
"../../rtl/fine_delay_wb.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"161"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/general-cores/modules/genrams/xilinx/generic_async_fifo.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"162"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/general-cores/modules/genrams/xilinx/generic_dpram.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"163"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/general-cores/modules/genrams/xilinx/generic_spram.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"164"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/general-cores/modules/genrams/xilinx/generic_sync_fifo.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"165"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/wr-cores/platform/xilinx/wr_gtp_phy/gtp_bitslide.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"166"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/wr-cores/platform/xilinx/wr_gtp_phy/gtp_phase_align.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"167"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/wr-cores/platform/xilinx/wr_gtp_phy/whiterabbitgtp_wrapper.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"168"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/wr-cores/platform/xilinx/wr_gtp_phy/whiterabbitgtp_wrapper_tile.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"169"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/wr-cores/platform/xilinx/wr_gtp_phy/wr_gtp_phy_spartan6.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"170"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/wr-cores/modules/timing/dmtd_phase_meas.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"171"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/wr-cores/modules/timing/dmtd_with_deglitcher.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"172"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/wr-cores/modules/timing/multi_dmtd_with_deglitcher.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"173"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/wr-cores/modules/timing/hpll_period_detect.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"174"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/wr-cores/modules/wr_mini_nic/minic_packet_buffer.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"175"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/wr-cores/modules/wr_mini_nic/minic_wb_slave.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"176"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/wr-cores/modules/wrsw_endpoint/endpoint_pkg.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"177"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/wr-cores/modules/wr_softpll/softpll_wb.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"178"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/wr-cores/modules/wr_softpll/wr_softpll.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"179"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/wr-cores/modules/wrc_lm32/wrc_lm32.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"180"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/wr-cores/modules/wrc_lm32/lm32_cpu.v"
xil_pn:type=
"FILE_VERILOG"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"181"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/wr-cores/modules/wrc_lm32/lm32_addsub.v"
xil_pn:type=
"FILE_VERILOG"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"182"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/wr-cores/modules/wrc_lm32/lm32_top.v"
xil_pn:type=
"FILE_VERILOG"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"183"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/wr-cores/modules/wrc_lm32/lm32_instruction_unit.v"
xil_pn:type=
"FILE_VERILOG"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"184"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/wr-cores/modules/wrc_lm32/lm32_decoder.v"
xil_pn:type=
"FILE_VERILOG"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"185"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/wr-cores/modules/wrc_lm32/lm32_load_store_unit.v"
xil_pn:type=
"FILE_VERILOG"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"186"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/wr-cores/modules/wrc_lm32/lm32_adder.v"
xil_pn:type=
"FILE_VERILOG"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"187"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/wr-cores/modules/wrc_lm32/lm32_logic_op.v"
xil_pn:type=
"FILE_VERILOG"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"188"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/wr-cores/modules/wrc_lm32/lm32_shifter.v"
xil_pn:type=
"FILE_VERILOG"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"189"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/wr-cores/modules/wrc_lm32/lm32_multiplier.v"
xil_pn:type=
"FILE_VERILOG"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"190"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/wr-cores/modules/wrc_lm32/lm32_interrupt.v"
xil_pn:type=
"FILE_VERILOG"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"191"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/wr-cores/modules/wrc_lm32/lm32_dp_ram.v"
xil_pn:type=
"FILE_VERILOG"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"192"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/wr-cores/modules/wr_mini_nic/wr_mini_nic.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"193"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/wr-cores/modules/wrsw_endpoint/ep_enc_8b10b.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"194"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/wr-cores/modules/wrsw_endpoint/ep_dec_8b10b.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"195"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/wr-cores/modules/wrsw_endpoint/ep_rx_pcs_tbi.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"196"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/wr-cores/modules/wrsw_endpoint/ep_tx_pcs_tbi.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"197"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/wr-cores/modules/wrsw_endpoint/ep_autonegotiation.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"198"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/wr-cores/modules/wrsw_endpoint/ep_pcs_tbi_mdio_wb.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"199"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/wr-cores/modules/wrsw_endpoint/ep_1000basex_pcs.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"200"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/wr-cores/modules/wrsw_endpoint/ep_rx_crc_size_check.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"201"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/wr-cores/modules/wrsw_endpoint/ep_rx_deframer.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"202"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/wr-cores/modules/wrsw_endpoint/ep_tx_framer.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"203"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/wr-cores/modules/wrsw_endpoint/ep_flow_control.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"204"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/wr-cores/modules/wrsw_endpoint/ep_timestamping_unit.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"205"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/wr-cores/modules/wrsw_endpoint/ep_rmon_counters.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"206"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/wr-cores/modules/wrsw_endpoint/ep_rx_buffer.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"207"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/wr-cores/modules/wrsw_endpoint/ep_sync_detect.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"208"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/wr-cores/modules/wrsw_endpoint/ep_wishbone_controller.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"209"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/wr-cores/modules/wrsw_endpoint/ep_ts_counter.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"210"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/wr-cores/modules/wrsw_endpoint/wrsw_endpoint.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"211"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/wr-cores/modules/wrsw_pps_gen/pps_gen_wb.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"212"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/wr-cores/modules/wrsw_pps_gen/wrsw_pps_gen.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"213"
/>
</file>
</files>
</project>
Write
Preview
Markdown
is supported
0%
Try again
or
attach a new file
Attach a file
Cancel
You are about to add
0
people
to the discussion. Proceed with caution.
Finish editing this message first!
Cancel
Please
register
or
sign in
to comment
