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FMC DEL 1ns 4cha
Commits
aade9e8b
Commit
aade9e8b
authored
Apr 26, 2012
by
Tomasz Wlostowski
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software/python: updated demo GUI and library
parent
a9d3e9cc
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2 changed files
with
59 additions
and
31 deletions
+59
-31
demo.py
software/python/demo.py
+10
-3
fdelay_lib.py
software/python/fdelay_lib.py
+49
-28
No files found.
software/python/demo.py
View file @
aade9e8b
...
...
@@ -68,13 +68,20 @@ def on_chk_wr():
if
__name__
==
"__main__"
:
import
os
fd
=
os
.
open
(
"/dev/rawrabbit"
,
os
.
O_SYNC
)
if
(
fd
<
0
):
print
(
"Can't open the rawrabbit device. Is the rawrabbit driver installed?"
)
os
.
exit
(
-
1
)
card
=
FineDelay
(
fd
)
app
=
QApplication
(
sys
.
argv
)
location
=
"local/0x84000"
m
=
MainWindow
()
m
.
show
()
m
.
setWindowTitle
(
"Fine Delay Demo @
%
s"
%
location
)
card
=
FineDelay
(
location
)
import
os
m
.
setWindowTitle
(
"Fine Delay Demo"
)
m
.
wr_status
.
setText
(
""
)
ch_enable
=
[
m
.
en_ch1
,
m
.
en_ch2
,
m
.
en_ch3
,
m
.
en_ch4
];
ch_nsec
=
[
m
.
nsec_ch1
,
m
.
nsec_ch2
,
m
.
nsec_ch3
,
m
.
nsec_ch4
];
...
...
software/python/fdelay_lib.py
View file @
aade9e8b
...
...
@@ -3,12 +3,14 @@
from
ctypes
import
*
import
sys
import
re
import
os
class
fd_timestamp
(
Structure
):
_fields_
=
[(
"utc"
,
c_ulong
),
_fields_
=
[(
"utc"
,
c_ulong
long
),
(
"coarse"
,
c_ulong
),
(
"frac"
,
c_ulong
),
(
"seq_id"
,
c_ushort
)]
(
"seq_id"
,
c_ushort
),
(
"channel"
,
c_int
)]
def
nsecs
(
self
):
return
(
float
(
self
.
frac
)
*
8000.0
/
4096.0
+
float
(
self
.
coarse
)
*
8000.0
)
/
1000.0
;
...
...
@@ -21,6 +23,8 @@ class fd_timestamp(Structure):
class
FineDelay
:
BASE_ADDR
=
0x84000
FREE_RUNNING
=
0x10
WR_OFFLINE
=
0x8
WR_READY
=
0x1
...
...
@@ -29,31 +33,48 @@ class FineDelay:
SYNC_LOCAL
=
0x1
SYNC_WR
=
0x2
def
__init__
(
self
,
dev_path
):
s
=
re
.
split
(
"
\
/"
,
dev_path
)
self
.
fd
=
CDLL
(
'../lib/libfinedelay.so'
)
if
(
s
[
0
]
==
"local"
):
print
(
"Initializing local at
%
x"
%
int
(
s
[
1
],
16
))
self
.
handle
=
c_voidp
(
self
.
fd
.
fdelay_create_rawrabbit
(
int
(
s
[
1
],
16
)));
elif
(
s
[
0
]
==
"minibone"
):
print
(
"Initializing minibone at
%
s [
%
s]
\n
"
%
(
s
[
1
],
s
[
2
]))
self
.
handle
=
c_voidp
(
self
.
fd
.
fdelay_create_minibone
(
c_char_p
(
s
[
1
]),
c_char_p
(
s
[
2
]),
int
(
s
[
3
],
16
)));
if
(
self
.
fd
.
fdelay_init
(
self
.
handle
)
<
0
):
def
__init__
(
self
,
fd
):
cwd
=
os
.
path
.
dirname
(
__file__
)
self
.
fdelay
=
CDLL
(
cwd
+
'/../lib/libfinedelay.so'
)
self
.
handle
=
c_voidp
(
self
.
fdelay
.
fdelay_create_rawrabbit
(
c_int
(
fd
),
c_ulong
(
self
.
BASE_ADDR
)));
if
(
c_int
(
self
.
fdelay
.
fdelay_load_firmware
(
"spec_top.bin"
))
<
0
):
print
(
"Firmware loader failed..."
);
sys
.
exit
(
-
1
)
print
"Initialising Fine Delay board..."
if
(
self
.
fdelay
.
fdelay_init
(
self
.
handle
)
<
0
):
print
(
"Init failed.."
);
# sys.exit(-1)
sys
.
exit
(
-
1
)
def
conf_trigger
(
self
,
enable
,
termination
):
self
.
fd
.
fdelay_configure_trigger
(
self
.
handle
,
c_int
(
enable
),
c_int
(
termination
))
self
.
fd
elay
.
fdelay_configure_trigger
(
self
.
handle
,
c_int
(
enable
),
c_int
(
termination
))
def
conf_output
(
self
,
channel
,
enable
,
delay
,
width
):
self
.
fd
.
fdelay_configure_output
(
self
.
handle
,
c_int
(
channel
),
c_int
(
enable
),
c_ulonglong
(
delay
),
c_ulonglong
(
width
))
self
.
fd
elay
.
fdelay_configure_output
(
self
.
handle
,
c_int
(
channel
),
c_int
(
enable
),
c_ulonglong
(
delay
),
c_ulonglong
(
width
))
def
conf_readout
(
self
,
enable
):
self
.
fd
.
fdelay_configure_readout
(
self
.
handle
,
enable
)
self
.
fdelay
.
fdelay_configure_readout
(
self
.
handle
,
enable
)
# def conf_sync(self, mode):
# self.fdelay.fdelay_configure_sync(self.handle, mode)
def
conf_pulsegen
(
self
,
channel
,
enable
,
t_start_utc
,
t_start_coarse
,
width
,
delta
,
count
):
t
=
fd_timestamp
(
utc
=
c_ulonglong
(
t_start_utc
),
coarse
=
c_ulong
(
t_start_coarse
))
#print "channel:%d enable:%d start_t:%d width:%d delta:%d count:%d"%(channel, enable, t.utc, width, delta, count)
self
.
fdelay
.
fdelay_configure_pulse_gen
(
self
.
handle
,
c_int
(
channel
),
c_int
(
enable
),
t
,
c_ulonglong
(
width
),
c_ulonglong
(
delta
),
c_int
(
count
))
def
set_time
(
self
,
utc
,
coarse
):
t
=
fd_timestamp
(
utc
=
c_ulonglong
(
utc
),
coarse
=
c_ulong
(
coarse
))
self
.
fdelay
.
fdelay_set_time
(
self
.
handle
,
t
)
def
conf_sync
(
self
,
mode
):
self
.
fd
.
fdelay_configure_sync
(
self
.
handle
,
mode
)
def
get_time
(
self
):
t
=
fd_timestamp
()
self
.
fdelay
.
fdelay_get_time
(
self
.
handle
,
byref
(
t
))
return
t
def
get_sync_status
(
self
):
htab
=
{
self
.
FREE_RUNNING
:
"oscillator free-running"
,
...
...
@@ -61,14 +82,14 @@ class FineDelay:
self
.
WR_READY
:
"WR core ready"
,
self
.
WR_SYNCING
:
"Syncing local clock with WR"
,
self
.
WR_SYNCED
:
"Synced with WR"
}
# status = c_int(self.fd.fdelay_get_sync_status(self.handle));
# status = c_int(self.fd
elay
.fdelay_get_sync_status(self.handle));
# print("GetSyncStatus %x" % status.value);
return
"none"
;
#htab[status.value]
def
read_ts
(
self
):
buf
=
(
fd_timestamp
*
256
)();
ptr
=
pointer
(
buf
)
n
=
self
.
fd
.
fdelay_read
(
self
.
handle
,
ptr
,
256
)
n
=
self
.
fd
elay
.
fdelay_read
(
self
.
handle
,
ptr
,
256
)
arr
=
[];
for
i
in
range
(
0
,
n
):
arr
.
append
(
buf
[
i
])
...
...
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