Commit a686b998 authored by Tomasz Wlostowski's avatar Tomasz Wlostowski

hdl/ip_cores: removed vme64x-core files from the repo

parent ec77872b
Please send any questions or opinions to:
Developers: rok.stefanic@cosylab.com, ziga.kroflic@cosylab.com
OHWR list: vme64x-core@ohwr.org
\ No newline at end of file
--==============================================================--
--Design Units : CTX1 Control and Statistics
--Size:
--Speed:
--File Name: MebRam.vhd
--
--Purpose: The dpblockram implements a synthetisable model of a
-- dual port RAM.
-- There are an input data and addr ports to allow the
-- writing at the reception of a GMT frame.
-- The output data and addr ports allow a simultanous
-- reading of the circular buffer by the user, at the
-- same time than it is beeing written.
--
-- The frame and the millisecond stamp are stored in the
-- same ram word. It is the task of the MEB block to
-- separate the frame data from the millisecond stamp data.
--
--Limitations:
--
--Errors:
--
--Libraries:
--
--Dependancies: It instantiates a synthetisable model of a DPRAM
-- See MebRam.vhd
--
--Author: Pablo Antonio Alvarez Sanchez
-- European Organisation for Nuclear Research
-- SL SPS/LHC -- Control -- Timing Division
-- CERN, Geneva, Switzerland, CH-1211
-- Building 864 Room 1 - A24
--
--Simulator: ModelSim XE 5.5e_p1
--==============================================================--
--Revision List
--Version Author Date Changes
--
--1.0 PAAS 30.09.2002 Added comments, tested with the
-- rest of the design
--==============================================================--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity dpblockram is
generic (dl : integer := 42; -- Length of the data word
al : integer := 10; -- Size of the addr map (10 = 1024 words)
nw : integer := 1024); -- Number of words
-- 'nw' has to be coherent with 'al'
port (clk : in std_logic; -- Global Clock
we : in std_logic; -- Write Enable
aw : in std_logic_vector(al - 1 downto 0); -- Write Address
ar : in std_logic_vector(al - 1 downto 0); -- Read Address
di : in std_logic_vector(dl - 1 downto 0); -- Data input
dw : out std_logic_vector(dl - 1 downto 0); -- Data write, normaly open
do : out std_logic_vector(dl - 1 downto 0)); -- Data output
end dpblockram;
-- DATA OUTPUT NOT REGISTERED!
--library synplify;
--use synplify.attributes.all;
architecture syn of dpblockram is
type ram_type is array (nw - 1 downto 0) of std_logic_vector (dl - 1 downto 0);
signal RAM : ram_type;
signal read_a : std_logic_vector(al - 1 downto 0);
signal read_ar : std_logic_vector(al - 1 downto 0);
--attribute syn_ramstyle of RAM : signal is "block_ram";
begin
process (clk)
begin
if (clk'event and clk = '1') then
if (we = '1') then
RAM(conv_integer(aw)) <= di;
end if;
read_a <= aw;
read_ar <= ar;
end if;
end process;
dw <= RAM(conv_integer(read_a));
do <= RAM(conv_integer(read_ar)); -- Notice that the Data Output is not registered
end syn;
-------------------------------------------------------------------------------
--
-- Title : IRQ_controller
-- Design : VME64xCore
-- Author : Ziga Kroflic
-- Company : Cosylab
--
-------------------------------------------------------------------------------
--
-- File : IRQ_controller.vhd
-- Generated : Thu Apr 1 08:48:48 2010
-- From : interface description file
-- By : Itf2Vhdl ver. 1.20
--
-------------------------------------------------------------------------------
--
-- Description :
--
-------------------------------------------------------------------------------
--{{ Section below this comment is automatically maintained
-- and may be overwritten
--{entity {IRQ_controller} architecture {RTL}}
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_unsigned.all;
entity IRQ_controller is
port(
clk_i : in std_logic;
reset_i : in std_logic;
VME_IRQ_n_o : out std_logic_vector(6 downto 0);
VME_IACKIN_n_i : in std_logic;
VME_IACKOUT_n_o : out std_logic;
VME_AS_n_i : in STD_LOGIC;
VME_DS_n_i : in STD_LOGIC_VECTOR(1 downto 0);
irqDTACK_o : out std_logic;
IACKinProgress_o: out std_logic;
IRQ_i: in std_logic;
locAddr_i: in std_logic_vector(3 downto 1);
IDtoData_o: out std_logic;
IRQlevelReg_i: in std_logic_vector(7 downto 0)
);
end IRQ_controller;
architecture RTL of IRQ_controller is
component RisEdgeDetection is
port (
sig_i, clk_i: in std_logic;
RisEdge_o: out std_logic );
end component;
component SigInputSample is
port (
sig_i, clk_i: in std_logic;
sig_o: out std_logic );
end component;
component RegInputSample is
generic(
width: natural:=8
);
port (
reg_i: in std_logic_vector(width-1 downto 0);
reg_o: out std_logic_vector(width-1 downto 0):=(others => '0');
clk_i: in std_logic
);
end component;
signal VME_IACKIN_n_oversampled: std_logic;
signal VME_DS_n_oversampled : STD_LOGIC_VECTOR(1 downto 0);
signal s_reset: std_logic;
signal s_VME_IACKOUT: std_logic;
signal s_irqDTACK: std_logic; -- acknowledge of IACK cycle
signal s_applyIRQmask: std_logic; -- clears acknowlegded interrupt
signal s_IDtoData: std_logic; -- puts IRQ Status/ID register on data bus
signal s_IACKmatch: std_logic; -- signals that an active interrupt is being acknowledged
signal s_wbIRQrisingEdge: std_logic; -- rising edge detection on interrupt line
signal s_IRQenabled: std_logic; -- indicates that interrupts are enabled (IRQlevelReg has a valid level value)
signal s_IRQreg: std_logic; -- registers pending interrupt
type t_IRQstates is ( IDLE,
WAIT_FOR_DS,
CHECK_MATCH,
APPLY_MASK_AND_DATA,
PROPAGATE_IACK,
APPLY_DTACK
);
signal s_IRQstate: t_IRQstates;
begin
s_reset <= reset_i;
irqDTACK_o <= '0' when s_irqDTACK='0' else 'Z';
VME_IACKOUT_n_o <= '0' when s_VME_IACKOUT='0' else 'Z';
p_IRQcontrolFSM: process(clk_i)
begin
if rising_edge(clk_i) then
if s_reset='1' then
s_VME_IACKOUT <= '1';
s_irqDTACK <= '1';
s_applyIRQmask <= '0';
s_IDtoData <= '0';
IACKinProgress_o <= '0';
s_IRQstate <= IDLE;
else
case s_IRQstate is
when IDLE =>
s_VME_IACKOUT <= '1';
s_irqDTACK <= '1';
s_applyIRQmask <= '0';
s_IDtoData <= '0';
IACKinProgress_o <= '0';
if VME_IACKIN_n_oversampled='0' then
s_IRQstate <= WAIT_FOR_DS;
else
s_IRQstate <= IDLE;
end if;
when WAIT_FOR_DS =>
s_VME_IACKOUT <= '1';
s_irqDTACK <= '1';
s_applyIRQmask <= '0';
s_IDtoData <= '0';
IACKinProgress_o <= '0';
if VME_DS_n_oversampled/="11" then
s_IRQstate <= CHECK_MATCH;
else
s_IRQstate <= WAIT_FOR_DS;
end if;
when CHECK_MATCH =>
s_VME_IACKOUT <= '1';
s_irqDTACK <= '1';
s_applyIRQmask <= '0';
s_IDtoData <= '0';
IACKinProgress_o <= '0';
if s_IACKmatch='1' then
s_IRQstate <= APPLY_MASK_AND_DATA;
else
s_IRQstate <= PROPAGATE_IACK;
end if;
when APPLY_MASK_AND_DATA =>
s_VME_IACKOUT <= '1';
s_irqDTACK <= '1';
s_applyIRQmask <= '1';
s_IDtoData <= '1';
IACKinProgress_o <= '1';
s_IRQstate <= APPLY_DTACK;
when APPLY_DTACK =>
s_VME_IACKOUT <= '1';
s_irqDTACK <= '0';
s_applyIRQmask <= '0';
s_IDtoData <= '1';
IACKinProgress_o <= '1';
if VME_IACKIN_n_oversampled='1' then
s_IRQstate <= IDLE;
else
s_IRQstate <= APPLY_DTACK;
end if;
when PROPAGATE_IACK =>
s_VME_IACKOUT <= VME_IACKIN_n_oversampled;
s_irqDTACK <= '1';
s_applyIRQmask <= '0';
s_IDtoData <= '0';
IACKinProgress_o <= '0';
if VME_IACKIN_n_oversampled='1' then
s_IRQstate <= IDLE;
else
s_IRQstate <= PROPAGATE_IACK;
end if;
when OTHERS =>
s_VME_IACKOUT <= '1';
s_irqDTACK <= '1';
s_applyIRQmask <= '0';
s_IDtoData <= '0';
IACKinProgress_o <= '0';
s_IRQstate <= IDLE;
end case;
end if;
end if;
end process;
s_IACKmatch <= '1' when "00000"&locAddr_i = IRQlevelReg_i else '0';
s_IRQenabled <= '1' when IRQlevelReg_i < 8 and IRQlevelReg_i /= 0 else '0';
IDtoData_o <= s_IDtoData;
-- Setting and clearing pending interrupt request register
p_IRQregHandling: process(clk_i)
begin
if rising_edge(clk_i) then
if s_reset='1' then
s_IRQreg <= '0';
elsif s_applyIRQmask='1' then
s_IRQreg <= '0';
else
s_IRQreg <= s_wbIRQrisingEdge and s_IRQenabled;
end if;
end if;
end process;
-- Driving VME_IRQ lines
gen_IRQoutput: for i in 0 to 6 generate
VME_IRQ_n_o(i) <= '0' when s_IRQreg='1' and IRQlevelReg_i=(i+1) else 'Z';
end generate;
-- Signal input oversample & rising edge detection
IRQrisingEdge: RisEdgeDetection
port map (
sig_i => IRQ_i,
clk_i => clk_i,
RisEdge_o => s_wbIRQrisingEdge
);
IACKINinputSample: SigInputSample
port map(
sig_i => VME_IACKIN_n_i,
sig_o => VME_IACKIN_n_oversampled,
clk_i => clk_i
);
DSinputSample: RegInputSample
generic map(
width => 2
)
port map(
reg_i => VME_DS_n_i,
reg_o => VME_DS_n_oversampled,
clk_i => clk_i
);
end RTL;
files = [
"VME_bus.vhd",
"VME_CR_pack.vhd",
"wb_dma.vhd",
"VME_CSR_pack.vhd",
"VME_pack.vhd",
"SharedComps.vhd",
"DpBlockRam.vhd",
"TrueDpBlockRam.vhd",
"common_components.vhd",
"VME64xCore_NoIpTop.vhd" ];
library IEEE;
use IEEE.STD_LOGIC_1164.all;
-- tripple sample sig_i signals to avoid metastable states
entity SigInputSample is
port (
sig_i, clk_i: in std_logic;
sig_o: out std_logic );
end SigInputSample;
architecture RTL of SigInputSample is
signal s_1: std_logic;
signal s_2: std_logic;
begin
process(clk_i)
begin
if rising_edge(clk_i) then
s_1 <= sig_i;
s_2 <= s_1;
sig_o <= s_2;
end if;
end process;
end RTL;
-- ***************************************************
library IEEE;
use IEEE.STD_LOGIC_1164.all;
-- double sample sig_i signals to avoid metastable states
entity DoubleSigInputSample is
port (
sig_i, clk_i: in std_logic;
sig_o: out std_logic );
end DoubleSigInputSample;
architecture RTL of DoubleSigInputSample is
signal s_1: std_logic;
-- signal s_2: std_logic;
begin
process(clk_i)
begin
if rising_edge(clk_i) then
s_1 <= sig_i;
sig_o <= s_1;
end if;
end process;
end RTL;
-- ***************************************************
library IEEE;
use IEEE.STD_LOGIC_1164.all;
-- detect rising edge
entity RisEdgeDetection is
port (
sig_i, clk_i: in std_logic;
RisEdge_o: out std_logic );
end RisEdgeDetection;
architecture RTL of RisEdgeDetection is
signal s_1: std_logic;
begin
process(clk_i)
begin
if rising_edge(clk_i) then
s_1 <= sig_i;
if s_1 = '0' and sig_i = '1' then
RisEdge_o <= '1';
else
RisEdge_o <= '0';
end if;
end if;
end process;
end RTL;
-- ***************************************************
library IEEE;
use IEEE.STD_LOGIC_1164.all;
-- detect falling edge
entity FallingEdgeDetection is
port (
sig_i, clk_i: in std_logic;
FallEdge_o: out std_logic );
end FallingEdgeDetection;
architecture RTL of FallingEdgeDetection is
signal s_1: std_logic;
begin
process(clk_i)
begin
if rising_edge(clk_i) then
s_1 <= sig_i;
if s_1 = '1' and sig_i = '0' then
FallEdge_o <= '1';
else
FallEdge_o <= '0';
end if;
end if;
end process;
end RTL;
-- ***************************************************
library IEEE;
use IEEE.STD_LOGIC_1164.all;
-- give pulse (sigEdge_o) at rising and falling edge
entity EdgeDetection is
port (
sig_i,
clk_i: in std_logic;
sigEdge_o: out std_logic
);
end EdgeDetection;
architecture RTL of EdgeDetection is
signal s_1: std_logic;
begin
process(clk_i)
begin
if rising_edge(clk_i) then
s_1 <= sig_i;
if (s_1 = '0' and sig_i = '1') or (s_1 = '1' and sig_i = '0') then
sigEdge_o <= '1';
else
sigEdge_o <= '0';
end if;
end if;
end process;
end RTL;
-- ***************************************************
library IEEE;
use IEEE.STD_LOGIC_1164.all;
-- triple sample input register reg_i to avoid metastable states
-- and catching of transition values
entity RegInputSample is
generic(
width: natural:=8
);
port (
reg_i: in std_logic_vector(width-1 downto 0);
reg_o: out std_logic_vector(width-1 downto 0);
clk_i: in std_logic
);
end RegInputSample;
architecture RTL of RegInputSample is
signal reg_1, reg_2: std_logic_vector(width-1 downto 0);
begin
process(clk_i)
begin
if rising_edge(clk_i) then
reg_1 <= reg_i;
reg_2 <= reg_1;
reg_o <= reg_2;
end if;
end process;
end RTL;
-- ***************************************************
library IEEE;
use IEEE.STD_LOGIC_1164.all;
-- triple sample input register reg_i to avoid metastable states
-- and catching of transition values
entity DoubleRegInputSample is
generic(
width: natural:=8
);
port (
reg_i: in std_logic_vector(width-1 downto 0);
reg_o: out std_logic_vector(width-1 downto 0);
clk_i: in std_logic
);
end DoubleRegInputSample;
architecture RTL of DoubleRegInputSample is
signal reg_1, reg_2: std_logic_vector(width-1 downto 0);
begin
process(clk_i)
begin
if rising_edge(clk_i) then
reg_1 <= reg_i;
reg_o <= reg_1;
end if;
end process;
end RTL;
\ No newline at end of file
--==============================================================--
--Design Units : CTX1 Control and Statistics
--Size:
--Speed:
--File Name: MebRam.vhd
--
--Purpose: The dpblockram implements a synthetisable model of a
-- dual port RAM.
-- There are an input data and addr ports to allow the
-- writing at the reception of a GMT frame.
-- The output data and addr ports allow a simultanous
-- reading of the circular buffer by the user, at the
-- same time than it is beeing written.
--
-- The frame and the millisecond stamp are stored in the
-- same ram word. It is the task of the MEB block to
-- separate the frame data from the millisecond stamp data.
--
--Limitations:
--
--Errors:
--
--Libraries:
--
--Dependancies: It instantiates a synthetisable model of a DPRAM
-- See MebRam.vhd
--
--Author: Pablo Antonio Alvarez Sanchez
-- European Organisation for Nuclear Research
-- SL SPS/LHC -- Control -- Timing Division
-- CERN, Geneva, Switzerland, CH-1211
-- Building 864 Room 1 - A24
--
--Simulator: ModelSim XE 5.5e_p1
--==============================================================--
--Revision List
--Version Author Date Changes
--
--1.0 PAAS 30.09.2002 Added comments, tested with the
-- rest of the design
--==============================================================--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity TrueDpblockram is
generic (dl : integer := 42; -- Length of the data word
al : integer := 10); -- Size of the addr map (10 = 1024 words)
-- 'nw' has to be coherent with 'al'
port (clk_a_i : in std_logic; -- Global Clock
we_a_i : in std_logic; -- Write Enable
a_a_i : in std_logic_vector(al - 1 downto 0); -- Write Address
di_a_i : in std_logic_vector(dl - 1 downto 0); -- Data input
do_a_o : out std_logic_vector(dl - 1 downto 0); -- Data write, normaly open
clk_b_i : in std_logic; -- Global Clock
we_b_i : in std_logic; -- Write Enable
a_b_i : in std_logic_vector(al - 1 downto 0); -- Write Address
di_b_i : in std_logic_vector(dl - 1 downto 0); -- Data input
do_b_o : out std_logic_vector(dl - 1 downto 0)); -- Data write, normaly open
end TrueDpblockram;
-- DATA OUTPUT NOT REGISTERED!
--library synplify;
--use synplify.attributes.all;
architecture syn of TrueDpblockram is
type t_ram is array (2**al-1 downto 0) of std_logic_vector (dl-1 downto 0);
shared variable ram: t_ram;
begin
process (clk_a_i)
begin
if (clk_a_i'event and clk_a_i = '1') then
-- if (<enableA> = '1') then
if (we_a_i = '1') then
ram(conv_integer(a_a_i)) := di_a_i;
end if;
do_a_o <= ram(conv_integer(a_a_i));
-- end if;
end if;
end process;
process (clk_b_i)
begin
if (clk_b_i'event and clk_b_i = '1') then
-- if (<enableB> = '1') then
if (we_b_i = '1') then
ram(conv_integer(a_b_i)) := di_b_i;
end if;
do_b_o <= ram(conv_integer(a_b_i));
end if;
-- end if;
end process;
end syn;
-------------------------------------------------------------------------------
--
-- Title : VME64xCore_Top
-- Design : VME64xCore
-- Author : Ziga Kroflic
-- Company : Cosylab
--
-------------------------------------------------------------------------------
--
-- File : VME64xCore_Top.vhd
-- Generated : Tue Mar 30 09:41:05 2010
-- From : interface description file
-- By : Itf2Vhdl ver. 1.20
--
-------------------------------------------------------------------------------
--
-- Description :
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.numeric_std.all;
use work.VME_CR_pack.all;
use work.common_components.all;
entity VME64xCore_Top is
port(
clk_i : in std_logic; -- 100 MHz clock input
-- VME
VME_AS_n_i : in std_logic;
VME_RST_n_i : in std_logic;
VME_WRITE_n_i : in std_logic;
VME_AM_i : in std_logic_vector(5 downto 0);
VME_DS_n_i : in std_logic_vector(1 downto 0);
VME_GA_i : in std_logic_vector(5 downto 0);
VME_BERR_o : out std_logic;
VME_DTACK_n_o : out std_logic;
VME_RETRY_n_o : out std_logic;
VME_RETRY_OE_o : out std_logic;
VME_LWORD_n_b : inout std_logic;
VME_ADDR_b : inout std_logic_vector(31 downto 1);
VME_DATA_b : inout std_logic_vector(31 downto 0);
VME_BBSY_n_i : in std_logic;
VME_IRQ_n_o : out std_logic_vector(6 downto 0);
VME_IACK_n_i : in std_logic;
VME_IACKIN_n_i : in std_logic;
VME_IACKOUT_n_o : out std_logic;
-- VME buffers
VME_DTACK_OE_o : out std_logic;
VME_DATA_DIR_o : out std_logic;
VME_DATA_OE_n_o : out std_logic;
VME_ADDR_DIR_o : out std_logic;
VME_ADDR_OE_n_o : out std_logic;
-- WishBone
RST_i : in std_logic;
DAT_i : in std_logic_vector(63 downto 0);
DAT_o : out std_logic_vector(63 downto 0);
ADR_o : out std_logic_vector(63 downto 0);
CYC_o : out std_logic;
ERR_i : in std_logic;
LOCK_o : out std_logic;
RTY_i : in std_logic;
SEL_o : out std_logic_vector(7 downto 0);
STB_o : out std_logic;
ACK_i : in std_logic;
WE_o : out std_logic;
STALL_i : in std_logic;
-- IRQ
IRQ_i : in std_logic
-- Uncomment this for use of external CR and CRAM
-- -- CROM
-- CRaddr_o: out std_logic_vector(18 downto 0);
-- CRdata_i: in std_logic_vector(7 downto 0);
--
-- -- CRAM
-- CRAMaddr_o: out std_logic_vector(18 downto 0);
-- CRAMdata_o: out std_logic_vector(7 downto 0);
-- CRAMdata_i: in std_logic_vector(7 downto 0);
-- CRAMwea_o: out std_logic
);
end VME64xCore_Top;
architecture RTL of VME64xCore_Top is
component VME_bus
port(
clk_i : in std_logic;
reset_o : out std_logic;
-- VME signals
VME_RST_n_i : in std_logic;
VME_AS_n_i : in std_logic;
VME_LWORD_n_b_o : out std_logic;
VME_LWORD_n_b_i : in std_logic;
VME_RETRY_n_o : out std_logic;
VME_RETRY_OE_n_o : out std_logic;
VME_WRITE_n_i : in std_logic;
VME_DS_n_i : in std_logic_vector(1 downto 0);
VME_GA_i : in std_logic_vector(5 downto 0); -- Geographical Address and GA parity
VME_DTACK_n_o : out std_logic;
VME_DTACK_OE_o : out std_logic;
VME_BERR_o : out std_logic;
VME_ADDR_b_i : in std_logic_vector(31 downto 1);
VME_ADDR_b_o : out std_logic_vector(31 downto 1);
VME_ADDR_DIR_o : out std_logic;
VME_ADDR_OE_o : out std_logic;
VME_DATA_b_i : in std_logic_vector(31 downto 0);
VME_DATA_b_o : out std_logic_vector(31 downto 0);
VME_DATA_DIR_o : out std_logic;
VME_DATA_OE_o : out std_logic;
VME_AM_i : in std_logic_vector(5 downto 0);
VME_BBSY_n_i : in std_logic;
VME_IACKIN_n_i : in std_logic;
-- CROM
CRaddr_o : out std_logic_vector(18 downto 0);
CRdata_i : in std_logic_vector(7 downto 0);
-- CRAM
CRAMaddr_o : out std_logic_vector(18 downto 0);
CRAMdata_o : out std_logic_vector(7 downto 0);
CRAMdata_i : in std_logic_vector(7 downto 0);
CRAMwea_o : out std_logic;
-- WB signals
memReq_o : out std_logic;
memAckWB_i : in std_logic;
wbData_o : out std_logic_vector(63 downto 0);
wbData_i : in std_logic_vector(63 downto 0);
locAddr_o : out std_logic_vector(63 downto 0);
wbSel_o : out std_logic_vector(7 downto 0);
RW_o : out std_logic;
lock_o : out std_logic;
cyc_o : out std_logic;
err_i : in std_logic;
rty_i : in std_logic;
stall_i : in std_logic;
psize_o : out std_logic_vector(7 downto 0);
-- IRQ controller signals
irqDTACK_i : in std_logic;
IACKinProgress_i : in std_logic;
IDtoData_i : in std_logic;
IRQlevelReg_o : out std_logic_vector(7 downto 0);
-- 2e related signals
TWOeInProgress_o : out std_logic;
transfer_done_i : in std_logic
);
end component;
component WB_bus is
port (
clk_i : in std_logic;
reset_i : in std_logic;
RST_i : in std_logic;
DAT_i : in std_logic_vector(63 downto 0);
DAT_o : out std_logic_vector(63 downto 0);
ADR_o : out std_logic_vector(63 downto 0);
CYC_o : out std_logic;
ERR_i : in std_logic;
LOCK_o : out std_logic;
RTY_i : in std_logic;
SEL_o : out std_logic_vector(7 downto 0);
STB_o : out std_logic;
ACK_i : in std_logic;
WE_o : out std_logic;
STALL_i : in std_logic;
memReq_i : in std_logic;
memAck_o : out std_logic;
locData_o : out std_logic_vector(63 downto 0);
locData_i : in std_logic_vector(63 downto 0);
locAddr_i : in std_logic_vector(63 downto 0);
sel_i : in std_logic_vector(7 downto 0);
RW_i : in std_logic;
lock_i : in std_logic;
err_o : out std_logic;
rty_o : out std_logic;
cyc_i : in std_logic;
psize_o : in std_logic_vector(7 downto 0);
-- FIFOrden_o : out std_logic;
-- FIFOwren_o : out std_logic;
-- FIFOdata_i : in std_logic_vector(63 downto 0);
-- FIFOdata_o : out std_logic_vector(63 downto 0);
-- FIFOreset_o : out std_logic;
-- writeFIFOempty_i : in std_logic;
TWOeInProgress_i : in std_logic;
WBbusy_o : out std_logic
);
end component;
component IRQ_controller is
port(
clk_i : in std_logic;
reset_i : in std_logic;
VME_IRQ_n_o : out std_logic_vector(6 downto 0);
VME_IACKIN_n_i : in std_logic;
VME_IACKOUT_n_o : out std_logic;
VME_AS_n_i : in std_logic;
VME_DS_n_i : in std_logic_vector(1 downto 0);
irqDTACK_o : out std_logic;
IACKinProgress_o : out std_logic;
IRQ_i : in std_logic;
locAddr_i : in std_logic_vector(3 downto 1);
IDtoData_o : out std_logic;
IRQlevelReg_i : in std_logic_vector(7 downto 0)
);
end component;
constant c_zeros : std_logic_vector(31 downto 0) := (others => '0');
constant c_ones : std_logic_vector(31 downto 0) := (others => '1');
signal s_CRAMdataOut : std_logic_vector(7 downto 0);
signal s_CRAMaddr : std_logic_vector(18 downto 0);
signal s_CRAMdataIn : std_logic_vector(7 downto 0);
signal s_CRAMwea : std_logic;
signal s_CRaddr : std_logic_vector(18 downto 0);
signal s_CRdata : std_logic_vector(7 downto 0);
signal s_RW : std_logic;
signal s_lock : std_logic;
signal s_locAddr : std_logic_vector(63 downto 0);
signal s_WBdataIn : std_logic_vector(63 downto 0);
signal s_WBdataOut : std_logic_vector(63 downto 0);
signal s_WBsel : std_logic_vector(7 downto 0);
signal s_memAckWB : std_logic;
signal s_memReq : std_logic;
--signal s_IRQ: std_logic;
signal s_cyc : std_logic;
signal s_reset : std_logic;
signal s_err : std_logic;
signal s_rty : std_logic;
signal s_irqDTACK : std_logic;
signal s_IACKinProgress : std_logic;
signal s_IRQlevelReg : std_logic_vector(7 downto 0);
signal s_IDtoData : std_logic;
signal s_FIFOreset : std_logic;
signal s_TWOeInProgress : std_logic;
-- signal s_WBbusy : std_logic;
signal s_stall : std_logic;
signal s_psize : std_logic_vector(7 downto 0);
signal s_vme_addr_b_o : std_logic_vector(31 downto 1);
signal s_VME_LWORD_n_b_o : std_logic;
signal s_VME_ADDR_OE_o, s_VME_DATA_OE, s_VME_DATA_DIR : std_logic;
signal s_VME_DATA_b_o : std_logic_vector(31 downto 0);
signal s_transfer_done : std_logic;
signal sel_we : std_logic;
signal s_VME_ADDR_DIR : std_logic;
begin
-- Uncomment this section for use of external CR and CRAM
--s_CRAMdataOut <= CRAMdata_i;
--CRAMaddr_o <= s_CRAMaddr;
--CRAMdata_o <= s_CRAMdataIn;
--CRAMwea_o <= s_CRAMwea;
--CRaddr_o <= s_CRaddr;
--s_CRdata <= CRdata_i;
--s_FIFOreset <= s_wbFIFOreset or s_reset;
VME_bus_1 : VME_bus
port map(
VME_AM_i => VME_AM_i,
VME_AS_n_i => VME_AS_n_i,
VME_DS_n_i => VME_DS_n_i,
VME_GA_i => VME_GA_i,
VME_RST_n_i => VME_RST_n_i,
VME_WRITE_n_i => VME_WRITE_n_i,
VME_BERR_o => VME_BERR_o,
VME_DTACK_n_o => VME_DTACK_n_o,
VME_RETRY_n_o => VME_RETRY_n_o,
VME_RETRY_OE_n_o => VME_RETRY_OE_o,
VME_ADDR_b_o => s_VME_ADDR_b_o,
VME_ADDR_b_i => VME_ADDR_b,
VME_LWORD_n_b_i => VME_LWORD_n_b,
VME_LWORD_n_b_o => s_VME_LWORD_n_b_o,
VME_ADDR_DIR_o => s_VME_ADDR_DIR,
VME_ADDR_OE_o => s_VME_ADDR_OE_o,
VME_DATA_b_o => s_VME_DATA_b_o,
VME_DATA_b_i => VME_DATA_b,
VME_DATA_DIR_o => s_VME_DATA_DIR,
VME_DATA_OE_o => s_VME_DATA_OE,
VME_BBSY_n_i => VME_BBSY_n_i,
VME_IACKIN_n_i => VME_IACKIN_n_i,
VME_DTACK_OE_o => VME_DTACK_OE_o,
clk_i => clk_i,
reset_o => s_reset,
CRAMdata_i => s_CRAMdataOut,
CRAMaddr_o => s_CRAMaddr,
CRAMdata_o => s_CRAMdataIn,
CRAMwea_o => s_CRAMwea,
CRaddr_o => s_CRaddr,
CRdata_i => s_CRdata,
RW_o => s_RW,
lock_o => s_lock,
cyc_o => s_cyc,
stall_i => s_stall,
locAddr_o => s_locAddr,
wbData_o => s_WBdataIn,
wbData_i => s_WBdataOut,
wbSel_o => s_WBsel,
memAckWB_i => s_memAckWB,
memReq_o => s_memReq,
err_i => s_err,
rty_i => s_rty,
psize_o => s_psize,
irqDTACK_i => s_irqDTACK,
IACKinProgress_i => s_IACKinProgress,
IDtoData_i => s_IDtoData,
IRQlevelReg_o => s_IRQlevelReg,
-- FIFOwren_o => s_FIFOwriteWren,
-- FIFOdata_o => s_FIFOwriteDin,
-- FIFOrden_o => s_FIFOreadRden,
-- FIFOdata_i => s_FIFOreadDout,
TWOeInProgress_o => s_TWOeInProgress,
transfer_done_i => s_transfer_done
-- WBbusy_i => s_WBbusy
-- readFIFOempty_i => s_FIFOreadEmpty
);
VME_ADDR_b <= s_VME_ADDR_b_o when s_VME_ADDR_DIR = '1' else (others => 'Z');
VME_LWORD_n_b <= s_VME_LWORD_n_b_o when s_VME_ADDR_DIR = '1' else 'Z';
VME_DATA_b <= s_VME_DATA_b_o when s_VME_DATA_DIR = '1' else (others => 'Z');
VME_DATA_OE_n_o <= s_VME_DATA_OE;
VME_ADDR_OE_n_o <= s_VME_ADDR_OE_o;
VME_DATA_DIR_o <= s_VME_DATA_DIR;
VME_ADDR_DIR_o <= s_VME_ADDR_DIR;
sel_we <= not s_RW;
Uwb_dma : wb_dma
generic map(c_dl => s_WBdataIn'length,
c_al => s_locAddr'length,
c_sell => s_WBsel'length,
c_psizel => s_psize'length)
port map(
-- Common signals
clk_i => clk_i,
reset_i => s_reset,
transfer_done_o => s_transfer_done,
-- Slave WB with dma support
sl_dat_i => s_WBdataIn,
sl_dat_o => s_WBdataOut,
sl_adr_i => s_locAddr,
sl_cyc_i => s_cyc,
sl_err_o => s_err,
sl_lock_i => s_lock,
sl_rty_o => s_rty,
sl_sel_i => s_WBsel,
sl_stb_i => s_memReq,
sl_ack_o => s_memAckWB,
sl_we_i => sel_we,
sl_stall_o => s_stall,
sl_psize_i => s_psize,
-- sl_buff_access_i : in std_logic;
-- Master WB port to fabric
m_dat_i => DAT_i,
m_dat_o => DAT_o,
m_adr_o => ADR_o,
m_cyc_o => cyc_o,
m_err_i => err_i,
m_lock_o => lock_o,
m_rty_i => rty_i,
m_sel_o => SEL_o,
m_stb_o => STB_o,
m_ack_i => ACK_i,
m_we_o => WE_o,
m_stall_i => STALL_i
);
-------------------------------------------------------------------------------
VME_IACKOUT_n_o <= '1';
VME_IRQ_n_o <= (others => '0');
-------------------------------------------------------------------------------
--IRQ_controller_1: IRQ_controller
-- port map(
-- clk_i => clk_i,
-- reset_i => s_reset,
-- VME_IRQ_n_o => VME_IRQ_n_o,
-- VME_IACKIN_n_i => VME_IACKIN_n_i,
-- VME_IACKOUT_n_o => VME_IACKOUT_n_o,
-- VME_AS_n_i => VME_AS_n_i,
-- VME_DS_n_i => VME_DS_n_i,
-- irqDTACK_o => s_irqDTACK,
-- IACKinProgress_o => s_IACKinProgress,
-- IRQ_i => IRQ_i,
-- locAddr_i => s_locAddr(3 downto 1),
-- IDtoData_o => s_IDtoData,
-- IRQlevelReg_i => s_IRQlevelReg
-- );
-------------------------------------------------------------------------------
s_irqDTACK <= '0';
s_IACKinProgress <= '0';
s_IDtoData <= '0';
s_IRQlevelReg <= (others => '0');
-------------------------------------------------------------------------------
process(clk_i)
begin
if rising_edge(clk_i) then
s_CRdata <= c_cr_array(to_integer(unsigned(s_CRaddr(11 downto 0))));
end if;
end process;
-------------------------------------------------------------------------------
CRAM_1 : dpblockram
generic map(dl => 8, -- Length of the data word
al => 9, -- Size of the addr map (10 = 1024 words)
nw => 2**9) -- Number of words
-- 'nw' has to be coherent with 'al'
port map(clk => clk_i, -- Global Clock
we => s_CRAMwea, -- Write Enable
aw => s_CRAMaddr(8 downto 0), -- Write Address
ar => c_zeros(8 downto 0), -- Read Address
di => s_CRAMdataIn, -- Data input
dw => s_CRAMdataOut, -- Data write, normaly open
do => open); -- Data output
end RTL;
-------------------------------------------------------------------------------
--
-- Title : VME64xCore_Top
-- Design : VME64xCore
-- Author : Ziga Kroflic
-- Company : Cosylab
--
-------------------------------------------------------------------------------
--
-- File : VME64xCore_Top.vhd
-- Generated : Tue Mar 30 09:41:05 2010
-- From : interface description file
-- By : Itf2Vhdl ver. 1.20
--
-------------------------------------------------------------------------------
--
-- Description :
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity VME64xCore_Top is
port(
clk_i : in STD_LOGIC; -- 100 MHz clock input
-- VME
VME_AS_n_i : in STD_LOGIC;
VME_RST_n_i : in STD_LOGIC;
VME_WRITE_n_i : in STD_LOGIC;
VME_AM_i : in STD_LOGIC_VECTOR(5 downto 0);
VME_DS_n_i : in STD_LOGIC_VECTOR(1 downto 0);
VME_GA_i : in STD_LOGIC_VECTOR(5 downto 0);
VME_BERR_n_o : out STD_LOGIC;
VME_DTACK_n_o : out STD_LOGIC;
VME_RETRY_n_o : out STD_LOGIC;
VME_LWORD_n_b : inout STD_LOGIC;
VME_ADDR_b : inout STD_LOGIC_VECTOR(31 downto 1);
VME_DATA_b : inout STD_LOGIC_VECTOR(31 downto 0);
VME_BBSY_n_i : in STD_LOGIC;
VME_IRQ_n_o : out std_logic_vector(6 downto 0);
VME_IACKIN_n_i : in std_logic;
VME_IACKOUT_n_o : out std_logic;
-- VME buffers
VME_DTACK_OE_o: out std_logic;
VME_DATA_DIR_o: out std_logic;
VME_DATA_OE_n_o: out std_logic;
VME_ADDR_DIR_o: out std_logic;
VME_ADDR_OE_n_o: out std_logic;
-- WishBone
RST_i: in std_logic;
DAT_i: in std_logic_vector(63 downto 0);
DAT_o: out std_logic_vector(63 downto 0);
ADR_o: out std_logic_vector(63 downto 0);
CYC_o: out std_logic;
ERR_i: in std_logic;
LOCK_o: out std_logic;
RTY_i: in std_logic;
SEL_o: out std_logic_vector(7 downto 0);
STB_o: out std_logic;
ACK_i: in std_logic;
WE_o: out std_logic;
STALL_i: in std_logic;
-- IRQ
IRQ_i: in std_logic
-- Uncomment this for use of external CR and CRAM
-- -- CROM
-- CRaddr_o: out std_logic_vector(18 downto 0);
-- CRdata_i: in std_logic_vector(7 downto 0);
--
-- -- CRAM
-- CRAMaddr_o: out std_logic_vector(18 downto 0);
-- CRAMdata_o: out std_logic_vector(7 downto 0);
-- CRAMdata_i: in std_logic_vector(7 downto 0);
-- CRAMwea_o: out std_logic
);
end VME64xCore_Top;
architecture RTL of VME64xCore_Top is
component VME_bus
port(
clk_i : in STD_LOGIC;
reset_o: out STD_LOGIC;
-- VME signals
VME_RST_n_i : in STD_LOGIC;
VME_AS_n_i : in STD_LOGIC;
VME_LWORD_n_b : inout STD_LOGIC;
VME_RETRY_n_o : out STD_LOGIC;
VME_WRITE_n_i : in STD_LOGIC;
VME_DS_n_i : in STD_LOGIC_VECTOR(1 downto 0);
VME_GA_i : in STD_LOGIC_VECTOR(5 downto 0);
VME_DTACK_n_o : out STD_LOGIC;
VME_BERR_n_o : out STD_LOGIC;
VME_ADDR_b : inout STD_LOGIC_VECTOR(31 downto 1);
VME_DATA_b : inout STD_LOGIC_VECTOR(31 downto 0);
VME_AM_i : in std_logic_vector(5 downto 0);
VME_BBSY_n_i : in std_logic;
VME_IACKIN_n_i: in std_logic;
VME_DTACK_OE_o: out std_logic;
VME_DATA_DIR_o: out std_logic;
VME_DATA_OE_o: out std_logic;
VME_ADDR_DIR_o: out std_logic;
VME_ADDR_OE_o: out std_logic;
-- CROM
CRaddr_o: out std_logic_vector(18 downto 0);
CRdata_i: in std_logic_vector(7 downto 0);
-- CRAM
CRAMaddr_o: out std_logic_vector(18 downto 0);
CRAMdata_o: out std_logic_vector(7 downto 0);
CRAMdata_i: in std_logic_vector(7 downto 0);
CRAMwea_o: out std_logic;
-- WB signals
memReq_o: out std_logic;
memAckWB_i: in std_logic;
wbData_o: out std_logic_vector(63 downto 0);
wbData_i: in std_logic_vector(63 downto 0);
locAddr_o: out std_logic_vector(63 downto 0);
wbSel_o: out std_logic_vector(7 downto 0);
RW_o: out std_logic;
lock_o: out std_logic;
cyc_o: out std_logic;
err_i: in std_logic;
rty_i: in std_logic;
beatCount_o: out std_logic_vector(7 downto 0);
-- IRQ controller signals
irqDTACK_i: in std_logic;
IACKinProgress_i: in std_logic;
IDtoData_i: in std_logic;
IRQlevelReg_o: out std_logic_vector(7 downto 0);
-- 2e related signals
FIFOwren_o: out std_logic;
FIFOdata_o: out std_logic_vector(63 downto 0);
FIFOrden_o: out std_logic;
FIFOdata_i: in std_logic_vector(63 downto 0);
TWOeInProgress_o: out std_logic;
WBbusy_i: in std_logic;
readFIFOempty_i: in std_logic
);
end component;
component WB_bus is
port (
clk_i: in std_logic;
reset_i: in std_logic;
RST_i: in std_logic;
DAT_i: in std_logic_vector(63 downto 0);
DAT_o: out std_logic_vector(63 downto 0);
ADR_o: out std_logic_vector(63 downto 0);
CYC_o: out std_logic;
ERR_i: in std_logic;
LOCK_o: out std_logic;
RTY_i: in std_logic;
SEL_o: out std_logic_vector(7 downto 0);
STB_o: out std_logic;
ACK_i: in std_logic;
WE_o: out std_logic;
STALL_i: in std_logic;
memReq_i: in std_logic;
memAck_o: out std_logic;
locData_o: out std_logic_vector(63 downto 0);
locData_i: in std_logic_vector(63 downto 0);
locAddr_i: in std_logic_vector(63 downto 0);
sel_i: in std_logic_vector(7 downto 0);
RW_i: in std_logic;
lock_i: in std_logic;
err_o: out std_logic;
rty_o: out std_logic;
cyc_i: in std_logic;
beatCount_i: in std_logic_vector(7 downto 0);
FIFOrden_o: out std_logic;
FIFOwren_o: out std_logic;
FIFOdata_i: in std_logic_vector(63 downto 0);
FIFOdata_o: out std_logic_vector(63 downto 0);
FIFOreset_o: out std_logic;
writeFIFOempty_i: in std_logic;
TWOeInProgress_i: in std_logic;
WBbusy_o: out std_logic
);
end component;
component IRQ_controller is
port(
clk_i : in std_logic;
reset_i : in std_logic;
VME_IRQ_n_o : out std_logic_vector(6 downto 0);
VME_IACKIN_n_i : in std_logic;
VME_IACKOUT_n_o : out std_logic;
VME_AS_n_i : in STD_LOGIC;
VME_DS_n_i : in STD_LOGIC_VECTOR(1 downto 0);
irqDTACK_o : out std_logic;
IACKinProgress_o: out std_logic;
IRQ_i: in std_logic;
locAddr_i: in std_logic_vector(3 downto 1);
IDtoData_o: out std_logic;
IRQlevelReg_i: in std_logic_vector(7 downto 0)
);
end component;
component CR
port (
addra : in STD_LOGIC_VECTOR(11 downto 0);
clka : in STD_LOGIC;
douta : out STD_LOGIC_VECTOR(7 downto 0)
);
end component;
component CRAM is
port (
clka: IN std_logic;
wea: IN std_logic_VECTOR(0 downto 0);
addra: IN std_logic_VECTOR(8 downto 0);
dina: IN std_logic_VECTOR(7 downto 0);
douta: OUT std_logic_VECTOR(7 downto 0));
end component;
component FIFO is
port (
clk: IN std_logic;
din: IN std_logic_VECTOR(63 downto 0);
rd_en: IN std_logic;
rst: IN std_logic;
wr_en: IN std_logic;
dout: OUT std_logic_VECTOR(63 downto 0);
empty: OUT std_logic;
full: OUT std_logic);
end component;
signal s_CRAMdataOut: std_logic_vector(7 downto 0);
signal s_CRAMaddr: std_logic_vector(18 downto 0);
signal s_CRAMdataIn: std_logic_vector(7 downto 0);
signal s_CRAMwea: std_logic;
signal s_CRaddr: std_logic_vector(18 downto 0);
signal s_CRdata: std_logic_vector(7 downto 0);
signal s_RW: std_logic;
signal s_lock: std_logic;
signal s_locAddr: std_logic_vector(63 downto 0);
signal s_WBdataIn: std_logic_vector(63 downto 0);
signal s_WBdataOut: std_logic_vector(63 downto 0);
signal s_WBsel: std_logic_vector(7 downto 0);
signal s_memAckWB: std_logic;
signal s_memReq: std_logic;
signal s_IRQ: std_logic;
signal s_cyc: std_logic;
signal s_reset: std_logic;
signal s_err: std_logic;
signal s_rty: std_logic;
signal s_irqDTACK: std_logic;
signal s_IACKinProgress: std_logic;
signal s_IRQlevelReg: std_logic_vector(7 downto 0);
signal s_IDtoData: std_logic;
signal s_FIFOreadWren: std_logic;
signal s_FIFOwriteWren: std_logic;
signal s_FIFOwriteDin: std_logic_vector(63 downto 0);
signal s_FIFOreadDout: std_logic_vector(63 downto 0);
signal s_FIFOwriteDout: std_logic_vector(63 downto 0);
signal s_FIFOreadDin: std_logic_vector(63 downto 0);
signal s_FIFOreadEmpty: std_logic;
signal s_FIFOwriteEmpty: std_logic;
signal s_FIFOfull: std_logic;
signal s_FIFOwriteRden: std_logic;
signal s_FIFOreadRden: std_logic;
signal s_wbFIFOreset: std_logic;
signal s_FIFOreset: std_logic;
signal s_TWOeInProgress: std_logic;
signal s_WBbusy: std_logic;
signal s_beatCount: std_logic_vector(7 downto 0);
begin
-- Uncomment this section for use of external CR and CRAM
--s_CRAMdataOut <= CRAMdata_i;
--CRAMaddr_o <= s_CRAMaddr;
--CRAMdata_o <= s_CRAMdataIn;
--CRAMwea_o <= s_CRAMwea;
--CRaddr_o <= s_CRaddr;
--s_CRdata <= CRdata_i;
s_FIFOreset <= s_wbFIFOreset or s_reset;
VME_bus_1 : VME_bus
port map(
VME_AM_i => VME_AM_i,
VME_AS_n_i => VME_AS_n_i,
VME_DS_n_i => VME_DS_n_i,
VME_GA_i => VME_GA_i,
VME_RST_n_i => VME_RST_n_i,
VME_WRITE_n_i => VME_WRITE_n_i,
VME_BERR_n_o => VME_BERR_n_o,
VME_DTACK_n_o => VME_DTACK_n_o,
VME_RETRY_n_o => VME_RETRY_n_o,
VME_ADDR_b => VME_ADDR_b,
VME_DATA_b => VME_DATA_b,
VME_LWORD_n_b => VME_LWORD_n_b,
VME_BBSY_n_i => VME_BBSY_n_i,
VME_IACKIN_n_i => VME_IACKIN_n_i,
VME_DTACK_OE_o => VME_DTACK_OE_o,
VME_DATA_DIR_o => VME_DATA_DIR_o,
VME_DATA_OE_o => VME_DATA_OE_n_o,
VME_ADDR_DIR_o => VME_ADDR_DIR_o,
VME_ADDR_OE_o => VME_ADDR_OE_n_o,
clk_i => clk_i,
reset_o => s_reset,
CRAMdata_i => s_CRAMdataOut,
CRAMaddr_o => s_CRAMaddr,
CRAMdata_o => s_CRAMdataIn,
CRAMwea_o => s_CRAMwea,
CRaddr_o => s_CRaddr,
CRdata_i => s_CRdata,
RW_o => s_RW,
lock_o => s_lock,
cyc_o => s_cyc,
locAddr_o => s_locAddr,
wbData_o => s_WBdataIn,
wbData_i => s_WBdataOut,
wbSel_o => s_WBsel,
memAckWB_i => s_memAckWB,
memReq_o => s_memReq,
err_i => s_err,
rty_i => s_rty,
beatCount_o => s_beatCount,
irqDTACK_i => s_irqDTACK,
IACKinProgress_i => s_IACKinProgress,
IDtoData_i => s_IDtoData,
IRQlevelReg_o => s_IRQlevelReg,
FIFOwren_o => s_FIFOwriteWren,
FIFOdata_o => s_FIFOwriteDin,
FIFOrden_o => s_FIFOreadRden,
FIFOdata_i => s_FIFOreadDout,
TWOeInProgress_o => s_TWOeInProgress,
WBbusy_i => s_WBbusy,
readFIFOempty_i => s_FIFOreadEmpty
);
WB_bus_1: WB_bus
port map(
clk_i => clk_i,
reset_i => s_reset,
RST_i => RST_i,
DAT_i => DAT_i,
DAT_o => DAT_o,
ADR_o => ADR_o,
CYC_o => CYC_o,
ERR_i => ERR_i,
LOCK_o => LOCK_o,
RTY_i => RTY_i,
SEL_o => SEL_o,
STB_o => STB_o,
ACK_i => ACK_i,
WE_o => WE_o,
STALL_i => STALL_i,
memReq_i => s_memReq,
memAck_o => s_memAckWB,
locData_o => s_wbDataOut,
locData_i => s_wbDataIn,
locAddr_i => s_locAddr,
sel_i => s_wbSel,
RW_i => s_RW,
lock_i => s_lock,
err_o => s_err,
rty_o => s_rty,
cyc_i => s_cyc,
beatCount_i => s_beatCount,
FIFOrden_o => s_FIFOwriteRden,
FIFOwren_o => s_FIFOreadWren,
FIFOdata_i => s_FIFOwriteDout,
FIFOdata_o => s_FIFOreadDin,
FIFOreset_o => s_wbFIFOreset,
writeFIFOempty_i => s_FIFOwriteEmpty,
TWOeInProgress_i => s_TWOeInProgress,
WBbusy_o => s_WBbusy
);
IRQ_controller_1: IRQ_controller
port map(
clk_i => clk_i,
reset_i => s_reset,
VME_IRQ_n_o => VME_IRQ_n_o,
VME_IACKIN_n_i => VME_IACKIN_n_i,
VME_IACKOUT_n_o => VME_IACKOUT_n_o,
VME_AS_n_i => VME_AS_n_i,
VME_DS_n_i => VME_DS_n_i,
irqDTACK_o => s_irqDTACK,
IACKinProgress_o => s_IACKinProgress,
IRQ_i => IRQ_i,
locAddr_i => s_locAddr(3 downto 1),
IDtoData_o => s_IDtoData,
IRQlevelReg_i => s_IRQlevelReg
);
-- Comment this component instance for use of external CR
CR_1 : CR
port map(
addra => s_CRaddr(11 downto 0),
clka => clk_i,
douta => s_CRdata
);
-- Comment this component instance for use of external CRAM
CRAM_1: CRAM
port map(
clka => clk_i,
wea(0) => s_CRAMwea,
addra => s_CRAMaddr(8 downto 0),
dina => s_CRAMdataIn,
douta => s_CRAMdataOut
);
FIFO_write: FIFO
port map(
clk => clk_i,
din => s_FIFOwriteDin,
rd_en => s_FIFOwriteRden,
rst => s_FIFOreset,
wr_en => s_FIFOwriteWren,
dout => s_FIFOwriteDout,
empty => s_FIFOwriteEmpty,
full => s_FIFOfull
);
FIFO_read: FIFO
port map(
clk => clk_i,
din => s_FIFOreadDin,
rd_en => s_FIFOreadRden,
rst => s_FIFOreset,
wr_en => s_FIFOreadWren,
dout => s_FIFOreadDout,
empty => s_FIFOreadEmpty,
full => open
);
end RTL;
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.numeric_std.all;
use work.VME_pack.all;
package VME_CR_pack is
constant c_cr_array : t_cr_array(2**12 downto 0) :=
(
16#00# => (others => '0'),
-- Length of ROM
16#01# => x"01",
16#02# => x"00",
16#03# => x"00",
--Configuration ROM data acces width
16#04# => x"00",
--Configuration ROM data acces width
16#05# => x"01",
--Ascii "C"
16#06# => x"01",
--Ascii "R"
16#07# => x"43",
--Manufacturer's ID
16#08# => x"52",
16#09# => x"01",
16#0A# => x"02",
--board id
16#0B# => x"03",
16#0C# => x"03",
16#0D# => x"04",
16#0E# => x"04",
--Rev id
16#0F# => x"03",
16#10# => x"03",
16#11# => x"04",
16#12# => x"04",
--Point to ascii null terminatied
16#13# => x"03",
16#14# => x"03",
16#15# => x"04",
--Program Id code
16#1E# => x"12",
--Function data access width
16#40# => x"85", -- Fun 0 D32
16#41# => x"85", -- Fun 1 D32
16#42# => x"85", -- Fun 2
16#43# => x"85", -- Fun 3
16#44# => x"85", -- Fun 4
16#45# => x"85", -- Fun 5
16#46# => x"85", -- Fun 6
16#47# => x"85", -- Fun 7
--Function AM code Mask
16#48# => x"00", -- Fun 0
16#49# => x"00", -- Fun 0
16#4A# => x"00", -- Fun 0
16#4B# => x"01", -- Fun 0 X"01" AM=20
16#4C# => x"00", -- Fun 0
16#4D# => x"00", -- Fun 0
16#4E# => x"00", -- Fun 0
16#4F# => x"00", -- Fun 0
16#50# => x"03", -- Fun 1 x"02" AM=39, AM=38
16#51# => x"00", -- Fun 1
16#52# => x"00", -- Fun 1
16#53# => x"00", -- Fun 1
16#54# => x"00", -- Fun 1
16#55# => x"00", -- Fun 1
16#56# => x"00", -- Fun 1
16#57# => x"00", -- Fun 1
--
--
16#58# => x"03", -- Fun 2 x"02" AM=39, AM=38
16#59# => x"00", -- Fun 2
16#5a# => x"00", -- Fun 2
16#5b# => x"00", -- Fun 2
16#5c# => x"00", -- Fun 2
16#5d# => x"00", -- Fun 2
16#5e# => x"00", -- Fun 2 X"10" AM=0c
16#5f# => x"00", -- Fun 2
--
--
16#60# => x"00", -- Fun 3
16#61# => x"00", -- Fun 3
16#62# => x"00", -- Fun 3
16#63# => x"00", -- Fun 3
16#64# => x"00", -- Fun 3
16#65# => x"00", -- Fun 3
16#66# => x"03", -- Fun 3
16#67# => x"00", -- Fun 3
--
16#68# => x"00", -- Fun 4
16#69# => x"00", -- Fun 4
16#6a# => x"00", -- Fun 4
16#6b# => x"00", -- Fun 4
16#6c# => x"00", -- Fun 4
16#6d# => x"00", -- Fun 4
16#6e# => x"03", -- Fun 4
16#6f# => x"00", -- Fun 4
--XAMCAP
16#88# => x"00", -- Fun 0 XAMCAP MSB
16#a5# => x"06", -- Fun 0 XAMCAP=0x11
16#A7# => x"00",
16#108# => x"00", -- Fun 4 XAMCAP MSB
16#109# => x"06", -- Fun 4 XAMCAP=0x11
16#10a# => x"00", -- Fun 4
--...
--16#C6# => x"00", -- Fun 0 XAMCAP LSB
--16#C7# => x"01", -- Fun 0 XAMCAP LSB
--......
-- Address Decoder Mask ADEM
16#188# => x"00", -- Fun 0
16#189# => x"00", -- Fun 0
16#18A# => x"00", -- Fun 0
16#18B# => x"05", -- Fun 0
16#18c# => x"ff", -- Fun 1
16#18d# => x"ff", -- Fun 1
16#18e# => x"00", -- Fun 1
16#18f# => x"00", -- Fun 1
16#190# => x"00", -- Fun 2
16#191# => x"e0", -- Fun 2
16#192# => x"00", -- Fun 2
16#193# => x"00", -- Fun 2
16#194# => x"ff", -- Fun 3
16#195# => x"00", -- Fun 3
16#196# => x"00", -- Fun 3
16#197# => x"00", -- Fun 3
others => (others => '0'));
end VME_CR_pack;
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.numeric_std.all;
--type is array(BAR downto IRQ_level) of unsigned(7 downto 0);
use work.VME_pack.all;
package VME_CSR_pack is
constant c_csr_array : t_CSRarray :=
(
BAR => x"00", --CR/CSR BAR
BIT_SET_CLR_REG => x"00", --Bit set register
USR_BIT_SET_CLR_REG => x"00", --Bit clear register
CRAM_OWNER => x"00", --CRAM_OWNER
FUNC0_ADER_0 =>x"44",
FUNC0_ADER_1 =>x"00",
FUNC0_ADER_2 =>x"00",
FUNC0_ADER_3 =>x"00",
FUNC1_ADER_0 =>x"00",
FUNC1_ADER_1 =>x"00",
FUNC1_ADER_2 =>x"34",
FUNC1_ADER_3 =>x"12",
FUNC2_ADER_0 =>x"e4",
FUNC2_ADER_1 =>x"00",
FUNC2_ADER_2 =>x"80",
FUNC2_ADER_3 =>x"00",
FUNC3_ADER_0 =>x"24",
FUNC3_ADER_1 =>x"00",
FUNC3_ADER_2 =>x"00",
FUNC3_ADER_3 =>x"80",
FUNC4_ADER_0 =>x"44",
FUNC4_ADER_1 =>x"00",
FUNC4_ADER_2 =>x"00",
FUNC4_ADER_3 =>x"00",
FUNC5_ADER_0 =>x"00",
FUNC5_ADER_1 =>x"00",
FUNC5_ADER_2 =>x"34",
FUNC5_ADER_3 =>x"11",
others => (others => '0'));
-- constant BAR : integer := 255;
-- constant BIT_SET_CLR_REG : integer := 254;
-- constant USR_BIT_SET_CLR_REG : integer := 253;
-- constant CRAM_OWNER : integer := 252;
--
-- constant FUNC7_ADER_0 : integer := 251;
-- constant FUNC7_ADER_1 : integer := FUNC7_ADER_0 - 1;
-- constant FUNC7_ADER_2 : integer := FUNC7_ADER_0 - 2;
-- constant FUNC7_ADER_3 : integer := FUNC7_ADER_0 - 3;
-- constant FUNC6_ADER_0 : integer := FUNC7_ADER_0 - 4;
-- constant FUNC6_ADER_1 : integer := FUNC7_ADER_0 - 5;
-- constant FUNC6_ADER_2 : integer := FUNC7_ADER_0 - 6;
-- constant FUNC6_ADER_3 : integer := FUNC7_ADER_0 - 7;
-- constant FUNC5_ADER_0 : integer := FUNC7_ADER_0 - 8;
-- constant FUNC5_ADER_1 : integer := FUNC7_ADER_0 - 9;
-- constant FUNC5_ADER_2 : integer := FUNC7_ADER_0 - 10;
-- constant FUNC5_ADER_3 : integer := FUNC7_ADER_0 - 11;
-- constant FUNC4_ADER_0 : integer := FUNC7_ADER_0 - 12;
-- constant FUNC4_ADER_1 : integer := FUNC7_ADER_0 - 13;
-- constant FUNC4_ADER_2 : integer := FUNC7_ADER_0 - 14;
-- constant FUNC4_ADER_3 : integer := FUNC7_ADER_0 - 15;
-- constant FUNC3_ADER_0 : integer := FUNC7_ADER_0 - 16;
-- constant FUNC3_ADER_1 : integer := FUNC7_ADER_0 - 17;
-- constant FUNC3_ADER_2 : integer := FUNC7_ADER_0 - 18;
-- constant FUNC3_ADER_3 : integer := FUNC7_ADER_0 - 19;
-- constant FUNC2_ADER_0 : integer := FUNC7_ADER_0 - 20;
-- constant FUNC2_ADER_1 : integer := FUNC7_ADER_0 - 21;
-- constant FUNC2_ADER_2 : integer := FUNC7_ADER_0 - 22;
-- constant FUNC2_ADER_3 : integer := FUNC7_ADER_0 - 23;
-- constant FUNC1_ADER_0 : integer := FUNC7_ADER_0 - 24;
-- constant FUNC1_ADER_1 : integer := FUNC7_ADER_0 - 25;
-- constant FUNC1_ADER_2 : integer := FUNC7_ADER_0 - 26;
-- constant FUNC1_ADER_3 : integer := FUNC7_ADER_0 - 27;
-- constant FUNC0_ADER_0 : integer := FUNC7_ADER_0 - 28;
-- constant FUNC0_ADER_1 : integer := FUNC7_ADER_0 - 29;
-- constant FUNC0_ADER_2 : integer := FUNC7_ADER_0 - 30;
-- constant FUNC0_ADER_3 : integer := FUNC7_ADER_0 - 31;
end VME_CSR_pack;
-------------------------------------------------------------------------------
--
-- Title : VME_bus
-- Design : VME64xCore
-- Author : Ziga Kroflic
-- Company : Cosylab
--
-------------------------------------------------------------------------------
--
-- File : VME_bus.vhd
-- Generated : Wed Mar 10 09:27:09 2010
-- From : interface description file
-- By : Itf2Vhdl ver. 1.20
--
-------------------------------------------------------------------------------
--
-- Description :
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.numeric_std.all;
--use IEEE.STD_LOGIC_unsigned.all;
use work.VME_pack.all;
use work.VME_CR_pack.all;
use work.VME_CSR_pack.all;
entity VME_bus is
port(
clk_i : in std_logic;
reset_o : out std_logic;
-- VME signals
VME_RST_n_i : in std_logic;
VME_AS_n_i : in std_logic;
VME_LWORD_n_b_o : out std_logic;
VME_LWORD_n_b_i : in std_logic;
VME_RETRY_n_o : out std_logic;
VME_RETRY_OE_n_o : out std_logic;
VME_WRITE_n_i : in std_logic;
VME_DS_n_i : in std_logic_vector(1 downto 0);
VME_GA_i : in std_logic_vector(5 downto 0); -- Geographical Address and GA parity
VME_DTACK_n_o : out std_logic;
VME_DTACK_OE_o : out std_logic;
VME_BERR_o : out std_logic;
VME_ADDR_b_i : in std_logic_vector(31 downto 1);
VME_ADDR_b_o : out std_logic_vector(31 downto 1);
VME_ADDR_DIR_o : out std_logic;
VME_ADDR_OE_o : out std_logic;
VME_DATA_b_i : in std_logic_vector(31 downto 0);
VME_DATA_b_o : out std_logic_vector(31 downto 0);
VME_DATA_DIR_o : out std_logic;
VME_DATA_OE_o : out std_logic;
VME_AM_i : in std_logic_vector(5 downto 0);
VME_BBSY_n_i : in std_logic;
VME_IACKIN_n_i : in std_logic;
-- CROM
CRaddr_o : out std_logic_vector(18 downto 0);
CRdata_i : in std_logic_vector(7 downto 0);
-- CRAM
CRAMaddr_o : out std_logic_vector(18 downto 0);
CRAMdata_o : out std_logic_vector(7 downto 0);
CRAMdata_i : in std_logic_vector(7 downto 0);
CRAMwea_o : out std_logic;
-- WB signals
memReq_o : out std_logic;
memAckWB_i : in std_logic;
wbData_o : out std_logic_vector(63 downto 0);
wbData_i : in std_logic_vector(63 downto 0);
locAddr_o : out std_logic_vector(63 downto 0);
wbSel_o : out std_logic_vector(7 downto 0);
RW_o : out std_logic;
lock_o : out std_logic;
cyc_o : out std_logic;
err_i : in std_logic;
rty_i : in std_logic;
stall_i : in std_logic;
psize_o : out std_logic_vector(7 downto 0);
-- IRQ controller signals
irqDTACK_i : in std_logic;
IACKinProgress_i : in std_logic;
IDtoData_i : in std_logic;
IRQlevelReg_o : out std_logic_vector(7 downto 0);
-- 2e related signals
-- FIFOwren_o : out std_logic;
-- FIFOdata_o : out std_logic_vector(63 downto 0);
-- FIFOrden_o : out std_logic;
-- FIFOdata_i : in std_logic_vector(63 downto 0);
transfer_done_i : in std_logic;
TWOeInProgress_o : out std_logic
);
end VME_bus;
architecture RTL of VME_bus is
component RegInputSample is
generic(
width : natural := 8
);
port (
reg_i : in std_logic_vector(width-1 downto 0);
reg_o : out std_logic_vector(width-1 downto 0) := (others => '0');
clk_i : in std_logic
);
end component;
component DoubleRegInputSample is
generic(
width : natural := 8
);
port (
reg_i : in std_logic_vector(width-1 downto 0);
reg_o : out std_logic_vector(width-1 downto 0) := (others => '0');
clk_i : in std_logic
);
end component;
component SigInputSample is
port (
sig_i, clk_i : in std_logic;
sig_o : out std_logic);
end component;
component DoubleSigInputSample is
port (
sig_i, clk_i : in std_logic;
sig_o : out std_logic);
end component;
component RisEdgeDetection is
port (
sig_i, clk_i : in std_logic;
RisEdge_o : out std_logic);
end component;
component FallingEdgeDetection is
port (
sig_i, clk_i : in std_logic;
FallEdge_o : out std_logic);
end component;
component EdgeDetection is
port (
sig_i,
clk_i : in std_logic;
sigEdge_o : out std_logic := '0'
);
end component;
signal s_reset : std_logic;
signal s_moduleEnable : std_logic;
-- Oversampled input signals
signal VME_RST_n_oversampled : std_logic;
signal VME_AS_n_oversampled : std_logic;
signal VME_LWORD_n_oversampled : std_logic;
--signal VME_RETRY_n_oversampled : STD_LOGIC;
signal VME_WRITE_n_oversampled : std_logic;
signal VME_DS_n_oversampled, VME_DS_n_oversampled_1 : std_logic_vector(1 downto 0);
signal VME_GA_oversampled : std_logic_vector(5 downto 0);
signal VME_ADDR_oversampled : std_logic_vector(31 downto 1);
signal VME_DATA_oversampled : std_logic_vector(31 downto 0);
signal VME_AM_oversampled : std_logic_vector(5 downto 0);
signal VME_BBSY_n_oversampled : std_logic;
signal VME_IACKIN_n_oversampled : std_logic;
-- Bidirectional signals
signal s_VMEaddrInput : unsigned(31 downto 1);
--signal s_VMEaddrOutput: unsigned(31 downto 1);
signal s_VMEdataInput : unsigned(31 downto 0);
--signal s_VMEdataOutput: unsigned(31 downto 0);
signal s_LWORDinput : std_logic;
--signal s_LWORDoutput: std_logic;
-- External latch signals
signal s_dtackOE : std_logic;
signal s_dataDir : std_logic;
signal s_dataOE : std_logic;
signal s_addrDir : std_logic;
signal s_addrOE : std_logic;
-- Local data & address
signal s_locDataIn : unsigned(63 downto 0);
signal s_locDataOut : unsigned(63 downto 0);
signal s_locData : unsigned(63 downto 0); -- Local data
signal s_locAddr : unsigned(63 downto 0); -- Local address
signal s_locAddr2e : unsigned(63 downto 0); -- Local address for 2e transfers
signal s_locAddrBeforeOffset : unsigned(63 downto 0);
signal s_phase1addr : unsigned(63 downto 0); -- Stores received address in a certain address phase (for 2e transfers)
signal s_phase2addr : unsigned(63 downto 0); --
signal s_phase3addr : unsigned(63 downto 0); --
signal s_addrOffset : unsigned(17 downto 0); -- Offset to the initial address (for block transfers)
signal s_CrCsrOffsetAddr, s_CrCsrOffsetAderIndex_aux : unsigned(18 downto 0); -- Offset to the initial CR/CSR address (for block transfers)
signal s_CrCsrOffsetAderIndex : unsigned(9 downto 0);
-- Latched signals
signal s_VMEaddrLatched : unsigned(63 downto 1); -- Stores address on falling edge of AS
signal s_LWORDlatched : std_logic; -- Stores LWORD on falling edge of AS
signal s_DSlatched : std_logic_vector(1 downto 0); -- Stores DS
signal s_AMlatched : std_logic_vector(5 downto 0); -- Stores AM on falling edge of AS
-- Type of data transfer (depending on VME_DS_n, VME_LWORD_n and VME_ADDR(1))
type t_typeOfDataTransfer is (D08,
D16,
D32,
UnAl0to2,
UnAl1to3,
UnAl1to2,
TypeError
);
signal s_typeOfDataTransfer : t_typeOfDataTransfer;
signal s_typeOfDataTransferSelect : std_logic_vector(3 downto 0);
-- Addressing type (depending on VME_AM)
type t_addressingType is (A24,
A24_BLT,
A24_MBLT,
A24_LCK,
CR_CSR,
A16,
A16_LCK,
A32,
A32_BLT,
A32_MBLT,
A32_LCK,
A64,
A64_BLT,
A64_MBLT,
A64_LCK,
TWOedge,
AM_Error
);
signal s_addressingType : t_addressingType;
signal s_addressingTypeSelect : std_logic_vector(5 downto 0);
type t_transferType is (SINGLE,
BLT,
MBLT,
LCK,
error
);
signal s_transferType : t_transferType;
type t_XAMtype is (A32_2eVME,
A64_2eVME,
A32_2eSST,
A64_2eSST,
A32_2eSSTb,
A64_2eSSTb,
XAM_error
);
signal s_XAMtype : t_XAMtype;
type t_2eType is (TWOe_VME,
TWOe_SST
);
signal s_2eType : t_2eType;
-- Main FSM signals
type t_mainFSMstates is (IDLE,
DECODE_ACCESS,
WAIT_FOR_DS,
LATCH_DS,
CHECK_TRANSFER_TYPE,
MEMORY_REQ,
DATA_TO_BUS,
DTACK_LOW,
DECIDE_NEXT_CYCLE,
INCREMENT_ADDR,
SET_DATA_PHASE,
ACKNOWLEDGE_LOCK,
WAIT_FOR_DS_2e,
ADDR_PHASE_1,
ADDR_PHASE_2,
ADDR_PHASE_3,
DECODE_ACCESS_2e,
DTACK_PHASE_1,
DTACK_PHASE_2,
DTACK_PHASE_3,
TWOe_FIFO_WRITE,
TWOe_TOGGLE_DTACK,
TWOe_WAIT_FOR_DS1,
TWOe_FIFO_WAIT_READ,
TWOe_FIFO_READ,
TWOe_CHECK_BEAT,
TWOe_RELEASE_DTACK,
TWOe_END_1,
TWOe_END_2
);
signal s_mainFSMstate : t_mainFSMstates;
signal s_dataToAddrBus : std_logic; -- Puts data to VME data and address bus (for D64)
signal s_dataToOutput : std_logic; -- Puts data to VME data bus
signal s_mainDTACK : std_logic; -- DTACK driving
signal s_2eLatchAddr : std_logic_vector(1 downto 0); -- Stores address in different address phases (for 2e transfers)
-- signal s_readFIFO : std_logic; -- FIFO memory request
--signal s_dataWidth: std_logic_vector(1 downto 0); -- Tells WB the width of valid data
signal s_addrWidth : std_logic_vector(1 downto 0); -- Width of valid address
signal s_memAck : std_logic; -- Memory acknowledge (from CR/CSR or from WB)
signal s_memAckCSR : std_logic_vector(2 downto 0); -- Memory acknowledge from CR/CSR (shift register for delaying of the acknowledge)
signal s_memReq : std_logic; -- Global memory request
signal s_VMEaddrLatch : std_logic; -- Stores address on falling edge of VME_AS_n_i
signal s_DSlatch : std_logic; -- Stores data strobes
signal s_incrementAddr : std_logic; -- Increments local address (pulse on rising edge)
signal s_incrementAddr_1 : std_logic; --
signal s_incrementAddrPulse : std_logic; --
signal s_resetAddrOffset : std_logic; -- Resets address offset
signal s_blockTransferLimit : std_logic; -- Block transfer is limited to 255 bytes
signal s_blockTransferLimitPulse : std_logic; -- Rising edge on s_blockTransferLimit
signal s_mainFSMreset : std_logic; -- Resets main FSM on rising edge of address strobe
signal s_dataPhase : std_logic; -- Indicates that multiplexed transfer is in data phase
signal s_transferActive : std_logic; -- Indicates an active VME transfer
signal s_setLock : std_logic; -- Sets LOCK towards WB slave
signal s_TWOeInProgress : std_logic; -- Indicates that 2eSST is in progress
signal s_retry : std_logic; -- RETRY signal
signal s_berr : std_logic; -- BERR signal
signal s_berr_1 : std_logic; -- Berr condition must be active for at least two cycles
signal s_berr_2 : std_logic; --
-- Access decode signals
signal s_confAccess : std_logic; -- Asserted when CR or CSR is addressed
signal s_cardSel : std_logic; -- Asserted when internal memory space is addressed
signal s_lockSel : std_logic; -- Asserted when function losk is correctly addressed
--signal s_memAckCaseCondition: std_logic_vector(1 downto 0); -- Used in p_memAck for case condition
signal s_XAM : unsigned(7 downto 0); -- Stores received XAM
-- type t_funcMatch is array (0 to 7) of std_logic; -- Indicates that a certain function has been sucesfully decoded
signal s_funcMatch : std_logic_vector(7 downto 0);
-- type t_AMmatch is array (0 to 7) of std_logic; -- Indicates that received AM matches the one programmed in ADER
signal s_AMmatch : std_logic_vector(7 downto 0);
-- WishBone signals
signal s_sel : std_logic_vector(7 downto 0); -- SEL WB signal
signal s_RW : std_logic; -- RW WB signal
signal s_lock : std_logic; -- LOCK WB signal
signal s_cyc : std_logic; -- CYC WB signal
-- 2e related signals
signal s_beatCount : unsigned(8 downto 0); -- cycleCount*2 for 2eVME, cycleCount for 2eSST
signal s_runningBeatCount : unsigned(8 downto 0); -- Beat counter
signal s_beatCountEnd : std_logic; -- Indicates that data transfer is over
signal s_cycleCount : unsigned(7 downto 0); -- Stores received cycle count
signal s_DS1pulse : std_logic; -- Pulse on rising and falling edge of DS1
-- CR/CSR related signals
signal s_CRaddressed : std_logic; -- Indicates tha CR is addressed
signal s_CRAMaddressed : std_logic; -- Indicates tha CRAM is addressed
signal s_CSRaddressed : std_logic; -- Indicates tha CSR space is addressed
signal s_CSRdata : unsigned(7 downto 0); -- Carries data for CSR write/read
signal s_CRdataIn : std_logic_vector(7 downto 0); -- CR data bus
signal s_CRAMdataIn : std_logic_vector(7 downto 0); -- CRAM data bus
signal s_bar_written : std_logic;
-- Control Status Registers
signal s_CSRarray : t_CSRarray; --:= c_csr_array(t_CSRarray'range); -- Array of CSR registers
signal s_BitSetReg : unsigned(7 downto 0); -- Bit set register
signal s_BitClrReg : unsigned(7 downto 0); -- Bit clear register
signal s_UsrBitSetReg : unsigned(7 downto 0); -- User bit set register
signal s_UsrBitClrReg : unsigned(7 downto 0); -- User bit clear register
type t_FUNC_32b_array is array (0 to 7) of unsigned(31 downto 0); -- ADER register array
type t_FUNC_64b_array is array (0 to 7) of unsigned(63 downto 0); -- ADER register array
type t_FUNC_256b_array is array (0 to 7) of unsigned(255 downto 0); -- ADER register array
signal s_FUNC_ADER, s_FUNC_ADEM : t_FUNC_32b_array;
signal s_FUNC_AMCAP, s_FUNC_ADER_64, s_FUNC_ADEM_64 : t_FUNC_64b_array;
signal s_FUNC_XAMCAP : t_FUNC_256b_array;
signal s_GAparityMatch : std_logic; -- Indicates that geographical address is valid (parity matches)
-- CR image registers
signal s_BEG_USER_CSR : unsigned(23 downto 0);
signal s_END_USER_CSR : unsigned(23 downto 0);
signal s_BEG_USER_CR : unsigned(23 downto 0);
signal s_END_USER_CR : unsigned(23 downto 0);
signal s_BEG_CRAM : unsigned(23 downto 0);
signal s_END_CRAM : unsigned(23 downto 0);
signal s_CRregArray : t_reg52x8bit; -- CR image register array
--signal c_CRinitAddr: t_reg52x12bit;
-- Misc. signals
signal s_BERRcondition : std_logic; -- Condition for asserting BERR
signal s_irqIDdata : unsigned(7 downto 0); -- IRQ Status/ID data
-- Initialization signals
signal s_initInProgress : std_logic; -- Indicates that initialization procedure is in progress
signal s_initReadCounter : unsigned(8 downto 0); -- range 0 to 52; -- Counts read operations
signal s_latchCRdata : std_logic; -- Stores read CR data
--signal s_WrRd : std_logic;
type t_initState is (IDLE, -- Initialization procedure FSM
SET_ADDR,
GET_DATA,
END_INIT
);
signal s_initState : t_initState;
signal s_locAddr_eq_bar, s_addressingType_CR_CSR : std_logic;
signal s_amcap_match, s_xamcap_match : std_logic_vector(7 downto 0);
signal s_CRaddr, s_CRadd_offset, s_CRaddr_base : unsigned(18 downto 0);
signal s_latchCRdataPos : std_logic_vector(BEG_USER_CR to FUNC_ADEM);
signal s_DS1pulse_d : std_logic;
signal transfer_done_flag : std_logic;
signal s_is_d64 : std_logic;
begin
--------
s_is_d64 <= '1' when s_sel= "11111111" else '0';
--------
s_reset <= (not VME_RST_n_oversampled); -- or s_CSRarray(BIT_SET_CLR_REG)(7); -- hardware reset and software reset
reset_o <= s_reset;
-- added by pablo for testing. it was:'1' when IACKinProgress_i='1' else s_dtackOE;
VME_DATA_DIR_o <= s_dataDir; -- added by pablo for testing. it was:'1' when IACKinProgress_i='1' else s_dataDir;
VME_DATA_OE_o <= '0'; -- added by pablo for testing. it was: '1' when IACKinProgress_i='1' else s_dataOE;
VME_ADDR_DIR_o <= s_addrDir; -- added by pablo for testing. it was:s_addrDir;
VME_ADDR_OE_o <= '0'; -- added by pablo for testing. it was:s_addrOE;
-- Type of data transfer decoder
s_typeOfDataTransferSelect <= s_DSlatched & s_VMEaddrLatched(1) & s_LWORDlatched;
process(clk_i)
begin
if rising_edge(clk_i) then
case s_typeOfDataTransferSelect is
when "0101" => s_typeOfDataTransfer <= D08;
when "1001" => s_typeOfDataTransfer <= D08;
when "0111" => s_typeOfDataTransfer <= D08;
when "1011" => s_typeOfDataTransfer <= D08;
when "0001" => s_typeOfDataTransfer <= D16;
when "0011" => s_typeOfDataTransfer <= D16;
when "0000" => s_typeOfDataTransfer <= D32;
when "0100" => s_typeOfDataTransfer <= UnAl0to2;
when "1000" => s_typeOfDataTransfer <= UnAl1to3;
when "0010" => s_typeOfDataTransfer <= UnAl1to2;
when others => s_typeOfDataTransfer <= TypeError;
end case;
end if;
end process;
-- Address modifier decoder
s_addressingTypeSelect <= VME_AM_oversampled;
with s_addressingTypeSelect select
s_addressingType <= A24 when c_A24,
A24 when c_A24_S,
A24_BLT when c_A24_BLT,
A24_MBLT when c_A24_MBLT,
A24_LCK when c_A24_LCK,
CR_CSR when c_CR_CSR,
A16 when c_A16,
A16_LCK when c_A16_LCK,
A32 when c_A32,
A32_BLT when c_A32_BLT,
A32_MBLT when c_A32_MBLT,
A32_LCK when c_A32_LCK,
A64 when c_A64,
A64_BLT when c_A64_BLT,
A64_MBLT when c_A64_MBLT,
A64_LCK when c_A64_LCK,
TWOedge when c_TWOedge,
AM_Error when others;
s_transferType <= SINGLE when s_addressingType = A24 or s_addressingType = CR_CSR or s_addressingType = A16 or s_addressingType = A32 or s_addressingType = A64 else
BLT when s_addressingType = A24_BLT or s_addressingType = A32_BLT or s_addressingType = A64_BLT else
MBLT when s_addressingType = A24_MBLT or s_addressingType = A32_MBLT or s_addressingType = A64_MBLT else
LCK when s_addressingType = A16_LCK or s_addressingType = A24_LCK or s_addressingType = A32_LCK or s_addressingType = A64_LCK else
error;
s_addrWidth <= "00" when s_addressingType = A16 or s_addressingType = A16_LCK else
"01" when s_addressingType = A24 or s_addressingType = A24_BLT or s_addressingType = A24_MBLT or s_addressingType = CR_CSR or s_addressingType = A24_LCK else
"10" when s_addressingType = A32 or s_addressingType = A32_BLT or s_addressingType = A32_MBLT or s_addressingType = A32_LCK else
"11";
with s_XAM select
s_XAMtype <= A32_2eVME when x"01",
A64_2eVME when x"02",
A32_2eSST when x"11",
A64_2eSST when x"12",
XAM_error when others;
s_2eType <= TWOe_VME when s_XAMtype = A32_2eVME or s_XAMtype = A64_2eVME else
TWOe_SST;
--Main FSM
p_VMEmainFSM : process(clk_i)
begin
if rising_edge(clk_i) then
if s_reset = '1' or s_mainFSMreset = '1' or s_blockTransferLimitPulse = '1' or VME_IACKIN_n_oversampled = '0' then -- FSM is also reset on rising edge of address strobe (which indicates end of transfer) and on rising edge of block transfer limit signal
--s_dtackOE <= '0';
s_dataDir <= '0';
s_dataOE <= '0';
s_addrDir <= '0';
s_addrOE <= '0';
s_mainDTACK <= '1'; -- it was 'Z'
s_memReq <= '0';
s_DSlatch <= '1';
--s_WrRd <= '0';
s_incrementAddr <= '0';
s_resetAddrOffset <= '1';
s_dataPhase <= '0';
s_dataToOutput <= '0';
s_dataToAddrBus <= '0';
s_transferActive <= '0';
s_setLock <= '0';
s_cyc <= '0';
s_2eLatchAddr <= "00";
s_TWOeInProgress <= '0';
--s_readFIFO <= '0';
s_retry <= '0';
s_berr <= '0';
s_mainFSMstate <= IDLE;
transfer_done_flag <= '0';
else
case s_mainFSMstate is
when IDLE =>
-- if IACKinProgress_i='1' then
-- --s_dtackOE <= '1';
-- else
-- --s_dtackOE <= '0';
-- end if;
s_dataDir <= '0';
s_dataOE <= '0';
s_addrDir <= '0';
s_addrOE <= '0';
s_mainDTACK <= '1';
s_memReq <= '0';
s_DSlatch <= '1';
--s_WrRd <= '0';
s_incrementAddr <= '0';
s_resetAddrOffset <= '1';
s_dataPhase <= '0';
s_dataToOutput <= '0';
s_dataToAddrBus <= '0';
s_transferActive <= '0';
s_setLock <= '0';
s_cyc <= '0';
s_2eLatchAddr <= "00";
s_TWOeInProgress <= '0';
--s_readFIFO <= '0';
s_retry <= '0';
s_berr <= '0';
transfer_done_flag <= '0';
if s_VMEaddrLatch = '1' then -- If address strobe goes low, check if this slave is addressed
s_mainFSMstate <= DECODE_ACCESS;
else
s_mainFSMstate <= IDLE;
end if;
when DECODE_ACCESS =>
--s_dtackOE <= '0';
s_dataDir <= '0';
s_dataOE <= '0';
s_addrDir <= '0';
s_addrOE <= '0';
s_mainDTACK <= '1';
s_memReq <= '0';
s_DSlatch <= '1';
--s_WrRd <= '0';
s_incrementAddr <= '0';
s_resetAddrOffset <= '0';
s_dataPhase <= '0';
s_dataToOutput <= '0';
s_dataToAddrBus <= '0';
s_transferActive <= '0';
s_setLock <= '0';
s_cyc <= '0';
s_2eLatchAddr <= "00";
s_TWOeInProgress <= '0';
--s_readFIFO <= '0';
s_retry <= '0';
s_berr <= '0';
transfer_done_flag <= '0';
if s_lockSel = '1' then -- LOCK request
s_mainFSMstate <= ACKNOWLEDGE_LOCK;
elsif s_addressingType = TWOedge then -- start 2e transfer
s_mainFSMstate <= WAIT_FOR_DS_2e;
elsif s_confAccess = '1' or (s_cardSel = '1') then -- If this slave is addressed, start transfer
s_mainFSMstate <= WAIT_FOR_DS;
else
s_mainFSMstate <= DECODE_ACCESS;
end if;
when WAIT_FOR_DS =>
--s_dtackOE <= '0';
s_dataDir <= VME_WRITE_n_oversampled;
s_dataOE <= '0';
s_addrDir <= (s_is_d64) and VME_WRITE_n_oversampled;
s_addrOE <= '0';
s_mainDTACK <= '1';
s_memReq <= '0';
s_DSlatch <= '1';
--s_WrRd <= '0';
s_incrementAddr <= '0';
s_resetAddrOffset <= '0';
s_dataPhase <= s_dataPhase;
s_dataToOutput <= '0';
s_dataToAddrBus <= '0';
s_transferActive <= '0';
s_setLock <= '0';
s_cyc <= '1';
s_2eLatchAddr <= "00";
s_TWOeInProgress <= '0';
--s_readFIFO <= '0';
s_retry <= '0';
s_berr <= '0';
if VME_DS_n_oversampled /= "11" then
s_mainFSMstate <= LATCH_DS;
else
s_mainFSMstate <= WAIT_FOR_DS;
end if;
when LATCH_DS =>
--s_dtackOE <= '0';
s_dataDir <= VME_WRITE_n_oversampled;
s_dataOE <= '0';
s_addrDir <= (s_is_d64) and VME_WRITE_n_oversampled;
s_addrOE <= '0';
s_mainDTACK <= '1';
s_memReq <= '0';
s_DSlatch <= '1';
--s_WrRd <= '0';
s_incrementAddr <= '0';
s_resetAddrOffset <= '0';
s_dataPhase <= s_dataPhase;
s_dataToOutput <= '0';
s_dataToAddrBus <= '0';
s_transferActive <= '0';
s_setLock <= '0';
s_cyc <= '1';
s_2eLatchAddr <= "00";
s_TWOeInProgress <= '0';
--s_readFIFO <= '0';
s_retry <= '0';
s_berr <= '0';
s_mainFSMstate <= CHECK_TRANSFER_TYPE;
when CHECK_TRANSFER_TYPE =>
--s_dtackOE <= '0';
s_dataDir <= VME_WRITE_n_oversampled;
s_dataOE <= '0';
s_addrDir <= (s_is_d64) and VME_WRITE_n_oversampled;
s_addrOE <= '0';
s_mainDTACK <= '1';
s_memReq <= '0';
s_DSlatch <= '0';
s_incrementAddr <= '0';
s_resetAddrOffset <= '0';
s_dataPhase <= s_dataPhase;
s_dataToOutput <= '0';
s_dataToAddrBus <= '0';
s_transferActive <= '1';
s_setLock <= '0';
s_cyc <= '1';
s_2eLatchAddr <= "00";
s_TWOeInProgress <= '0';
--s_readFIFO <= '0';
s_retry <= '0';
s_berr <= '0';
if s_transferType = SINGLE or s_transferType = BLT then
s_mainFSMstate <= MEMORY_REQ;
s_memReq <= '1';
elsif s_transferType = MBLT and s_dataPhase = '0' then
s_mainFSMstate <= DTACK_LOW;
s_memReq <= '0';
elsif s_transferType = MBLT and s_dataPhase = '1' then
s_mainFSMstate <= MEMORY_REQ;
s_memReq <= '0';
end if;
when MEMORY_REQ =>
--s_dtackOE <= '1';
s_dataDir <= VME_WRITE_n_oversampled;
s_dataOE <= '1';
s_addrDir <= (s_is_d64) and VME_WRITE_n_oversampled;
s_addrOE <= '0';
s_mainDTACK <= '1';
s_memReq <= stall_i;
s_DSlatch <= '0';
s_incrementAddr <= '0';
s_resetAddrOffset <= '0';
s_dataPhase <= '1';
s_dataToOutput <= '0';
s_dataToAddrBus <= '0';
s_transferActive <= '1';
s_setLock <= '0';
s_cyc <= '1';
s_2eLatchAddr <= "00";
s_TWOeInProgress <= '0';
--s_readFIFO <= '0';
s_retry <= '0';
s_berr <= '0';
if s_memAck = '1' and s_RW = '0' then
s_mainFSMstate <= DTACK_LOW;
--s_WrRd <= '0';
elsif s_memAck = '1' and s_RW = '1' then
s_mainFSMstate <= DATA_TO_BUS;
--s_WrRd <= '0';
else
s_mainFSMstate <= MEMORY_REQ;
--s_WrRd <= VME_WRITE_n_oversampled;
end if;
when DATA_TO_BUS =>
--s_dtackOE <= '1';
s_dataDir <= VME_WRITE_n_oversampled;
s_dataOE <= '1';
s_addrDir <= (s_is_d64) and VME_WRITE_n_oversampled;
s_addrOE <= '0';
s_mainDTACK <= '1';
s_memReq <= '0';
s_DSlatch <= '0';
--s_WrRd <= '0';
s_incrementAddr <= '0';
s_resetAddrOffset <= '0';
s_dataPhase <= '1';
s_setLock <= '0';
s_cyc <= '1';
s_2eLatchAddr <= "00";
s_TWOeInProgress <= '0';
--s_readFIFO <= '0';
s_retry <= '0';
if s_transferType = MBLT then
s_dataToOutput <= '0';
s_dataToAddrBus <= '1';
else
s_dataToOutput <= '1';
s_dataToAddrBus <= '0';
end if;
s_transferActive <= '1';
s_berr <= '0';
s_mainFSMstate <= DTACK_LOW;
when DTACK_LOW =>
--s_dtackOE <= '1';
s_dataDir <= VME_WRITE_n_oversampled;
s_dataOE <= '1';
s_addrDir <= (s_is_d64) and VME_WRITE_n_oversampled;
s_addrOE <= '0';
s_mainDTACK <= '0';
s_memReq <= '0';
s_DSlatch <= '0';
--s_WrRd <= '0';
s_incrementAddr <= '0';
s_resetAddrOffset <= '0';
s_dataPhase <= s_dataPhase;
s_dataToOutput <= s_dataToOutput;
s_dataToAddrBus <= s_dataToAddrBus;
s_transferActive <= '1';
s_setLock <= '0';
s_cyc <= '1';
s_2eLatchAddr <= "00";
s_TWOeInProgress <= '0';
--s_readFIFO <= '0';
s_retry <= '0';
s_berr <= '0';
if VME_DS_n_oversampled = "11" then
s_mainFSMstate <= DECIDE_NEXT_CYCLE;
else
s_mainFSMstate <= DTACK_LOW;
end if;
when DECIDE_NEXT_CYCLE =>
--s_dtackOE <= '0';
s_dataDir <= VME_WRITE_n_oversampled;
s_dataOE <= '0';
s_addrDir <= (s_is_d64) and VME_WRITE_n_oversampled;
s_addrOE <= '0';
s_mainDTACK <= '1';
s_memReq <= '0';
s_DSlatch <= '0';
--s_WrRd <= '0';
s_incrementAddr <= '0';
s_resetAddrOffset <= '0';
s_dataPhase <= s_dataPhase;
s_dataToOutput <= '0';
s_dataToAddrBus <= '0';
s_transferActive <= '1';
s_setLock <= '0';
s_cyc <= '1';
s_2eLatchAddr <= "00";
s_TWOeInProgress <= '0';
--s_readFIFO <= '0';
s_retry <= '0';
s_berr <= '0';
if s_transferType = SINGLE then
s_mainFSMstate <= WAIT_FOR_DS;
elsif s_transferType = BLT then
s_mainFSMstate <= INCREMENT_ADDR;
elsif s_transferType = MBLT and s_dataPhase = '0' then
s_mainFSMstate <= SET_DATA_PHASE;
elsif s_transferType = MBLT and s_dataPhase = '1' then
s_mainFSMstate <= INCREMENT_ADDR;
end if;
when INCREMENT_ADDR =>
--s_dtackOE <= '0';
s_dataDir <= VME_WRITE_n_oversampled;
s_dataOE <= '0';
s_addrDir <= (s_is_d64) and VME_WRITE_n_oversampled;
s_addrOE <= '0';
s_mainDTACK <= '1';
s_memReq <= '0';
s_DSlatch <= '0';
--s_WrRd <= '0';
s_incrementAddr <= '1';
s_resetAddrOffset <= '0';
s_dataPhase <= s_dataPhase;
s_dataToOutput <= '0';
s_dataToAddrBus <= '0';
s_transferActive <= '1';
s_setLock <= '0';
s_cyc <= '1';
s_2eLatchAddr <= "00";
s_TWOeInProgress <= '0';
--s_readFIFO <= '0';
s_retry <= '0';
s_berr <= '0';
s_mainFSMstate <= WAIT_FOR_DS;
when SET_DATA_PHASE =>
--s_dtackOE <= '0';
s_dataDir <= VME_WRITE_n_oversampled;
s_dataOE <= '0';
s_addrDir <= (s_is_d64) and VME_WRITE_n_oversampled;
s_addrOE <= '0';
s_mainDTACK <= '1';
s_memReq <= '0';
s_DSlatch <= '0';
--s_WrRd <= '0';
s_incrementAddr <= '0';
s_resetAddrOffset <= '0';
s_dataPhase <= '1';
s_dataToOutput <= '0';
s_dataToAddrBus <= '0';
s_transferActive <= '1';
s_setLock <= '0';
s_cyc <= '1';
s_2eLatchAddr <= "00";
s_TWOeInProgress <= '0';
--s_readFIFO <= '0';
s_retry <= '0';
s_berr <= '0';
s_mainFSMstate <= WAIT_FOR_DS;
when ACKNOWLEDGE_LOCK =>
--s_dtackOE <= '1';
s_dataDir <= VME_WRITE_n_oversampled;
s_dataOE <= '0';
s_addrDir <= (s_is_d64) and VME_WRITE_n_oversampled;
s_addrOE <= '0';
if VME_DS_n_oversampled /= "11" then
s_mainDTACK <= '0';
else
s_mainDTACK <= '1';
end if;
s_memReq <= '0';
s_DSlatch <= '0';
--s_WrRd <= '0';
s_incrementAddr <= '0';
s_resetAddrOffset <= '0';
s_dataPhase <= '0';
s_dataToOutput <= '0';
s_dataToAddrBus <= '0';
s_transferActive <= '0';
s_setLock <= '1';
s_cyc <= '0';
s_2eLatchAddr <= "00";
s_TWOeInProgress <= '0';
--s_readFIFO <= '0';
s_retry <= '0';
s_berr <= '0';
s_mainFSMstate <= ACKNOWLEDGE_LOCK; -- wait here until AS goes high, which resets the FSM
when WAIT_FOR_DS_2e =>
--s_dtackOE <= '0';
s_dataDir <= '0';
s_dataOE <= '1';
s_addrDir <= '0';
s_addrOE <= '1';
s_mainDTACK <= '1';
s_memReq <= '0';
s_DSlatch <= '0';
--s_WrRd <= '0';
s_incrementAddr <= '0';
s_resetAddrOffset <= '0';
s_dataPhase <= '0';
s_dataToOutput <= '0';
s_dataToAddrBus <= '0';
s_transferActive <= '0';
s_setLock <= '0';
s_cyc <= '0';
s_2eLatchAddr <= "01";
s_TWOeInProgress <= '0';
--s_readFIFO <= '0';
s_retry <= '0';
s_berr <= '0';
if VME_DS_n_oversampled(0) = '0' then
s_mainFSMstate <= ADDR_PHASE_1;
end if;
when ADDR_PHASE_1 =>
--s_dtackOE <= '0';
s_dataDir <= '0';
s_dataOE <= '1';
s_addrDir <= '0';
s_addrOE <= '1';
s_mainDTACK <= '1';
--s_WrRd <= '0';
s_memReq <= '0';
s_DSlatch <= '0';
s_incrementAddr <= '0';
s_resetAddrOffset <= '0';
s_dataPhase <= '0';
s_dataToOutput <= '0';
s_dataToAddrBus <= '0';
s_transferActive <= '0';
s_setLock <= '0';
s_cyc <= '0';
s_2eLatchAddr <= "00";
s_TWOeInProgress <= '0';
--s_readFIFO <= '0';
s_retry <= '0';
s_berr <= '0';
s_mainFSMstate <= DECODE_ACCESS_2e;
when DECODE_ACCESS_2e =>
--s_dtackOE <= '1';
s_dataDir <= '0';
s_dataOE <= '1';
s_addrDir <= '0';
s_addrOE <= '1';
s_mainDTACK <= '1';
--s_WrRd <= '0';
s_memReq <= '0';
s_DSlatch <= '0';
s_incrementAddr <= '0';
s_resetAddrOffset <= '0';
s_dataPhase <= '0';
s_dataToOutput <= '0';
s_dataToAddrBus <= '0';
s_transferActive <= '0';
s_setLock <= '0';
s_cyc <= '0';
s_2eLatchAddr <= "00";
s_TWOeInProgress <= '0';
--s_readFIFO <= '0';
s_retry <= '0';
if s_XAMtype = XAM_error then
s_berr <= '1';
else
s_berr <= '0';
end if;
if s_cardSel = '1' then -- if module is selected, proceed with DTACK, else wait here until FSM reset by AS going high
s_mainFSMstate <= DTACK_PHASE_1;
end if;
when DTACK_PHASE_1 =>
--s_dtackOE <= '1';
s_dataDir <= '0';
s_dataOE <= '1';
s_addrOE <= '1';
s_addrDir <= '0';
s_mainDTACK <= '0';
--s_WrRd <= '0';
s_memReq <= '0';
s_DSlatch <= '0';
s_incrementAddr <= '0';
s_resetAddrOffset <= '0';
s_dataPhase <= '0';
s_dataToOutput <= '0';
s_dataToAddrBus <= '0';
s_transferActive <= '0';
s_setLock <= '0';
s_cyc <= '0';
s_2eLatchAddr <= "00";
s_TWOeInProgress <= '0';
--s_readFIFO <= '0';
s_retry <= '0';
s_berr <= s_berr;
if VME_DS_n_oversampled(0) = '1' and s_berr = '0' then
s_mainFSMstate <= ADDR_PHASE_2;
elsif VME_DS_n_oversampled(0) = '1' and s_berr = '1' then
s_mainFSMstate <= TWOe_RELEASE_DTACK;
end if;
when ADDR_PHASE_2 =>
--s_dtackOE <= '1';
s_dataDir <= '0';
s_dataOE <= '1';
s_addrDir <= '0';
s_addrOE <= '1';
s_mainDTACK <= '0';
--s_WrRd <= '0';
s_memReq <= '0';
s_DSlatch <= '0';
s_incrementAddr <= '0';
s_resetAddrOffset <= '0';
s_dataPhase <= '0';
s_dataToOutput <= '0';
s_dataToAddrBus <= '0';
s_transferActive <= '0';
s_setLock <= '0';
s_cyc <= '0';
s_2eLatchAddr <= "10";
s_TWOeInProgress <= '0';
--s_readFIFO <= '0';
s_retry <= '0';
s_berr <= '0';
s_mainFSMstate <= DTACK_PHASE_2;
when DTACK_PHASE_2 =>
--s_dtackOE <= '1';
s_dataDir <= '0';
s_dataOE <= '1';
s_addrDir <= '0';
s_addrOE <= '1';
s_mainDTACK <= '1';
--s_WrRd <= '0';
s_memReq <= '0';
s_DSlatch <= '0';
s_incrementAddr <= '0';
s_resetAddrOffset <= '0';
s_dataPhase <= '0';
s_dataToOutput <= '0';
s_dataToAddrBus <= '0';
s_transferActive <= '0';
s_setLock <= '0';
s_cyc <= '0';
s_2eLatchAddr <= "00";
s_TWOeInProgress <= '0';
--s_readFIFO <= '0';
s_retry <= '0';
s_berr <= '0';
if VME_DS_n_oversampled(0) = '0' then
s_mainFSMstate <= ADDR_PHASE_3;
end if;
when ADDR_PHASE_3 =>
--s_dtackOE <= '1';
s_dataDir <= '0';
s_dataOE <= '1';
s_addrDir <= '0';
s_addrOE <= '1';
s_mainDTACK <= '1';
--s_WrRd <= '0';
s_memReq <= '0';
s_DSlatch <= '0';
s_incrementAddr <= '0';
s_resetAddrOffset <= '0';
s_dataPhase <= '0';
s_dataToOutput <= '0';
s_dataToAddrBus <= '0';
s_transferActive <= '0';
s_setLock <= '0';
s_cyc <= '0';
s_2eLatchAddr <= "11";
s_TWOeInProgress <= '0';
--s_readFIFO <= '0';
if stall_i = '1' then
s_retry <= '1';
else
s_retry <= '0';
end if;
s_berr <= '0';
-- if WBbusy_i = '0' then -- Removed by pablo
s_mainFSMstate <= DTACK_PHASE_3;
-- end if;
when DTACK_PHASE_3 =>
--s_dtackOE <= '1';
s_dataDir <= '0';
s_dataOE <= '1';
s_addrDir <= '0';
s_addrOE <= '1';
s_mainDTACK <= '0';
s_DSlatch <= '0';
s_incrementAddr <= '0';
s_resetAddrOffset <= '0';
s_dataPhase <= '0';
s_dataToOutput <= '0';
s_dataToAddrBus <= '0';
s_transferActive <= '0';
s_setLock <= '0';
s_cyc <= '1';
s_2eLatchAddr <= "00";
s_TWOeInProgress <= '0';
--s_readFIFO <= '0';
s_retry <= s_retry;
s_berr <= '0';
if s_RW = '0' and s_retry = '0' then
s_mainFSMstate <= TWOe_FIFO_WRITE;
s_memReq <= '0';
elsif s_RW = '1' and s_retry = '0' then
if s_2eType = TWOe_VME then
s_mainFSMstate <= TWOe_FIFO_WAIT_READ;
s_memReq <= '0';
else
s_mainFSMstate <= TWOe_FIFO_WAIT_READ;
s_memReq <= '0';
end if;
--s_WrRd <= VME_WRITE_n_oversampled;
elsif VME_DS_n_oversampled(0) = '1' and s_retry = '1' then
s_mainFSMstate <= TWOe_RELEASE_DTACK;
s_memReq <= '0';
else
s_memReq <= '0';
end if;
when TWOe_FIFO_WRITE =>
--s_dtackOE <= '1';
s_dataDir <= '0';
s_dataOE <= '1';
s_addrDir <= '0';
s_addrOE <= '1';
s_mainDTACK <= s_mainDTACK;
s_DSlatch <= '0';
--s_WrRd <= '0';
s_incrementAddr <= '0';
s_resetAddrOffset <= '0';
s_dataPhase <= '0';
s_dataToOutput <= '0';
s_dataToAddrBus <= '0';
s_transferActive <= '0';
s_setLock <= '0';
s_cyc <= '1';
s_2eLatchAddr <= "00";
s_TWOeInProgress <= '1';
--s_readFIFO <= '0';
s_retry <= '0';
s_berr <= '0';
if s_DS1pulse = '1' and s_2eType = TWOe_VME then
s_memReq <= '1';
elsif s_DS1pulse = '1' then --VME_DS_n_oversampled(0) = '1' then
s_memReq <= '1';
else
s_memReq <= '0';
end if;
if s_DS1pulse = '1' and s_2eType = TWOe_VME then
s_mainFSMstate <= TWOe_TOGGLE_DTACK;
elsif VME_DS_n_oversampled(0) = '1' then
s_mainFSMstate <= TWOe_RELEASE_DTACK;
end if;
when TWOe_TOGGLE_DTACK =>
--s_dtackOE <= '1';
s_dataDir <= s_dataDir;
s_dataOE <= '1';
s_addrDir <= s_addrDir;
s_addrOE <= '1';
s_memReq <= '0';
s_DSlatch <= '0';
--s_WrRd <= '0';
s_incrementAddr <= '0';
s_resetAddrOffset <= '0';
s_dataPhase <= '0';
s_dataToOutput <= '0';
s_dataToAddrBus <= '0';
s_transferActive <= '0';
s_setLock <= '0';
s_cyc <= '1';
s_2eLatchAddr <= "00";
s_TWOeInProgress <= '1';
--s_readFIFO <= '0';
s_retry <= '0';
s_berr <= '0';
-- IF s_2eType = TWOe_SST
if s_RW = '0' and s_2eType = TWOe_SST then
s_mainFSMstate <= TWOe_FIFO_WRITE;
s_mainDTACK <= '0';
elsif s_RW = '1' and s_2eType = TWOe_SST then
s_mainFSMstate <= TWOe_CHECK_BEAT;
s_mainDTACK <= not s_mainDTACK;
elsif s_RW = '0' then
s_mainFSMstate <= TWOe_FIFO_WRITE;
s_mainDTACK <= not s_mainDTACK;
else
s_mainFSMstate <= TWOe_WAIT_FOR_DS1;
s_mainDTACK <= not s_mainDTACK;
end if;
when TWOe_WAIT_FOR_DS1 =>
--s_dtackOE <= '1';
s_dataDir <= s_dataDir;
s_dataOE <= '1';
s_addrDir <= s_addrDir;
s_addrOE <= '1';
s_mainDTACK <= s_mainDTACK;
s_memReq <= '0';
s_DSlatch <= '0';
--s_WrRd <= '0';
s_incrementAddr <= '0';
s_resetAddrOffset <= '0';
s_dataPhase <= '0';
s_dataToOutput <= '0';
s_dataToAddrBus <= '1';
s_transferActive <= '0';
s_setLock <= '0';
s_cyc <= '1';
s_2eLatchAddr <= "00";
s_TWOeInProgress <= '1';
--s_readFIFO <= '0';
s_retry <= '0';
s_berr <= '0';
if (s_DS1pulse = '1' and s_2eType = TWOe_VME) or s_2eType = TWOe_SST then
s_mainFSMstate <= TWOe_CHECK_BEAT;
end if;
when TWOe_FIFO_WAIT_READ =>
--s_dtackOE <= '1';
s_dataDir <= '1';
s_dataOE <= '1';
s_addrDir <= s_is_d64;
s_addrOE <= '1';
s_mainDTACK <= s_mainDTACK;
s_DSlatch <= '0';
--s_WrRd <= '0';
s_incrementAddr <= '0';
s_resetAddrOffset <= '0';
s_dataPhase <= '0';
s_dataToOutput <= '0';
s_dataToAddrBus <= '0';
s_transferActive <= '0';
s_setLock <= '0';
s_cyc <= '1';
s_2eLatchAddr <= "00";
s_TWOeInProgress <= '1';
--s_readFIFO <= '0';
s_retry <= '0';
s_berr <= '0';
-- if readFIFOempty_i = '0' then --and s_2eType=TWOe_SST then
if stall_i = '0' then --and s_2eType=TWOe_SST then
s_mainFSMstate <= TWOe_FIFO_READ;
end if;
s_memReq <= not stall_i; -- access to the wb_dma
when TWOe_FIFO_READ =>
--s_dtackOE <= '1';
s_dataDir <= '1';
s_dataOE <= '1';
s_addrDir <= s_is_d64;
s_addrOE <= '1';
s_mainDTACK <= s_mainDTACK;
s_memReq <= '0';
s_DSlatch <= '0';
s_incrementAddr <= '0';
s_resetAddrOffset <= '0';
s_dataPhase <= '0';
s_dataToOutput <= '0';
s_dataToAddrBus <= memAckWB_i;
s_transferActive <= '0';
s_setLock <= '0';
s_cyc <= '1';
s_2eLatchAddr <= "00";
s_TWOeInProgress <= '1';
--s_readFIFO <= '1';
s_retry <= '0';
s_berr <= '0';
if memAckWB_i = '1' then
s_mainFSMstate <= TWOe_TOGGLE_DTACK;
end if;
if transfer_done_i = '1' then
transfer_done_flag <= '1';
end if;
when TWOe_CHECK_BEAT =>
--s_dtackOE <= '1';
s_dataDir <= '1';
s_dataOE <= '1';
s_addrDir <= s_is_d64;
s_addrOE <= '1';
-- s_mainDTACK <= not s_mainDTACK; -- s_mainDTACK;
s_mainDTACK <= s_mainDTACK;
s_memReq <= '0';
s_DSlatch <= '0';
s_incrementAddr <= '0';
s_resetAddrOffset <= '0';
s_dataPhase <= '0';
s_dataToOutput <= '0';
s_dataToAddrBus <= '0';
s_transferActive <= '0';
s_setLock <= '0';
s_cyc <= '1';
s_2eLatchAddr <= "00";
s_TWOeInProgress <= '1';
--s_readFIFO <= '0';
s_retry <= '0';
s_berr <= '0';
if transfer_done_flag = '0' then
s_mainFSMstate <= TWOe_FIFO_WAIT_READ;
transfer_done_flag <= '0';
else
s_mainFSMstate <= TWOe_END_1;
transfer_done_flag <= '0';
end if;
s_memReq <= '0';--not stall_i; -- access to the wb_dma
when TWOe_RELEASE_DTACK =>
--s_dtackOE <= '0';
s_dataDir <= '0';
s_dataOE <= '0';
s_addrDir <= '0';
s_addrOE <= '0';
s_mainDTACK <= '1';
s_memReq <= '0';
s_DSlatch <= '0';
s_incrementAddr <= '0';
s_resetAddrOffset <= '0';
s_dataPhase <= '0';
s_dataToOutput <= '0';
s_dataToAddrBus <= '0';
s_transferActive <= '0';
s_setLock <= '0';
s_cyc <= '0';
s_2eLatchAddr <= "00";
s_TWOeInProgress <= '0';
--s_readFIFO <= '0';
s_retry <= '0';
s_berr <= '0';
s_mainFSMstate <= TWOe_RELEASE_DTACK;
when TWOe_END_1 =>
--s_dtackOE <= '1';
s_dataDir <= '0';
s_dataOE <= '0';
s_addrDir <= '0';
s_addrOE <= '0';
s_mainDTACK <= s_mainDTACK;
s_memReq <= '0';
s_DSlatch <= '0';
s_incrementAddr <= '0';
s_resetAddrOffset <= '0';
s_dataPhase <= '0';
s_dataToOutput <= '0';
s_dataToAddrBus <= '0';
s_transferActive <= '0';
s_setLock <= '0';
s_cyc <= '0';
s_2eLatchAddr <= "00";
s_TWOeInProgress <= '0';
--s_readFIFO <= '0';
s_retry <= '1';
s_berr <= '0';
s_mainFSMstate <= TWOe_END_2;
transfer_done_flag <= '0';
when TWOe_END_2 =>
--s_dtackOE <= '1';
s_dataDir <= '0';
s_dataOE <= '0';
s_addrDir <= '0';
s_addrOE <= '0';
s_mainDTACK <= s_mainDTACK;
s_memReq <= '0';
s_DSlatch <= '0';
s_incrementAddr <= '0';
s_resetAddrOffset <= '0';
s_dataPhase <= '0';
s_dataToOutput <= '0';
s_dataToAddrBus <= '0';
s_transferActive <= '0';
s_setLock <= '0';
s_cyc <= '0';
s_2eLatchAddr <= "00";
s_TWOeInProgress <= '0';
--s_readFIFO <= '0';
s_retry <= '1';
s_berr <= '1';
if VME_DS_n_oversampled = "11" then
s_mainFSMstate <= TWOe_RELEASE_DTACK;
end if;
when others =>
--s_dtackOE <= '0';
s_dataDir <= '0';
s_dataOE <= '0';
s_addrDir <= '0';
s_addrOE <= '1';
s_mainDTACK <= '1';
s_memReq <= '0';
s_DSlatch <= '0';
s_incrementAddr <= '0';
s_resetAddrOffset <= '1';
s_dataPhase <= '0';
s_dataToOutput <= '0';
s_dataToAddrBus <= '0';
s_transferActive <= '0';
s_setLock <= '0';
s_cyc <= '0';
s_2eLatchAddr <= "00";
s_TWOeInProgress <= '0';
--s_readFIFO <= '0';
s_retry <= '0';
s_berr <= '0';
s_mainFSMstate <= IDLE;
transfer_done_flag <= '0';
end case;
end if;
end if;
end process;
cyc_o <= s_cyc and s_cardSel and not (s_transferActive and s_BERRcondition);
-- FIFOwren_o <= s_DS1pulse and s_TWOeInProgress and not s_RW;
-- FIFOrden_o <= s_readFIFO;
TWOeInProgress_o <= s_TWOeInProgress;
-- RETRY driver
p_RETRYdriver: process(clk_i)
begin
if rising_edge(clk_i) then
if rty_i='1' or s_retry='1' then
VME_RETRY_n_o <= '1';
VME_RETRY_OE_n_o <= '1';
else
VME_RETRY_n_o <= '0';
VME_RETRY_OE_n_o <= '0';
end if;
end if;
end process;
-- BERR driver
p_BERRdriver: process(clk_i)
begin
if rising_edge(clk_i) then
s_berr_1 <= s_berr;
s_berr_2 <= s_berr and s_berr_1;
if (s_transferActive='1' and s_BERRcondition='1') or s_berr_2='1' then
VME_BERR_o <= '1';
else
VME_BERR_o <= '0';
end if;
end if;
end process;
process(clk_i)
begin
if rising_edge(clk_i) then
if s_transferType = error or s_typeOfDataTransfer = TypeError or err_i = '1' then
if (s_CRaddressed = '1' and s_confAccess = '1' and s_RW = '0') or (s_CSRaddressed = '1' and s_CRaddressed = '1') then
if (s_CRAMaddressed = '1' and s_CRaddressed = '1') or (s_CRAMaddressed = '1' and s_CSRaddressed = '1') then
s_BERRcondition <= '1';
else
s_BERRcondition <= '0';
end if;
else
s_BERRcondition <= '0';
end if;
else
s_BERRcondition <= '0';
end if;
end if;
end process;
-- LOCK driver
p_LOCKdriver : process(clk_i)
begin
if rising_edge(clk_i) then
if s_reset = '1' then
s_lock <= '0';
elsif VME_BBSY_n_oversampled = '1' then
s_lock <= '0';
elsif s_setLock = '1' then
s_lock <= '1';
else
s_lock <= s_lock;
end if;
end if;
end process;
lock_o <= s_lock;
-- DTACK multiplexing
-- p_DTACKmux : process(clk_i)
-- begin
-- if rising_edge(clk_i) then
---- if IACKinProgress_i='1' then
---- VME_DTACK_n_o <= irqDTACK_i;
---- s_dtackOE <= not irqDTACK_i;
---- els
-- if s_mainDTACK = '0' then
-- VME_DTACK_n_o <= '0';
-- s_dtackOE <= '1';
-- else
-- VME_DTACK_n_o <= '1';
-- s_dtackOE <= '0';
-- end if;
-- end if;
-- end process;
process(clk_i)
begin
if rising_edge(clk_i) then
VME_DTACK_n_o <= s_mainDTACK;
VME_DTACK_OE_o <= s_dataOE;
end if;
end process;
--s_dtackOE <= not s_mainDTACK;
-- Bidirectional signal handling
s_VMEaddrInput <= unsigned(VME_ADDR_oversampled);
s_LWORDinput <= VME_LWORD_n_oversampled;
s_VMEdataInput <= unsigned(VME_DATA_oversampled);
p_ADDRmux : process(clk_i)
begin
if rising_edge(clk_i) then
-- if s_dataToAddrBus = '1' and s_TWOeInProgress = '1' then
-- VME_ADDR_b_o <= FIFOdata_i(63 downto 33);
-- VME_LWORD_n_b_o <= FIFOdata_i(32);
-- els
if s_dataToAddrBus = '1' then
VME_ADDR_b_o <= std_logic_vector(s_locData(63 downto 33));
VME_LWORD_n_b_o <= s_locData(32);
-- else
-- VME_ADDR_b_o <= (others => '0');
-- VME_LWORD_n_b_o <= '0';
end if;
end if;
end process;
p_DATAmux : process(clk_i)
begin
if rising_edge(clk_i) then
-- if s_dataToAddrBus = '1' and s_TWOeInProgress = '1' then
-- VME_DATA_b_o <= FIFOdata_i(31 downto 0);
-- els
if s_dataToAddrBus = '1' or s_dataToOutput = '1' then
VME_DATA_b_o <= std_logic_vector(s_locData(31 downto 0));
elsif IDtoData_i = '1' then
VME_DATA_b_o <= "------------------------" & std_logic_vector(s_irqIDdata);
-- else
-- VME_DATA_b_o <= (others => '0');
end if;
end if;
end process;
s_irqIDdata <= s_CSRarray(IRQ_ID);
-- Local address & AM latching
p_addrLatching : process(clk_i)
begin
if rising_edge(clk_i) then
if s_reset = '1' then
s_VMEaddrLatched <= (others => '0');
s_LWORDlatched <= '0';
s_AMlatched <= (others => '0');
else
if s_VMEaddrLatch = '1' then -- Latching on falling edge of VME_AS_n_i
s_VMEaddrLatched <= unsigned(s_VMEdataInput) & s_VMEaddrInput;
s_LWORDlatched <= s_LWORDinput;
s_AMlatched <= VME_AM_oversampled;
else
s_VMEaddrLatched <= s_VMEaddrLatched;
s_LWORDlatched <= s_LWORDlatched;
s_AMlatched <= s_AMlatched;
end if;
end if;
end if;
end process;
-- Data strobe latching
p_DSlatching : process(clk_i)
begin
if rising_edge(clk_i) then
if s_DSlatch = '1' then
s_DSlatched <= VME_DS_n_oversampled;
else
s_DSlatched <= s_DSlatched;
end if;
end if;
end process;
-- 2e address phase latching
p_2eAddrLatch : process(clk_i)
begin
if rising_edge(clk_i) then
if s_reset = '1' or s_mainFSMreset = '1' then
s_phase1addr <= (others => '0');
s_phase2addr <= (others => '0');
s_phase3addr <= (others => '0');
else
case s_2eLatchAddr is
when "01" => s_phase1addr <= s_VMEdataInput & s_VMEaddrInput & s_LWORDinput;
s_phase2addr <= s_phase2addr;
s_phase3addr <= s_phase3addr;
when "10" => s_phase2addr <= s_VMEdataInput & s_VMEaddrInput & s_LWORDinput;
s_phase1addr <= s_phase1addr;
s_phase3addr <= s_phase3addr;
when "11" => s_phase3addr <= s_VMEdataInput & s_VMEaddrInput & s_LWORDinput;
s_phase1addr <= s_phase1addr;
s_phase2addr <= s_phase2addr;
when others => s_phase1addr <= s_phase1addr;
s_phase2addr <= s_phase2addr;
s_phase3addr <= s_phase3addr;
end case;
end if;
end if;
end process;
s_XAM <= s_phase1addr(7 downto 0);
s_cycleCount <= unsigned(s_phase2addr(15 downto 8));
--s_beatCount <= ((s_cycleCount)&'0') when s_XAMtype=A32_2eVME or s_XAMtype=A64_2eVME else
-- ('0'&(s_cycleCount));
process(s_cycleCount,s_beatCount,s_XAMtype, s_transferType)
begin
if ((s_XAMtype = A32_2eVME) or (s_XAMtype = A64_2eVME)) then
s_beatCount <= (resize(s_cycleCount*2, s_beatCount'length));
elsif s_transferType = SINGLE then
s_beatCount <= (to_unsigned(1, s_beatCount'length));
else
s_beatCount <= ('0'&(s_cycleCount));
end if;
end process;
--
psize_o <= std_logic_vector(s_beatCount(7 downto 0));
-- Beat counter
-- p_FIFObeatCounter : process(clk_i)
-- begin
-- if rising_edge(clk_i) then
-- if s_reset = '1' or s_resetAddrOffset = '1' then
-- s_runningBeatCount <= (others => '0');
-- elsif s_readFIFO = '1' then
-- s_runningBeatCount <= s_runningBeatCount + 1;
-- else
-- s_runningBeatCount <= s_runningBeatCount;
-- end if;
-- end if;
-- end process;
-- s_beatCountEnd <= '0' when s_runningBeatCount < s_beatCount else '1';
-- Local address mapping
s_locAddrBeforeOffset(63 downto 1) <= x"000000000000" & s_VMEaddrLatched(15 downto 1) when s_addrWidth = "00" else
x"0000000000" & s_VMEaddrLatched(23 downto 1) when s_addrWidth = "01" else
x"00000000" & s_VMEaddrLatched(31 downto 1) when s_addrWidth = "10" else
s_VMEaddrLatched(63 downto 1);
s_locAddrBeforeOffset(0) <= '0' when (s_DSlatched(1) = '0' and s_DSlatched(0) = '1') else
'1' when (s_DSlatched(1) = '1' and s_DSlatched(0) = '0') else
'0';
s_locAddr2e <= s_phase1addr(63 downto 8) & s_phase2addr(7 downto 0);
process(clk_i)
begin
if rising_edge(clk_i) then
if s_typeOfDataTransfer = UnAl1to2 then
s_locAddr <= s_locAddrBeforeOffset - 1 + s_addrOffset;
elsif s_addressingType = TWOedge then
s_locAddr <= s_locAddr2e + s_addrOffset;
else
s_locAddr <= s_locAddrBeforeOffset + s_addrOffset;
end if;
end if;
end process;
-- s_locAddr <= s_locAddrBeforeOffset - 1 + s_addrOffset when s_typeOfDataTransfer=UnAl1to2 else -- exception for UnAl1to2
-- s_locAddr2e + s_addrOffset when s_addressingType=TWOedge else
-- s_locAddrBeforeOffset + s_addrOffset;
locAddr_o <= std_logic_vector(s_locAddr);
-- Local address incrementing
p_addrIncrementing : process(clk_i)
begin
if rising_edge(clk_i) then
s_incrementAddr_1 <= s_incrementAddr;
s_incrementAddrPulse <= s_incrementAddr and (not s_incrementAddr_1);
if s_resetAddrOffset = '1' or s_reset = '1' then
s_addrOffset <= (others => '0');
elsif s_incrementAddrPulse = '1' then
if s_addressingType = TWOedge then
s_addrOffset <= s_addrOffset + 8;
elsif s_typeOfDataTransfer = D08 then
if s_locAddrBeforeOffset(0) = '1' then
s_addrOffset <= s_addrOffset + 2;
else
s_addrOffset <= s_addrOffset;
end if;
elsif s_typeOfDataTransfer = D16 then
s_addrOffset <= s_addrOffset + 2;
elsif s_typeOfDataTransfer = D32 then
if s_transferType = MBLT then
s_addrOffset <= s_addrOffset + 8;
else
s_addrOffset <= s_addrOffset + 4;
end if;
else
s_addrOffset <= s_addrOffset;
end if;
end if;
end if;
end process;
s_blockTransferLimit <= s_addrOffset(8); -- If address offset overflows, limit is reached and main FSM will be reset
BlockTransferLimitFSMresetPulse : RisEdgeDetection
port map(
sig_i => s_blockTransferLimit,
clk_i => clk_i,
RisEdge_o => s_blockTransferLimitPulse
);
-- Memory mapping
p_memoryMapping : process(clk_i)
begin
if rising_edge(clk_i) then
case s_RW is
-- Read cycles
when '1' =>
case s_typeOfDataTransfer is
when D08 =>
case s_DSlatched(1) is
when '0' => -- D08(E)
s_sel <= "00000001";
when others => -- D08(O)
s_sel <= "00000001";
end case;
when D16 => -- D16
s_sel <= "00000011";
when D32 =>
case s_transferType is
when MBLT => -- D64
s_sel <= "11111111";
when others => -- D32
s_sel <= "00001111";
end case;
when UnAl0to2 => -- Unaligned transfer byte(0-2)
s_sel <= "00000111";
when UnAl1to3 => -- Unaligned transfer byte(1-3)
s_sel <= "00000111";
when UnAl1to2 => -- Unaligned transfer byte(1-2)
s_sel <= "00000011";
when others =>
s_sel <= "11111111";
end case;
-- Write cycles
when others =>
case s_typeOfDataTransfer is
when D08 =>
case s_DSlatched(1) is
when '0' => -- D08(E)
s_locDataIn(7 downto 0) <= s_VMEdataInput(15 downto 8);
s_sel <= "00000001";
when others => -- D08(O)
s_locDataIn(7 downto 0) <= s_VMEdataInput(7 downto 0);
s_sel <= "00000001";
end case;
when D16 => -- D16
s_locDataIn(15 downto 0) <= s_VMEdataInput(15 downto 0);
s_sel <= "00000011";
when D32 =>
case s_transferType is
when MBLT => -- D64
s_locDataIn(31 downto 0) <= s_VMEdataInput(31 downto 0);
s_locDataIn(63 downto 32) <= s_VMEaddrInput(31 downto 1) & s_LWORDinput;
s_sel <= "11111111";
when others => -- D32
s_locDataIn(31 downto 0) <= s_VMEdataInput(31 downto 0);
s_sel <= "00001111";
end case;
when UnAl0to2 => -- Unaligned transfer byte(0-2)
s_locDataIn(23 downto 0) <= s_VMEdataInput(31 downto 8);
s_sel <= "00000111";
when UnAl1to3 => -- Unaligned transfer byte(1-3)
s_locDataIn(23 downto 0) <= s_VMEdataInput(23 downto 0);
s_sel <= "00000111";
when UnAl1to2 => -- Unaligned transfer byte(1-2)
s_locDataIn(15 downto 0) <= s_VMEdataInput(23 downto 8);
s_sel <= "00000011";
when others =>
s_locDataIn(31 downto 0) <= s_VMEdataInput(31 downto 0);
s_locDataIn(63 downto 32) <= s_VMEaddrInput(31 downto 1) & s_LWORDinput;
s_sel <= "11111111";
end case;
end case;
end if;
end process;
P_dout_byte_swap : process(clk_i)-- s_locDataOut, s_typeOfDataTransfer, s_DSlatched, s_transferType)
begin
if rising_edge(clk_i) then
-- s_locData <= s_locDataOut;
case s_typeOfDataTransfer is
when D08 =>
case s_DSlatched(1) is
when '0' => -- D08(E)
s_locData(15 downto 8) <= s_locDataOut(7 downto 0);
s_locData(63 downto 16) <= (others => '0');
s_locData(7 downto 0) <= (others => '0');
when others => -- D08(O)
s_locData(7 downto 0) <= s_locDataOut(7 downto 0);
s_locData(63 downto 8) <= (others => '0');
end case;
when D16 => -- D16
s_locData(15 downto 0) <= s_locDataOut(15 downto 0);
s_locData(63 downto 16) <= (others => '0');
when D32 =>
case s_transferType is
when MBLT => -- D64
s_locData(63 downto 0) <= s_locDataOut(63 downto 0);
when others => -- D32
s_locData(31 downto 0) <= s_locDataOut(31 downto 0);
s_locData(63 downto 32) <= (others => '0');
end case;
when UnAl0to2 => -- Unaligned transfer byte(0-2)
s_locData(31 downto 8) <= s_locDataOut(23 downto 0);
s_locData(63 downto 32) <= (others => '0');
s_locData(7 downto 0) <= (others => '0');
when UnAl1to3 => -- Unaligned transfer byte(1-3)
s_locData(23 downto 0) <= s_locDataOut(23 downto 0);
s_locData(63 downto 24) <= (others => '0');
when UnAl1to2 => -- Unaligned transfer byte(1-2)
s_locData(23 downto 8) <= s_locDataOut(15 downto 0);
s_locData(63 downto 24) <= (others => '0');
s_locData(7 downto 0) <= (others => '0');
when others =>
s_locData(63 downto 0) <= s_locDataOut(63 downto 0);
end case;
end if;
end process;
-- FIFOdata_o <= std_logic_vector(s_VMEaddrInput) & s_LWORDinput & std_logic_vector(s_VMEdataInput);
s_locDataOut <= unsigned(WBdata_i) when s_cardSel = '1' else
resize(unsigned(s_CSRdata), s_locDataOut'length) when s_confAccess = '1' and s_CSRaddressed = '1' and s_CRAMaddressed = '0' and s_CRaddressed = '0' else
resize(unsigned(s_CRdataIn), s_locDataOut'length) when s_confAccess = '1' and s_CRaddressed = '1' and s_CRAMaddressed = '0' and s_CSRaddressed = '0' else
resize(unsigned(s_CRAMdataIn), s_locDataOut'length) when s_confAccess = '1' and s_CRAMaddressed = '1' and s_CRaddressed = '0' and s_CSRaddressed = '0' else
(others => '0');
process(clk_i)
begin
if rising_edge(clk_i) then
WBdata_o <= std_logic_vector(s_locDataIn);
RW_o <= s_RW;
memReq_o <= s_memReq and s_cardSel; -- memory request to WB only if it is selected with s_cardSel
wbSel_o <= s_sel;
end if;
end process;
CRAMdata_o <= std_logic_vector(s_locDataIn(7 downto 0));
CRAMwea_o <= '1' when s_confAccess = '1' and s_CRAMaddressed = '1' and s_memReq = '1' and s_RW = '0' else '0';
s_RW <= VME_WRITE_n_oversampled; --and s_WrRd; -- read if s_RW='1', write if s_RW='0'
s_memAck <= s_memAckCSR(0) or memAckWB_i;
-- Access decode (NOTE: since A64 is supported, there are 4 64-bit FUNC_ADERs, because two consecutive 32-bit FUNC_ADERs are needed to decode a 64 bit address)
process(clk_i) --s_moduleEnable, s_funcMatch,s_AMmatch, s_addressingType, s_initInProgress, s_transferType, s_initInProgress )
begin
if rising_edge(clk_i) then
if (s_moduleEnable = '1') and (s_addressingType /= CR_CSR) and (s_initInProgress = '0') then
for I in s_funcMatch'range loop
if s_funcMatch(I) = '1' and s_AMmatch(I) = '1' then
s_cardSel <= '1';
-- else
-- s_cardSel <= '0';
end if;
end loop;
else
s_cardSel <= '0';
end if;
if (s_moduleEnable = '1') and (s_transferType = LCK) and (s_initInProgress = '0') then
for I in s_funcMatch'range loop
if s_funcMatch(I) = '1' then
s_lockSel <= '1';
-- else
-- s_lockSel <= '0';
end if;
end loop;
else
s_lockSel <= '0';
end if;
end if;
end process;
s_confAccess <= '1' when unsigned(s_CSRarray(BAR)(7 downto 3)) = s_locAddr(23 downto 19) and s_addressingType = CR_CSR and s_initInProgress = '0' else '0'; -- CR/CSR decode
s_locAddr_eq_bar <= '1' when unsigned(s_CSRarray(BAR)(7 downto 3)) = s_locAddr(23 downto 19) else '0'; -- added by pablo to check simulation
s_addressingType_CR_CSR <= '1' when s_addressingType = CR_CSR else '0';
p_functMatch : process(clk_i) -- NOTE: interface will respond to different addressing types and will attempt to decode only the address width that it is given, even though the ADEM and ADER registers may contain a mask, that is greater than the current address width
begin
if rising_edge(clk_i) then -- Added by pablo. Guess it should be clocked as the only signal in the
-- sensitivity list was clk
case s_addrWidth is
when "11" =>
for i in s_funcMatch'range loop
if s_addressingType = TWOedge and (s_XAMtype = A32_2eVME or s_XAMtype = A32_2eSST) then
if s_FUNC_ADEM(i)(31 downto 10) /=0 then
if (s_FUNC_ADER(i)(31 downto 10) and s_FUNC_ADEM(i)(31 downto 10)) = ((s_locAddr(31 downto 10)) and s_FUNC_ADEM(i)(31 downto 10)) then
s_funcMatch(i) <= '1';
else
s_funcMatch(i) <= '0';
end if;
else
s_funcMatch(i) <= '0';
end if;
elsif s_addressingType = TWOedge and (s_XAMtype = A64_2eVME or s_XAMtype = A64_2eSST) then
if s_FUNC_ADEM(i)(31 downto 10) /=0 then
if (s_FUNC_ADER_64(i)(63 downto 10) and s_FUNC_ADEM_64(i)(63 downto 10)) = ((s_locAddr(63 downto 10)) and s_FUNC_ADEM_64(i)(63 downto 10)) then
s_funcMatch(i) <= '1';
else
s_funcMatch(i) <= '0';
end if;
else
s_funcMatch(i) <= '0';
end if;
else
if s_FUNC_ADEM(i)(31 downto 10) /=0 then
if (s_FUNC_ADER_64(i)(63 downto 8) and s_FUNC_ADEM_64(i)(63 downto 8)) = ((s_locAddr(63 downto 8)) and s_FUNC_ADEM_64(i)(63 downto 8)) then
s_funcMatch(i) <= '1';
else
s_funcMatch(i) <= '0';
end if;
else
s_funcMatch(i) <= '0';
end if;
end if;
end loop;
when "10" =>
for i in s_funcMatch'range loop
if s_FUNC_ADEM(i)(31 downto 8) /=0 then
if (s_FUNC_ADER(i)(31 downto 8) and s_FUNC_ADEM(i)(31 downto 8)) = ((s_locAddr(31 downto 8)) and s_FUNC_ADEM(i)(31 downto 8)) then
s_funcMatch(i) <= '1';
else
s_funcMatch(i) <= '0';
end if;
else
s_funcMatch(i) <= '0';
end if;
end loop;
when "01" =>
for i in s_funcMatch'range loop
if s_FUNC_ADEM(i)(23 downto 8) /=0 then
if (s_FUNC_ADER(i)(23 downto 8) and s_FUNC_ADEM(i)(23 downto 8)) = ((s_locAddr(23 downto 8)) and s_FUNC_ADEM(i)(23 downto 8)) then
s_funcMatch(i) <= '1';
else
s_funcMatch(i) <= '0';
end if;
else
s_funcMatch(i) <= '0';
end if;
end loop;
when "00" =>
for i in s_funcMatch'range loop
if s_FUNC_ADEM(i)(15 downto 8) /=0 then
if (s_FUNC_ADER(i)(15 downto 8) and s_FUNC_ADEM(i)(15 downto 8)) = ((s_locAddr(15 downto 8)) and s_FUNC_ADEM(i)(15 downto 8)) then
s_funcMatch(i) <= '1';
else
s_funcMatch(i) <= '0';
end if;
else
s_funcMatch(i) <= '0';
end if;
end loop;
when others =>
for i in s_funcMatch'range loop
s_funcMatch(i) <= '0';
end loop;
end case;
end if;
end process;
------------------------------------------------------
process(s_FUNC_AMCAP, VME_AM_oversampled)
begin
s_amcap_match <= (others => '0');
for i in 0 to 7 loop
s_amcap_match(i) <= s_FUNC_AMCAP(i)(to_integer(unsigned(VME_AM_oversampled)));
end loop;
end process;
------------------------------------------------------
process(s_FUNC_XAMCAP, s_XAM)
begin
s_xamcap_match <= (others => '0');
for i in 0 to 3 loop
s_xamcap_match(i) <= s_FUNC_XAMCAP(i)(to_integer(s_XAM));
end loop;
end process;
------------------------------------------------------
p_AMmatch : process(clk_i)
begin
if rising_edge(clk_i) then -- Added by pablo. Guess it should be clocked as the only signal in the
-- -- sensitivity list was clk_i
for i in s_AMmatch'range loop
if s_FUNC_ADEM(i)(DFS) = '1' then
if s_FUNC_ADER(i)(XAM_MODE) = '0' then
if unsigned(s_FUNC_ADER(i)(7 downto 2)) = unsigned(VME_AM_oversampled) then
s_AMmatch(i) <= '1';
else
s_AMmatch(i) <= '0';
end if;
else
if (s_addressingType = TWOedge) and ((s_XAM) = s_FUNC_ADER(i)(9 downto 2)) then
s_AMmatch(i) <= '1';
else
s_AMmatch(i) <= '0';
end if;
end if;
elsif s_addressingType = TWOedge and (s_FUNC_AMCAP(i)(to_integer(unsigned(VME_AM_oversampled))) = '1') then
s_AMmatch(i) <= '1'; --s_xamcap_match(i);
else
s_AMmatch(i) <= s_amcap_match(i);
end if;
end loop;
end if;
end process;
-- CR/CSR addressing (NOTE: only D08 access is supported)
s_CrCsrOffsetAddr <= s_locAddr(18 downto 0);
s_CRaddr <= (s_CrCsrOffsetAddr) when s_initInProgress = '0' else
(resize(s_initReadCounter, CRaddr_o'length)); -- when s_initInProgress='1' the initialization procedure will hijack this address bus
CRaddr_o <= std_logic_vector(s_CRaddr);
CRAMaddr_o <= std_logic_vector(s_CrCsrOffsetAddr - unsigned(s_BEG_CRAM(18 downto 0)));
s_CSRaddressed <= '1' when (s_CrCsrOffsetAddr <= x"7FFFF" and s_CrCsrOffsetAddr >= x"7FC00") xor (s_CrCsrOffsetAddr >= s_BEG_USER_CSR(18 downto 0) and s_CrCsrOffsetAddr <= s_END_USER_CSR(18 downto 0) and s_BEG_USER_CSR < s_END_USER_CSR) else '0';
s_CRaddressed <= '1' when (s_CrCsrOffsetAddr <= x"00FFF" and s_CrCsrOffsetAddr >= x"00000") xor (s_CrCsrOffsetAddr >= s_BEG_USER_CR(18 downto 0) and s_CrCsrOffsetAddr <= s_END_USER_CR(18 downto 0) and s_BEG_USER_CR < s_END_USER_CR) else '0';
s_CRAMaddressed <= '1' when (s_CrCsrOffsetAddr >= s_BEG_CRAM(18 downto 0) and s_CrCsrOffsetAddr <= s_END_CRAM(18 downto 0) and s_BEG_CRAM < s_END_CRAM) else '0';
-- CR/CSR memory acknowledge
p_memAckCSR : process(clk_i)
begin
if rising_edge(clk_i) then
if s_reset = '1' then
s_memAckCSR <= (others => '0');
else
if s_memReq = '1' and s_confAccess = '1' then
s_memAckCSR <= s_memAckCSR (1 downto 0) & '1';
else
s_memAckCSR <= (others => '0');
end if;
end if;
end if;
end process;
-- Control & Status Registers (NOTE: only D08 access is supported)
s_GAparityMatch <= '1' when VME_GA_oversampled(5) = not (VME_GA_oversampled(0) xor VME_GA_oversampled(1) xor VME_GA_oversampled(2) xor VME_GA_oversampled(3) xor VME_GA_oversampled(4)) else '0';
s_moduleEnable <= '1'; -- set by pablo for testing it was: s_CSRarray(BIT_SET_CLR_REG)(4);
-- CSR write
p_CSR_Write : process(clk_i)
begin
if rising_edge(clk_i) then
if s_reset = '1' then
if s_GAparityMatch = '1' then
s_CSRarray(BAR) <= (resize(unsigned(not VME_GA_oversampled(4 downto 0))*8, s_CSRarray(BAR)'length));
else
s_CSRarray(BAR) <= (others => '0');
end if;
s_bar_written <= '0';
elsif s_memReq = '1' and s_confAccess = '1' then
if s_CrCsrOffsetAddr = BAR and s_RW = '0' then
s_CSRarray(BAR) <= s_locDataIn(7 downto 0);
s_bar_written <= '1';
end if;
elsif s_bar_written = '0' then
s_CSRarray(BAR)(7 downto 3) <= unsigned(not VME_GA_oversampled(4 downto 0));
s_CSRarray(BAR)(2 downto 0) <= "000";
end if;
if s_reset = '1' then
s_BitSetReg <= (others => '0');
s_BitClrReg <= (others => '0');
s_UsrBitClrReg <= (others => '0');
s_UsrBitSetReg <= (others => '0');
s_CSRarray(CRAM_OWNER) <= (others => '0');
-- s_CSRarray(BAR) <= (others => '0');
for i in CRAM_OWNER downto IRQ_level loop
s_CSRarray(i) <= c_csr_array(i);
end loop;
elsif s_memReq = '1' and s_confAccess = '1' then
case to_integer(s_CrCsrOffsetAddr) is
-- Base Address Register
when BAR_addr =>
-- Bit Set Register
when BIT_SET_REG_addr =>
for i in 0 to 7 loop
if s_BitSetReg(i) = '1' then
s_CSRarray(BIT_SET_CLR_REG)(i) <= '1';
end if;
end loop;
if s_RW = '0' then
s_BitSetReg <= s_locDataIn(7 downto 0);
end if;
-- Bit Clear Register
when BIT_CLR_REG_addr =>
for i in 0 to 7 loop
if s_BitClrReg(i) = '1' then
s_CSRarray(BIT_SET_CLR_REG)(i) <= '0';
end if;
end loop;
if s_CSRarray(BIT_SET_CLR_REG)(2) = '0' then
s_CSRarray(CRAM_OWNER) <= x"00";
end if;
if s_RW = '0' then
s_BitClrReg <= s_locDataIn(7 downto 0);
end if;
-- CRAM Owner register
when CRAM_OWNER_addr =>
if s_RW = '0' and s_CSRarray(CRAM_OWNER) = x"00" then
s_CSRarray(CRAM_OWNER) <= s_locDataIn(7 downto 0); -- Write register (give ownership) only if register value is 0
end if;
-- User-Defined Bit Set Register
when USR_BIT_SET_REG_addr =>
for i in 0 to 7 loop
if s_UsrBitSetReg(i) = '1' then
s_CSRarray(USR_BIT_SET_CLR_REG)(i) <= '1';
end if;
end loop;
if s_RW = '0' then
s_UsrBitSetReg <= s_locDataIn(7 downto 0);
end if;
-- User-Defined Bit Clear Register
when USR_BIT_CLR_REG_addr =>
for i in 0 to 7 loop
if s_UsrBitClrReg(i) = '1' then
s_CSRarray(USR_BIT_SET_CLR_REG)(i) <= '0';
end if;
end loop;
if s_RW = '0' then
s_UsrBitClrReg <= s_locDataIn(7 downto 0);
end if;
-- Function ADER registers
when FUNC0_ADER_3_addr to FUNC7_ADER_0_addr =>
if s_RW = '0' then
s_CSRarray(to_integer(s_CrCsrOffsetAderIndex)) <= s_locDataIn(7 downto 0);
end if;
when IRQ_ID_addr =>
if s_RW = '0' then
s_CSRarray(IRQ_ID) <= s_locDataIn(7 downto 0);
end if;
when IRQ_level_addr =>
if s_RW = '0' then
s_CSRarray(IRQ_level) <= s_locDataIn(7 downto 0);
end if;
when others =>
end case;
else
if s_transferActive = '1' and s_BERRcondition = '1' then
s_CSRarray(BIT_SET_CLR_REG)(3) <= '1'; -- BERR flag
end if;
if s_CSRarray(CRAM_OWNER) = x"00" then -- CRAM OWNER flag
s_CSRarray(BIT_SET_CLR_REG)(2) <= '0';
else
s_CSRarray(BIT_SET_CLR_REG)(2) <= '1';
end if;
end if;
end if;
end process;
s_CrCsrOffsetAderIndex_aux <= s_CrCsrOffsetAddr - FUNC0_ADER_3_addr;
s_CrCsrOffsetAderIndex <= unsigned(s_CrCsrOffsetAderIndex_aux(s_CrCsrOffsetAderIndex'left + 2 downto 2))+ FUNC0_ADER_3;
-- CSR read
process(s_CSRarray, s_CrCsrOffsetAddr)
begin
s_CSRdata <= (others => '0');
case to_integer(s_CrCsrOffsetAddr) is
when BAR_addr => s_CSRdata <= s_CSRarray(BAR);
when BIT_SET_REG_addr => s_CSRdata <= s_CSRarray(BIT_SET_CLR_REG);
when BIT_CLR_REG_addr => s_CSRdata <= s_CSRarray(BIT_SET_CLR_REG);
when CRAM_OWNER_addr => s_CSRdata <= s_CSRarray(CRAM_OWNER);
when USR_BIT_SET_REG_addr => s_CSRdata <= s_CSRarray(USR_BIT_SET_CLR_REG);
when USR_BIT_CLR_REG_addr => s_CSRdata <= s_CSRarray(USR_BIT_SET_CLR_REG);
when FUNC7_ADER_0_addr => s_CSRdata <= s_CSRarray(FUNC7_ADER_0);
when FUNC7_ADER_1_addr => s_CSRdata <= s_CSRarray(FUNC7_ADER_1);
when FUNC7_ADER_2_addr => s_CSRdata <= s_CSRarray(FUNC7_ADER_2);
when FUNC7_ADER_3_addr => s_CSRdata <= s_CSRarray(FUNC7_ADER_3);
when FUNC6_ADER_0_addr => s_CSRdata <= s_CSRarray(FUNC6_ADER_0);
when FUNC6_ADER_1_addr => s_CSRdata <= s_CSRarray(FUNC6_ADER_1);
when FUNC6_ADER_2_addr => s_CSRdata <= s_CSRarray(FUNC6_ADER_2);
when FUNC6_ADER_3_addr => s_CSRdata <= s_CSRarray(FUNC6_ADER_3);
when FUNC5_ADER_0_addr => s_CSRdata <= s_CSRarray(FUNC5_ADER_0);
when FUNC5_ADER_1_addr => s_CSRdata <= s_CSRarray(FUNC5_ADER_1);
when FUNC5_ADER_2_addr => s_CSRdata <= s_CSRarray(FUNC5_ADER_2);
when FUNC5_ADER_3_addr => s_CSRdata <= s_CSRarray(FUNC5_ADER_3);
when FUNC4_ADER_0_addr => s_CSRdata <= s_CSRarray(FUNC4_ADER_0);
when FUNC4_ADER_1_addr => s_CSRdata <= s_CSRarray(FUNC4_ADER_1);
when FUNC4_ADER_2_addr => s_CSRdata <= s_CSRarray(FUNC4_ADER_2);
when FUNC4_ADER_3_addr => s_CSRdata <= s_CSRarray(FUNC4_ADER_3);
when FUNC3_ADER_0_addr => s_CSRdata <= s_CSRarray(FUNC3_ADER_0);
when FUNC3_ADER_1_addr => s_CSRdata <= s_CSRarray(FUNC3_ADER_1);
when FUNC3_ADER_2_addr => s_CSRdata <= s_CSRarray(FUNC3_ADER_2);
when FUNC3_ADER_3_addr => s_CSRdata <= s_CSRarray(FUNC3_ADER_3);
when FUNC2_ADER_0_addr => s_CSRdata <= s_CSRarray(FUNC2_ADER_0);
when FUNC2_ADER_1_addr => s_CSRdata <= s_CSRarray(FUNC2_ADER_1);
when FUNC2_ADER_2_addr => s_CSRdata <= s_CSRarray(FUNC2_ADER_2);
when FUNC2_ADER_3_addr => s_CSRdata <= s_CSRarray(FUNC2_ADER_3);
when FUNC1_ADER_0_addr => s_CSRdata <= s_CSRarray(FUNC1_ADER_0);
when FUNC1_ADER_1_addr => s_CSRdata <= s_CSRarray(FUNC1_ADER_1);
when FUNC1_ADER_2_addr => s_CSRdata <= s_CSRarray(FUNC1_ADER_2);
when FUNC1_ADER_3_addr => s_CSRdata <= s_CSRarray(FUNC1_ADER_3);
when FUNC0_ADER_0_addr => s_CSRdata <= s_CSRarray(FUNC0_ADER_0);
when FUNC0_ADER_1_addr => s_CSRdata <= s_CSRarray(FUNC0_ADER_1);
when FUNC0_ADER_2_addr => s_CSRdata <= s_CSRarray(FUNC0_ADER_2);
when FUNC0_ADER_3_addr => s_CSRdata <= s_CSRarray(FUNC0_ADER_3);
when IRQ_ID_addr => s_CSRdata <= s_CSRarray(IRQ_ID);
when IRQ_level_addr => s_CSRdata <= s_CSRarray(IRQ_level);
when others =>
end case;
-----------------------------------------------
-----------------------------------------------
-----------------------------------------------
end process;
IRQlevelReg_o <= std_logic_vector(s_CSRarray(IRQ_level));
-- Initialization procedure
p_coreInit : process(clk_i) -- Read important CR data (like FUNC_ADEMs etc.) and store it locally
begin
if rising_edge(clk_i) then
if s_reset = '1' then
s_initState <= IDLE;
s_initReadCounter <= to_unsigned(0, s_initReadCounter'length);
s_latchCRdata <= '0';
for i in 0 to 51 loop
s_CRregArray(i) <= (others => '0');
end loop;
else
case s_initState is
when IDLE =>
s_initReadCounter <= to_unsigned(0, s_initReadCounter'length);
s_latchCRdata <= '0';
s_initState <= SET_ADDR;
when SET_ADDR =>
s_initReadCounter <= s_initReadCounter+1;
s_latchCRdata <= '0';
s_initState <= GET_DATA;
when GET_DATA =>
s_initReadCounter <= s_initReadCounter;
s_latchCRdata <= '1';
if s_initInProgress = '1' then
s_initState <= SET_ADDR;
else
s_initState <= END_INIT;
end if;
when END_INIT => -- will wait in this state until reset
s_initReadCounter <= s_initReadCounter;
s_latchCRdata <= '0';
s_initState <= END_INIT;
when others =>
s_initState <= IDLE;
s_initReadCounter <= to_unsigned(0, s_initReadCounter'length);
s_latchCRdata <= '0';
end case;
-- if s_latchCRdata='1' then
-- s_CRregArray(s_initReadCounter) <= unsigned(CRdata_i);
-- end if;
end if;
end if;
end process;
s_initInProgress <= '1' when (s_initReadCounter <= (428)) else '0';
s_CRadd_offset <= s_CRaddr - s_CRaddr_base;
process(s_latchCRdata, s_initReadCounter)
begin
s_latchCRdataPos <= (others => '0');
s_CRaddr_base <= (others => '0');
for I in c_CRinitAddr'range loop
if (s_initReadCounter >= c_CRinitAddr(I).add) and (s_initReadCounter <= (c_CRinitAddr(I).add+(c_CRinitAddr(I).len-1))) then
s_CRaddr_base <= to_unsigned(c_CRinitAddr(I).add, s_CRaddr_base'length);
s_latchCRdataPos(I) <= s_latchCRdata;
exit;
end if;
end loop;
end process;
process(clk_i)
begin
if rising_edge(clk_i) then
for I in 0 to 2 loop
if (s_latchCRdataPos(BEG_USER_CR) = '1') and (unsigned(s_CRadd_offset(1 downto 0)) = I) then
s_BEG_USER_CR(((3-i)*8 - 1) downto (2-i)*8) <= unsigned(CRdata_i);
end if;
if s_latchCRdataPos(END_USER_CR) = '1' and (unsigned(s_CRadd_offset(1 downto 0)) = I) then
s_END_USER_CR(((3-i)*8 - 1) downto (2-i)*8) <= unsigned(CRdata_i);
end if;
if (s_latchCRdataPos(BEG_USER_CSR) = '1') and (unsigned(s_CRadd_offset(1 downto 0)) = I) then
s_BEG_USER_CSR(((3-i)*8 - 1) downto (2-i)*8) <= unsigned(CRdata_i);
end if;
if (s_latchCRdataPos(END_USER_CSR) = '1') and (unsigned(s_CRadd_offset(1 downto 0)) = I) then
s_END_USER_CSR(((3-i)*8 - 1) downto (2-i)*8) <= unsigned(CRdata_i);
end if;
if (s_latchCRdataPos(BEG_CRAM) = '1') and (unsigned(s_CRadd_offset(1 downto 0)) = I) then
s_BEG_CRAM(((3-i)*8 - 1) downto (2-i)*8) <= unsigned(CRdata_i);
end if;
if (s_latchCRdataPos(END_CRAM) = '1') and (unsigned(s_CRadd_offset(1 downto 0)) = I) then
s_END_CRAM(((3-i)*8 - 1) downto (2-i)*8) <= unsigned(CRdata_i);
end if;
end loop;
for I in 0 to 7 loop
if (s_latchCRdataPos(FUNC_AMCAP) = '1') and (unsigned(s_CRadd_offset(5 downto 3)) = I) then
for H in 0 to 7 loop
if (unsigned(s_CRadd_offset(2 downto 0)) = H) then
s_FUNC_AMCAP(I)(((8-h)*8 - 1) downto (7-h)*8) <= unsigned(CRdata_i);
end if;
end loop;
end if;
if (s_latchCRdataPos(FUNC_ADEM) = '1') and (unsigned(s_CRadd_offset(4 downto 2)) = I) then
for H in 0 to 3 loop
if (unsigned(s_CRadd_offset(1 downto 0)) = H) then
s_FUNC_ADEM(I)(((4-h)*8 - 1) downto (3-h)*8) <= unsigned(CRdata_i);
end if;
end loop;
end if;
if (s_latchCRdataPos(FUNC_XAMCAP) = '1') and (unsigned(s_CRadd_offset(7 downto 5)) = I) then
for H in 0 to 31 loop
if (unsigned(s_CRadd_offset(4 downto 0)) = H) then
s_FUNC_XAMCAP(I)(((32-h)*8 - 1) downto (31-h)*8) <= unsigned(CRdata_i);
end if;
end loop;
end if;
end loop;
end if;
end process;
GADER_1 : for i in 0 to 7 generate
GADER_2 : for h in 0 to 3 generate
s_FUNC_ADER(i)(8*(4-h)-1 downto 8*(3-h)) <= s_CSRarray(FUNC0_ADER_3+(h+i*4));
end generate GADER_2;
end generate GADER_1;
GAD_64 : for i in 0 to 6 generate
s_FUNC_ADER_64(i) <= s_FUNC_ADER(i+1)&s_FUNC_ADER(i);
s_FUNC_ADEM_64(I) <= s_FUNC_ADEM(i+1)&s_FUNC_ADEM(i);
end generate GAD_64;
s_FUNC_ADER_64(7) <= (others => '0');
s_FUNC_ADEM_64(7) <= (others => '0');
------------------------------------------------------
-- Input oversampling & edge detection
process(clk_i)
begin
if rising_edge(clk_i) then
s_DS1pulse_d <= s_DS1pulse;
end if;
end process;
ASfallingEdge : FallingEdgeDetection
port map (
sig_i => VME_AS_n_oversampled,
clk_i => clk_i,
FallEdge_o => s_VMEaddrLatch
);
ASrisingEdge : RisEdgeDetection
port map (
sig_i => VME_AS_n_oversampled,
clk_i => clk_i,
RisEdge_o => s_mainFSMreset
);
DS1EdgeDetect : EdgeDetection
port map (
sig_i => VME_DS_n_oversampled_1(1),
clk_i => clk_i,
sigEdge_o => s_DS1pulse
);
AMinputSample : RegInputSample
generic map(
width => 6
)
port map(
reg_i => VME_AM_i,
reg_o => VME_AM_oversampled,
clk_i => clk_i
);
DATAinputSample : RegInputSample
generic map(
width => 32
)
port map (
reg_i => VME_DATA_b_i,
reg_o => VME_DATA_oversampled,
clk_i => clk_i
);
ADDRinputSample : RegInputSample
generic map(
width => 31
)
port map(
reg_i => VME_ADDR_b_i,
reg_o => VME_ADDR_oversampled,
clk_i => clk_i
);
GAinputSample : RegInputSample
generic map(
width => 6
)
port map(
reg_i => VME_GA_i,
reg_o => VME_GA_oversampled,
clk_i => clk_i
);
DSinputSample : DoubleRegInputSample
generic map(
width => 2
)
port map(
reg_i => VME_DS_n_i,
reg_o => VME_DS_n_oversampled_1,
clk_i => clk_i
);
p_DSsync : process(clk_i)
begin
if rising_edge(clk_i) then
VME_DS_n_oversampled <= VME_DS_n_oversampled_1;
end if;
end process;
CRinputSample : RegInputSample
generic map(
width => 8
)
port map(
reg_i => CRdata_i,
reg_o => s_CRdataIn,
clk_i => clk_i
);
CRAMinputSample : RegInputSample
generic map(
width => 8
)
port map(
reg_i => CRAMdata_i,
reg_o => s_CRAMdataIn,
clk_i => clk_i
);
WRITEinputSample : SigInputSample
port map(
sig_i => VME_WRITE_n_i,
sig_o => VME_WRITE_n_oversampled,
clk_i => clk_i
);
LWORDinputSample : SigInputSample
port map(
sig_i => VME_LWORD_n_b_i,
sig_o => VME_LWORD_n_oversampled,
clk_i => clk_i
);
ASinputSample : DoubleSigInputSample
port map(
sig_i => VME_AS_n_i,
sig_o => VME_AS_n_oversampled,
clk_i => clk_i
);
RSTinputSample : SigInputSample
port map(
sig_i => VME_RST_n_i,
sig_o => VME_RST_n_oversampled,
clk_i => clk_i
);
BBSYinputSample : SigInputSample
port map(
sig_i => VME_BBSY_n_i,
sig_o => VME_BBSY_n_oversampled,
clk_i => clk_i
);
IACKINinputSample : SigInputSample
port map(
sig_i => VME_IACKIN_n_i,
sig_o => VME_IACKIN_n_oversampled,
clk_i => clk_i
);
end RTL;
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.numeric_std.all;
package VME_pack is
type t_reg52x8bit is array(51 downto 0) of unsigned(7 downto 0);
type t_reg52x12bit is array(51 downto 0) of unsigned(11 downto 0);
type t_cr_array is array (Natural range <>) of std_logic_vector(7 downto 0);
type t_rom_cell is
record
add : integer;
len : integer;
end record;
type t_cr_add_table is array (Natural range <>) of t_rom_cell;
constant c_A24 : std_logic_vector(5 downto 0) :="111001";
constant c_A24_S : std_logic_vector(5 downto 0) :="111101";
constant c_A24_BLT : std_logic_vector(5 downto 0) :="111111";
constant c_A24_MBLT : std_logic_vector(5 downto 0) :="111100";
constant c_A24_LCK : std_logic_vector(5 downto 0) :="110010";
constant c_CR_CSR : std_logic_vector(5 downto 0) :="101111";
constant c_A16 : std_logic_vector(5 downto 0) :="101101";
constant c_A16_LCK : std_logic_vector(5 downto 0) :="101100";
constant c_A32 : std_logic_vector(5 downto 0) :="001001";
constant c_A32_BLT : std_logic_vector(5 downto 0) :="001111";
constant c_A32_MBLT : std_logic_vector(5 downto 0) :="001100";
constant c_A32_LCK : std_logic_vector(5 downto 0) :="000101";
constant c_A64 : std_logic_vector(5 downto 0) :="000001";
constant c_A64_BLT : std_logic_vector(5 downto 0) :="000011";
constant c_A64_MBLT : std_logic_vector(5 downto 0) :="000000";
constant c_A64_LCK : std_logic_vector(5 downto 0) :="000100";
constant c_TWOedge : std_logic_vector(5 downto 0) :="100000";
constant c_cr_step : integer := 4;
constant BAR : integer := 255;
constant BIT_SET_CLR_REG : integer := 254;
constant USR_BIT_SET_CLR_REG : integer := 253;
constant CRAM_OWNER : integer := 252;
constant FUNC7_ADER_0 : integer := 251;
constant FUNC7_ADER_1 : integer := FUNC7_ADER_0 - 1;
constant FUNC7_ADER_2 : integer := FUNC7_ADER_0 - 2;
constant FUNC7_ADER_3 : integer := FUNC7_ADER_0 - 3;
constant FUNC6_ADER_0 : integer := FUNC7_ADER_0 - 4;
constant FUNC6_ADER_1 : integer := FUNC7_ADER_0 - 5;
constant FUNC6_ADER_2 : integer := FUNC7_ADER_0 - 6;
constant FUNC6_ADER_3 : integer := FUNC7_ADER_0 - 7;
constant FUNC5_ADER_0 : integer := FUNC7_ADER_0 - 8;
constant FUNC5_ADER_1 : integer := FUNC7_ADER_0 - 9;
constant FUNC5_ADER_2 : integer := FUNC7_ADER_0 - 10;
constant FUNC5_ADER_3 : integer := FUNC7_ADER_0 - 11;
constant FUNC4_ADER_0 : integer := FUNC7_ADER_0 - 12;
constant FUNC4_ADER_1 : integer := FUNC7_ADER_0 - 13;
constant FUNC4_ADER_2 : integer := FUNC7_ADER_0 - 14;
constant FUNC4_ADER_3 : integer := FUNC7_ADER_0 - 15;
constant FUNC3_ADER_0 : integer := FUNC7_ADER_0 - 16;
constant FUNC3_ADER_1 : integer := FUNC7_ADER_0 - 17;
constant FUNC3_ADER_2 : integer := FUNC7_ADER_0 - 18;
constant FUNC3_ADER_3 : integer := FUNC7_ADER_0 - 19;
constant FUNC2_ADER_0 : integer := FUNC7_ADER_0 - 20;
constant FUNC2_ADER_1 : integer := FUNC7_ADER_0 - 21;
constant FUNC2_ADER_2 : integer := FUNC7_ADER_0 - 22;
constant FUNC2_ADER_3 : integer := FUNC7_ADER_0 - 23;
constant FUNC1_ADER_0 : integer := FUNC7_ADER_0 - 24;
constant FUNC1_ADER_1 : integer := FUNC7_ADER_0 - 25;
constant FUNC1_ADER_2 : integer := FUNC7_ADER_0 - 26;
constant FUNC1_ADER_3 : integer := FUNC7_ADER_0 - 27;
constant FUNC0_ADER_0 : integer := FUNC7_ADER_0 - 28;
constant FUNC0_ADER_1 : integer := FUNC7_ADER_0 - 29;
constant FUNC0_ADER_2 : integer := FUNC7_ADER_0 - 30;
constant FUNC0_ADER_3 : integer := FUNC7_ADER_0 - 31;
constant IRQ_ID : integer := FUNC0_ADER_3 -1;
constant IRQ_level : integer := FUNC0_ADER_3 -2;
type t_CSRarray is array(BAR downto IRQ_level) of unsigned(7 downto 0);
----------------------------------
--Bit accronyms
constant DFS : integer := 2;
constant XAM_MODE : integer := 0;
--0x7FFFF CR/CSR (BAR) 1 byte VME64
-- Base Address Register
--0x7FFFB Bit Set Register 1 byte VME64
-- see Table 10-6
--0x7FFF7 Bit Clear Register 1 byte VME64
-- see Table 10-7
--0x7FFF3 CRAM_OWNER Register 1 byte VME64x
--0x7FFEF User-Defined Bit Set 1 byte VME64x
-- Register
--0x7FFEB User-Defined Bit Clear 1 byte VME64x
-- Register
--0x7FFE3 ... 0x7FFE7 RESERVED 2 bytes VME64x
--0x7FFD3 ... 0x7FFDF Function 7 ADER 4 bytes VME64x
-- see Table 10-8
--0x7FFC3 ... 0x7FFCF Function 6 ADER 4 bytes VME64x
--0x7FFB3 ... 0x7FFBF Function 5 ADER 4 bytes VME64x
--0x7FFA3 ... 0x7FFAF Function 4 ADER 4 bytes VME64x
--0x7FF93 ... 0x7FF9F Function 3 ADER 4 bytes VME64x
--0x7FF83 ... 0x7FF8F Function 2 ADER 4 bytes VME64x
--0x7FF73 ... 0x7FF7F Function 1 ADER 4 bytes VME64x
--0x7FF63 ... 0x7FF6F Function 0 ADER 4 bytes VME64x
--0x7FC00 ... 0x7FF5F RESERVED 216 bytes VME64x
--
-------------------
constant BAR_addr : integer := 16#7FFFF#;
constant BIT_SET_REG_addr : integer := 16#7FFFB#;
constant BIT_CLR_REG_addr : integer := 16#7FFF7#;
constant CRAM_OWNER_addr : integer := 16#7FFF3#;
constant USR_BIT_SET_REG_addr : integer := 16#7FFEF#;
constant USR_BIT_CLR_REG_addr : integer := 16#7FFEB#;
--Reserved 16#7FFE7#;
--Reserved 16#7FFE3#;
constant FUNC7_ADER_0_addr : integer := 16#7FFDF#;
constant FUNC7_ADER_1_addr : integer := 16#7FFDB#;
constant FUNC7_ADER_2_addr : integer := 16#7FFD7#;
constant FUNC7_ADER_3_addr : integer := 16#7FFD3#;
constant FUNC6_ADER_0_addr : integer := 16#7FFCF#;
constant FUNC6_ADER_1_addr : integer := 16#7FFCB#;
constant FUNC6_ADER_2_addr : integer := 16#7FFC7#;
constant FUNC6_ADER_3_addr : integer := 16#7FFC3#;
constant FUNC5_ADER_0_addr : integer := 16#7FFBF#;
constant FUNC5_ADER_1_addr : integer := 16#7FFBB#;
constant FUNC5_ADER_2_addr : integer := 16#7FFB7#;
constant FUNC5_ADER_3_addr : integer := 16#7FFB3#;
constant FUNC4_ADER_0_addr : integer := 16#7FFAF#;
constant FUNC4_ADER_1_addr : integer := 16#7FFAB#;
constant FUNC4_ADER_2_addr : integer := 16#7FFA7#;
constant FUNC4_ADER_3_addr : integer := 16#7FFA3#;
constant FUNC3_ADER_0_addr : integer := 16#7FF9F#;
constant FUNC3_ADER_1_addr : integer := 16#7FF9B#;
constant FUNC3_ADER_2_addr : integer := 16#7FF97#;
constant FUNC3_ADER_3_addr : integer := 16#7FF93#;
constant FUNC2_ADER_0_addr : integer := 16#7FF8F#;
constant FUNC2_ADER_1_addr : integer := 16#7FF8B#;
constant FUNC2_ADER_2_addr : integer := 16#7FF87#;
constant FUNC2_ADER_3_addr : integer := 16#7FF83#;
constant FUNC1_ADER_0_addr : integer := 16#7FF7F#;
constant FUNC1_ADER_1_addr : integer := 16#7FF7B#;
constant FUNC1_ADER_2_addr : integer := 16#7FF77#;
constant FUNC1_ADER_3_addr : integer := 16#7FF73#;
constant FUNC0_ADER_0_addr : integer := 16#7FF6F#;
constant FUNC0_ADER_1_addr : integer := 16#7FF6B#;
constant FUNC0_ADER_2_addr : integer := 16#7FF67#;
constant FUNC0_ADER_3_addr : integer := 16#7FF63#;
constant IRQ_ID_addr : integer := 16#7fbff#;
constant IRQ_level_addr : integer := 16#7fbef#;
----------------------------------
---------------------------------------------------------------------------
constant BEG_USER_CR: integer := 1;
constant END_USER_CR: integer := 2;
constant BEG_CRAM: integer := 3;
constant END_CRAM: integer := 4;
constant BEG_USER_CSR: integer := 5;
constant END_USER_CSR: integer := 6;
constant FUNC_AMCAP : integer := 7;
constant FUNC_XAMCAP : integer := 8;
constant FUNC_ADEM: integer := 9; -- 340
constant c_CRinitAddr: t_cr_add_table(BEG_USER_CR to FUNC_ADEM) := (
BEG_USER_CR => (add => 16#020#, len => 3),
END_USER_CR => (add => 16#023#, len => 3),
BEG_CRAM => (add => 16#26#, len => 3),
END_CRAM => (add => 16#29#, len => 3),
BEG_USER_CSR => (add => 16#02C#, len => 3),
END_USER_CSR => (add => 16#2F#, len => 3),
FUNC_AMCAP => (add => 16#048#, len => 64),
FUNC_XAMCAP => (add => 16#088#, len => 256),
FUNC_ADEM => (add => 16#188#, len => 32));
constant c_checksum_po : integer :=0;
constant c_length_of_rom_po : integer :=1;
constant c_csr_data_acc_width_po : integer :=2;
constant c_cr_space_specification_id_po : integer :=3;
constant c_ascii_c_po : integer :=4;
constant c_ascii_r_po : integer :=5;
constant c_manu_id_po : integer :=6;
constant c_board_id_po : integer :=7;
constant c_rev_id_po : integer :=8;
constant c_cus_ascii_po : integer :=9;
constant c_last_CR_pointer_po : integer := 9;
end VME_pack;
-------------------------------------------------------------------------------
--
-- Title : WB_bus
-- Design : VME64xCore
-- Author : Ziga Kroflic
-- Company : Cosylab
--
-------------------------------------------------------------------------------
--
-- File : WB_bus.vhd
-- Generated : Tue Mar 30 11:59:59 2010
-- From : interface description file
-- By : Itf2Vhdl ver. 1.20
--
-------------------------------------------------------------------------------
--
-- Description :
--
-------------------------------------------------------------------------------
--{{ Section below this comment is automatically maintained
-- and may be overwritten
--{entity {WB_bus} architecture {RTL}}
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_unsigned.all;
entity WB_bus is
port (
clk_i: in std_logic;
reset_i: in std_logic; -- propagated from VME
RST_i: in std_logic;
DAT_i: in std_logic_vector(63 downto 0);
DAT_o: out std_logic_vector(63 downto 0);
ADR_o: out std_logic_vector(63 downto 0);
CYC_o: out std_logic;
ERR_i: in std_logic;
LOCK_o: out std_logic;
RTY_i: in std_logic;
SEL_o: out std_logic_vector(7 downto 0);
STB_o: out std_logic;
ACK_i: in std_logic;
WE_o: out std_logic;
STALL_i: in std_logic;
memReq_i: in std_logic;
memAck_o: out std_logic;
locData_o: out std_logic_vector(63 downto 0);
locData_i: in std_logic_vector(63 downto 0);
locAddr_i: in std_logic_vector(63 downto 0);
sel_i: in std_logic_vector(7 downto 0);
RW_i: in std_logic;
lock_i: in std_logic;
err_o: out std_logic;
rty_o: out std_logic;
cyc_i: in std_logic;
beatCount_i: in std_logic_vector(7 downto 0);
FIFOrden_o: out std_logic;
FIFOwren_o: out std_logic;
FIFOdata_i: in std_logic_vector(63 downto 0);
FIFOdata_o: out std_logic_vector(63 downto 0);
FIFOreset_o: out std_logic;
writeFIFOempty_i: in std_logic;
TWOeInProgress_i: in std_logic;
WBbusy_o: out std_logic
);
end WB_bus;
architecture RTL of WB_bus is
signal s_reset: std_logic;
signal s_locDataOut: std_logic_vector(63 downto 0); -- local data
SIgnal s_locAddr: std_logic_vector(63 downto 0); -- local address
signal s_FSMactive: std_logic; -- signals when SST FIFO is being emptied
signal s_cyc: std_logic; -- CYC signal (for control in 2eFSM)
signal s_stb: std_logic; -- STB signal (for control in p_pipSTB)
signal s_addrLatch: std_logic; -- store initial address locally
signal s_pipeCommActive: std_logic; -- indicates tha 2eFSM is active (transfer is in progress)
signal s_WE: std_logic; -- WE signal (for control in 2eFSM)
signal s_runningBeatCount: std_logic_vector(8 downto 0); -- internal beat counter
signal s_beatCount: std_logic_vector(7 downto 0); -- registered beat count (received from VME core)
signal s_beatCountEnd: std_logic; -- marks that beat counter has reached the final value
signal s_cycleDelay: std_logic; -- used for delaying s_pipeCommActive signal for one clock cycle
signal s_ackCount: std_logic_vector(7 downto 0); -- ACK tick counter
signal s_ackCountEnd: std_logic; -- marks that all expected ACK ticks have been received
signal s_FIFOrden: std_logic; -- FIFO read enable
signal s_FIFOreset, s_FIFOreset_1, s_FIFOreset_2: std_logic; -- Resets FIFO at the end of each transfer
type t_2eFSMstates is ( IDLE,
ADDR_LATCH,
SET_CONTROL_SIGNALS,
DO_PIPELINED_COMM,
WAIT_FOR_END,
FIFO_RESET
);
signal s_2eFSMstate: t_2eFSMstates;
begin
s_reset <= reset_i or RST_i;
-- WB data latching
p_dataLatch: process(clk_i)
begin
if rising_edge(clk_i) then
if ACK_i='1' then
s_locDataOut <= DAT_i;
else
s_locDataOut <= s_locDataOut;
end if;
end if;
end process;
locData_o <= s_locDataOut;
FIFOdata_o <= DAT_i;
--p_ioRegister: process(clk_i)
--begin
-- if rising_edge(clk_i) then
-- if s_FSMactive='0' then
-- DAT_o <= locData_i;
-- ADR_o <= locAddr_i;
-- WE_o <= not RW_i;
-- err_o <= ERR_i;
-- rty_o <= RTY_i;
-- SEL_o <= sel_i;
-- CYC_o <= cyc_i;
-- STB_o <= memReq_i;
-- memAck_o <= ACK_i;
-- else
-- DAT_o <= FIFOdata_i;
-- ADR_o <= s_locAddr;
-- WE_o <= s_WE;
-- err_o <= '0';
-- rty_o <= '0';
-- SEL_o <= (others => '1');
-- CYC_o <= s_cyc;
-- STB_o <= s_stb;
-- memAck_o <= '0';
-- end if;
--
-- LOCK_o <= lock_i;
-- end if;
--end process;
STB_o <= memReq_i when s_FSMactive='0' else s_stb;
memAck_o <= ACK_i when s_FSMactive='0' else '0';
DAT_o <= locData_i when s_FSMactive='0' else FIFOdata_i;
ADR_o <= locAddr_i when s_FSMactive='0' else s_locAddr;
WE_o <= not RW_i when s_FSMactive='0' else s_WE;
LOCK_o <= lock_i;
err_o <= ERR_i when s_FSMactive='0' else '0';
rty_o <= RTY_i when s_FSMactive='0' else '0';
SEL_o <= sel_i when s_FSMactive='0' else (others => '1');
CYC_o <= cyc_i when s_FSMactive='0' else s_cyc;
WBbusy_o <= s_FSMactive;
-- 2e FSM
p_2eFSM: process(clk_i)
begin
if rising_edge(clk_i) then
if s_reset='1' then
s_FSMactive <='0';
s_cyc <='0';
s_pipeCommActive <='0';
s_WE <='0';
s_addrLatch <='0';
s_FIFOreset <='0';
s_2eFSMstate <= IDLE;
else
case s_2eFSMstate is
when IDLE =>
s_FSMactive <='0';
s_cyc <='0';
s_WE <= not RW_i;
s_addrLatch <='0';
s_pipeCommActive <='0';
s_FIFOreset <='0';
if TWOeInProgress_i='1' then
s_2eFSMstate <= ADDR_LATCH;
end if;
when ADDR_LATCH =>
s_FSMactive <='1';
s_cyc <='1';
s_WE <= s_WE;
s_addrLatch <='1';
s_pipeCommActive <='0';
s_FIFOreset <='0';
s_2eFSMstate <= SET_CONTROL_SIGNALS;
when SET_CONTROL_SIGNALS =>
s_FSMactive <='1';
s_cyc <='1';
s_WE <= s_WE;
s_addrLatch <='0';
s_pipeCommActive <='0';
s_FIFOreset <='0';
s_2eFSMstate <= DO_PIPELINED_COMM;
when DO_PIPELINED_COMM =>
s_FSMactive <='1';
s_cyc <='1';
s_WE <= s_WE;
s_addrLatch <='0';
s_pipeCommActive <='1';
s_FIFOreset <='0';
if s_ackCountEnd='1' then
s_2eFSMstate <= WAIT_FOR_END;
else
s_2eFSMstate <= DO_PIPELINED_COMM;
end if;
when WAIT_FOR_END =>
s_FSMactive <='0';
s_cyc <='0';
s_WE <= s_WE;
s_addrLatch <='0';
s_pipeCommActive <='0';
s_FIFOreset <='0';
if TWOeInProgress_i='0' then
s_2eFSMstate <= FIFO_RESET;
end if;
when FIFO_RESET =>
s_FSMactive <='0';
s_cyc <='0';
s_WE <= s_WE;
s_addrLatch <='0';
s_pipeCommActive <='0';
s_FIFOreset <='1';
s_2eFSMstate <= IDLE;
when OTHERS =>
s_FSMactive <='0';
s_cyc <='0';
s_WE <= s_WE;
s_addrLatch <='0';
s_pipeCommActive <='0';
s_FIFOreset <='0';
s_2eFSMstate <= IDLE;
end case;
end if;
end if;
end process;
-- Local address latching & incrementing
p_locAddrHandling: process(clk_i)
begin
if rising_edge(clk_i) then
if s_reset='1' then
s_locAddr <= (others => '0');
elsif s_addrLatch='1' then
s_locAddr <= locAddr_i;
elsif s_pipeCommActive='1' and STALL_i='0' and s_cycleDelay='1' and ((writeFIFOempty_i='0' and s_WE='1') or (s_WE='0')) then
s_locAddr <= s_locAddr + 8;
else
s_locAddr <= s_locAddr;
end if;
end if;
end process;
-- Beat counter
p_FIFObeatCounter: process(clk_i)
begin
if rising_edge(clk_i) then
if s_reset='1' or s_pipeCommActive='0' then
s_runningBeatCount <= (others => '0');
elsif s_pipeCommActive='1' and STALL_i='0' and ((writeFIFOempty_i='0' and s_WE='1') or (s_WE='0')) then
s_runningBeatCount <= s_runningBeatCount + 1;
else
s_runningBeatCount <= s_runningBeatCount;
end if;
end if;
end process;
s_beatCountEnd <= '0' when s_runningBeatCount < beatCount_i else '1';
-- One clock cycle delay
p_cycleDelay: process(clk_i)
begin
if rising_edge(clk_i) then
s_cycleDelay <= s_pipeCommActive;
end if;
end process;
-- ACK pulse counter
p_ackCounter: process(clk_i)
begin
if rising_edge(clk_i) then
if s_reset='1' or s_addrLatch='1' then
s_ackCount <= (others => '0');
elsif ACK_i='1' then
s_ackCount <= s_ackCount + 1;
else
s_ackCount <= s_ackCount;
end if;
end if;
end process;
s_ackCountEnd <= '1' when s_ackCount=s_beatCount else '0';
-- Beat count register
p_beatCountRegister: process(clk_i)
begin
if rising_edge(clk_i) then
if reset_i = '1' then
s_beatCount <= (others => '0');
else
if s_addrLatch='1' then
s_beatCount <= beatCount_i;
else
s_beatCount <= s_beatCount;
end if;
end if;
end if;
end process;
-- Pipelined transfer STB signal control
p_pipSTB: process(clk_i)
begin
if rising_edge(clk_i) then
if reset_i = '1' then
s_stb <= '0';
else
if s_pipeCommActive='1' and ((writeFIFOempty_i='0' and s_WE='1') or (s_WE='0')) and s_beatCountEnd='0' then
s_stb <= '1';
else
s_stb <= '0';
end if;
end if;
end if;
end process;
s_FIFOrden <= '1' when s_pipeCommActive='1' and s_WE='1' and STALL_i='0' and writeFIFOempty_i='0' and s_beatCountEnd='0' else '0';
FIFOrden_o <= s_FIFOrden;
FIFOwren_o <= ACK_i when s_pipeCommActive='1' and s_WE='0' else '0';
-- FIFO reset
p_FIFOresetStretch: process(clk_i)
begin
if rising_edge(clk_i) then
s_FIFOreset_1 <= s_FIFOreset;
s_FIFOreset_2 <= s_FIFOreset_1;
end if;
end process;
FIFOreset_o <= s_FIFOreset or s_FIFOreset_1 or s_FIFOreset_2;
end RTL;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
----------------------------------------------------------------------------
-- --
-- CERN, BE --
-- --
-------------------------------------------------------------------------------
--
-- unit name: common_components
--
--! @brief The common_components package defines some common components.
--!
--! @date 24\01\2009
--
--! @version 1
--
--! @details
--!
--! <b>Dependencies:</b>\n
--!
--!
--! <b>References:</b>\n
--! \n
--! <reference two>
--!
--! <b>Modified by:</b>\n
--! Author: <name>
-------------------------------------------------------------------------------
--! \n\n<b>Last changes:</b>\n
--! 24\01\2009 paas header included\n
--! <extended description>
-------------------------------------------------------------------------------
--! @todo Adapt vhdl sintax to ohr standard\n
--! <another thing to do> \n
--
-------------------------------------------------------------------------------
package common_components is
component dpblockram
generic (dl : integer := 42; -- Length of the data word
al : integer := 10; -- Size of the addr map (10 = 1024 words)
nw : integer := 1024); -- Number of words
-- 'nw' has to be coherent with 'al'
port (clk : in std_logic; -- Global Clock
we : in std_logic; -- Write Enable
aw : in std_logic_vector(al - 1 downto 0); -- Write Address
ar : in std_logic_vector(al - 1 downto 0); -- Read Address
di : in std_logic_vector(dl - 1 downto 0); -- Data input
dw : out std_logic_vector(dl - 1 downto 0); -- Data write, normaly open
do : out std_logic_vector(dl - 1 downto 0)); -- Data output
end component dpblockram;
component TrueDpblockram
generic (dl : integer := 42; -- Length of the data word
al : integer := 10); -- Size of the addr map (10 = 1024 words)
-- 'nw' has to be coherent with 'al'
port (clk_a_i : in std_logic; -- Global Clock
we_a_i : in std_logic; -- Write Enable
a_a_i : in std_logic_vector(al - 1 downto 0); -- Write Address
di_a_i : in std_logic_vector(dl - 1 downto 0); -- Data input
do_a_o : out std_logic_vector(dl - 1 downto 0); -- Data write, normaly open
clk_b_i : in std_logic; -- Global Clock
we_b_i : in std_logic; -- Write Enable
a_b_i : in std_logic_vector(al - 1 downto 0); -- Write Address
di_b_i : in std_logic_vector(dl - 1 downto 0); -- Data input
do_b_o : out std_logic_vector(dl - 1 downto 0)); -- Data write, normaly open
end component TrueDpblockram;
component QuadPortRam
generic(Al : integer := 8;
nw : integer := 256;
dl : integer := 32
);
port(
Clk : in std_logic;
RstN : in std_logic;
Mux : in std_logic;
DAdd : in std_logic_vector(Al-1 downto 0);
DDataIn : in std_logic_vector(dl -1 downto 0);
DWrEn : in std_logic;
DDataOut : out std_logic_vector(dl -1 downto 0);
AAdd : in std_logic_vector(Al-1 downto 0);
ADataIn : in std_logic_vector(dl -1 downto 0);
AWrEn : in std_logic;
BAdd : in std_logic_vector(Al-1 downto 0);
BDataOut : out std_logic_vector(dl -1 downto 0);
CAdd : in std_logic_vector(Al-1 downto 0);
CDataOut : out std_logic_vector(dl -1 downto 0));
end component QuadPortRam;
component TriPortRamWr_RdRD
generic(Al : integer := 8;
nw : integer := 256;
dl : integer := 32);
port(
Clk : in std_logic;
RstN : in std_logic;
MuxB_CN : in std_logic;
AAdd : in std_logic_vector(Al-1 downto 0);
ADataIn : in std_logic_vector(dl - 1 downto 0);
AWrEn : in std_logic;
BAdd : in std_logic_vector(Al-1 downto 0);
BDataOut : out std_logic_vector(dl - 1 downto 0);
CAdd : in std_logic_vector(Al-1 downto 0);
CDataOut : out std_logic_vector(dl - 1 downto 0));
end component TriPortRamWr_RdRD;
component Fifo
generic(g_ADDR_LENGTH : integer := 8;
g_DATA_LENGTH : integer := 32);
port(
Rst : in std_logic;
Clk : in std_logic;
Mux : in std_logic;
-- NotUsed mux ='1' else FifoWrEn
--BusRead mux ='1' else FifoRead
DataRdEn : in std_logic;
Addr : in std_logic_vector(g_ADDR_LENGTH - 1 downto 0);
-- DataOutRec : out DataOutRecordType;
data_o : out std_logic_vector(g_DATA_LENGTH - 1 downto 0);
RdDone : out std_logic;
-- DataRdDone : in std_logic;
-- DataRdEn and DataRdDone should be synch with Mux in a top level entity
Index : out std_logic_vector(g_DATA_LENGTH - 1 downto 0);
-- FifoIn : in FifoInRecordType;
data_i : in std_logic_vector(g_DATA_LENGTH - 1 downto 0);
WrEn : in std_logic;
GetNewData : in std_logic; --Resquests new data from the FIFO. It should -- be synch with Mux in a top level entity
-- FifoControl : out FifoOutRecordType
Empty : out std_logic;
NewFifoDataReady : out std_logic;
FifoDataOut : out std_logic_vector(g_DATA_LENGTH - 1 downto 0);
FifoOverFlow : out std_logic);
end component Fifo;
component wb_dma
generic(c_dl : integer := 64;
c_al : integer := 64;
c_sell : integer := 8;
c_psizel : integer := 10);
port (
-- Common signals
clk_i : in std_logic;
reset_i : in std_logic;
transfer_done_o : out std_logic;
-- Slave WB with dma support
sl_dat_i : in std_logic_vector(c_dl -1 downto 0);
sl_dat_o : out std_logic_vector(c_dl -1 downto 0);
sl_adr_i : in std_logic_vector(c_al -1 downto 0);
sl_cyc_i : in std_logic;
sl_err_o : out std_logic;
sl_lock_i : in std_logic;
sl_rty_o : out std_logic;
sl_sel_i : in std_logic_vector(c_sell -1 downto 0);
sl_stb_i : in std_logic;
sl_ack_o : out std_logic;
sl_we_i : in std_logic;
sl_stall_o : out std_logic;
-- This signals are not WB compatible. Should be connected to 0 if not
-- used.
sl_psize_i : in std_logic_vector(c_psizel -1 downto 0);
-- sl_buff_access_i : in std_logic;
-- Master WB port to fabric
m_dat_i : in std_logic_vector(c_dl -1 downto 0);
m_dat_o : out std_logic_vector(c_dl -1 downto 0);
m_adr_o : out std_logic_vector(c_al -1 downto 0);
m_cyc_o : out std_logic;
m_err_i : in std_logic;
m_lock_o : out std_logic;
m_rty_i : in std_logic;
m_sel_o : out std_logic_vector(c_sell -1 downto 0);
m_stb_o : out std_logic;
m_ack_i : in std_logic;
m_we_o : out std_logic;
m_stall_i : in std_logic
);
end component wb_dma;
component ddr3_ctrl
generic(
--! Core's clock period in ps
g_MEMCLK_PERIOD : integer := 3000;
--! Core's reset polarity (1=active low, 0=active high)
g_RST_ACT_LOW : integer := 1;
--! Core's clock type (SINGLE_ENDED or DIFFERENTIAL)
g_INPUT_CLK_TYPE : string := "SINGLE_ENDED";
--! Set to TRUE for simulation
g_SIMULATION : string := "FALSE";
--! If TRUE, uses Xilinx calibration core (Input term, DQS centering)
g_CALIB_SOFT_IP : string := "TRUE";
--! User ports addresses maping (BANK_ROW_COLUMN or ROW_BANK_COLUMN)
g_MEM_ADDR_ORDER : string := "ROW_BANK_COLUMN";
--! DDR3 data port width
g_NUM_DQ_PINS : integer := 16;
--! DDR3 address port width
g_MEM_ADDR_WIDTH : integer := 14;
--! DDR3 bank address width
g_MEM_BANKADDR_WIDTH : integer := 3;
--! Wishbone port 0 data mask size (8-bit granularity)
g_P0_MASK_SIZE : integer := 4;
--! Wishbone port 0 data width
g_P0_DATA_PORT_SIZE : integer := 32;
--! Wishbone port 1 data mask size (8-bit granularity)
g_P1_MASK_SIZE : integer := 4;
--! Wishbone port 1 data width
g_P1_DATA_PORT_SIZE : integer := 32
);
port(
----------------------------------------------------------------------------
-- Clocks and reset
----------------------------------------------------------------------------
--! Core's differential clock input (pos)
--clk_p_i : in std_logic;
--! Core's differential clock input (neg)
--clk_n_i : in std_logic;
--! Core's clock input
clk_i : in std_logic;
--! Core's reset input (active low)
rst_n_i : in std_logic;
----------------------------------------------------------------------------
-- Status
----------------------------------------------------------------------------
--! Indicates end of calibration sequence at startup
calib_done : out std_logic;
----------------------------------------------------------------------------
-- DDR3 interface
----------------------------------------------------------------------------
--! DDR3 data bus
ddr3_dq_b : inout std_logic_vector(g_NUM_DQ_PINS-1 downto 0);
--! DDR3 address bus
ddr3_a_o : out std_logic_vector(g_MEM_ADDR_WIDTH-1 downto 0);
--! DDR3 bank address
ddr3_ba_o : out std_logic_vector(g_MEM_BANKADDR_WIDTH-1 downto 0);
--! DDR3 row address strobe
ddr3_ras_n_o : out std_logic;
--! DDR3 column address strobe
ddr3_cas_n_o : out std_logic;
--! DDR3 write enable
ddr3_we_n_o : out std_logic;
--! DDR3 on-die termination
ddr3_odt_o : out std_logic;
--! DDR3 reset
ddr3_rst_n_o : out std_logic;
--! DDR3 clock enable
ddr3_cke_o : out std_logic;
--! DDR3 lower byte data mask
ddr3_dm_o : out std_logic;
--! DDR3 upper byte data mask
ddr3_udm_o : out std_logic;
--! DDR3 lower byte data strobe (pos)
ddr3_dqs_p_b : inout std_logic;
--! DDR3 lower byte data strobe (neg)
ddr3_dqs_n_b : inout std_logic;
--! DDR3 upper byte data strobe (pos)
ddr3_udqs_p_b : inout std_logic;
--! DDR3 upper byte data strobe (pos)
ddr3_udqs_n_b : inout std_logic;
--! DDR3 clock (pos)
ddr3_clk_p_o : out std_logic;
--! DDR3 clock (neg)
ddr3_clk_n_o : out std_logic;
--! MCB internal termination calibration resistor
ddr3_rzq_b : inout std_logic;
--! MCB internal termination calibration
ddr3_zio_b : inout std_logic;
----------------------------------------------------------------------------
-- Wishbone bus - Port 0
----------------------------------------------------------------------------
--! Wishbone bus clock
wb0_clk_i : in std_logic;
--! Wishbone bus byte select
wb0_sel_i : in std_logic_vector(g_P0_MASK_SIZE - 1 downto 0);
--! Wishbone bus cycle select
wb0_cyc_i : in std_logic;
--! Wishbone bus cycle strobe
wb0_stb_i : in std_logic;
--! Wishbone bus write enable
wb0_we_i : in std_logic;
--! Wishbone bus address
wb0_addr_i : in std_logic_vector(29 downto 0);
--! Wishbone bus data input
wb0_data_i : in std_logic_vector(g_P0_DATA_PORT_SIZE - 1 downto 0);
--! Wishbone bus data output
wb0_data_o : out std_logic_vector(g_P0_DATA_PORT_SIZE - 1 downto 0);
--! Wishbone bus acknowledge
wb0_ack_o : out std_logic;
--! Wishbone bus stall (for pipelined mode)
wb0_stall_o : out std_logic;
----------------------------------------------------------------------------
-- Wishbone bus - Port 1
----------------------------------------------------------------------------
--! Wishbone bus clock
wb1_clk_i : in std_logic;
--! Wishbone bus byte select
wb1_sel_i : in std_logic_vector(g_P0_MASK_SIZE - 1 downto 0);
--! Wishbone bus cycle select
wb1_cyc_i : in std_logic;
--! Wishbone bus cycle strobe
wb1_stb_i : in std_logic;
--! Wishbone bus write enable
wb1_we_i : in std_logic;
--! Wishbone bus address
wb1_addr_i : in std_logic_vector(29 downto 0);
--! Wishbone bus data input
wb1_data_i : in std_logic_vector(g_P0_DATA_PORT_SIZE - 1 downto 0);
--! Wishbone bus data output
wb1_data_o : out std_logic_vector(g_P0_DATA_PORT_SIZE - 1 downto 0);
--! Wishbone bus acknowledge
wb1_ack_o : out std_logic;
--! Wishbone bus stall (for pipelined mode)
wb1_stall_o : out std_logic
);
end component ddr3_ctrl;
function log2_f(n : in integer) return integer ;
end package common_components;
package body common_components is
function log2_f(n : in integer) return integer is
variable i : integer := 0;
begin
while (2**i <= n) loop
i := i + 1;
end loop;
return i-1;
end log2_f;
end package body common_components;
\ No newline at end of file
-------------------------------------------------------------------------------
--
-- Title : WB_bus
-- Design : VME64xCore
-- Author : Pablo Alvarez
-- Company : CERN
--
-------------------------------------------------------------------------------
--
-- File : wb_dma.vhd
-- Generated : 25/02/2011
-- From : interface description file
--
-------------------------------------------------------------------------------
--
-- Description :
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.numeric_std.all;
use work.common_components.all;
entity wb_dma is
generic(c_dl : integer := 64;
c_al : integer := 64;
c_sell : integer := 8;
c_psizel : integer := 10);
port (
-- Common signals
clk_i : in std_logic;
reset_i : in std_logic;
transfer_done_o : out std_logic;
-- Slave WB with dma support
sl_dat_i : in std_logic_vector(c_dl -1 downto 0);
sl_dat_o : out std_logic_vector(c_dl -1 downto 0);
sl_adr_i : in std_logic_vector(c_al -1 downto 0);
sl_cyc_i : in std_logic;
sl_err_o : out std_logic;
sl_lock_i : in std_logic;
sl_rty_o : out std_logic;
sl_sel_i : in std_logic_vector(c_sell -1 downto 0);
sl_stb_i : in std_logic;
sl_ack_o : out std_logic;
sl_we_i : in std_logic;
sl_stall_o : out std_logic;
-- This signals are not WB compatible. Should be connected to 0 if not
-- used.
sl_psize_i : in std_logic_vector(c_psizel -1 downto 0);
-- sl_buff_access_i : in std_logic;
-- Master WB port to fabric
m_dat_i : in std_logic_vector(c_dl -1 downto 0);
m_dat_o : out std_logic_vector(c_dl -1 downto 0);
m_adr_o : out std_logic_vector(c_al -1 downto 0);
m_cyc_o : out std_logic;
m_err_i : in std_logic;
m_lock_o : out std_logic;
m_rty_i : in std_logic;
m_sel_o : out std_logic_vector(c_sell -1 downto 0);
m_stb_o : out std_logic;
m_ack_i : in std_logic;
m_we_o : out std_logic;
m_stall_i : in std_logic
);
end wb_dma;
architecture RTL of wb_dma is
signal ack_latched : std_logic;
begin
process(clk_i)
begin
if rising_edge(clk_i) then
if(sl_cyc_i = '1' and sl_stb_i = '1' and m_ack_i = '1') then
ack_latched <= '1';
elsif(sl_cyc_i = '0' or sl_stb_i = '0') then
ack_latched <= '0';
end if;
end if;
end process;
sl_stall_o <= m_stall_i;
m_we_o <= sl_we_i;
sl_ack_o <= m_ack_i;
m_stb_o <= sl_stb_i and not ack_latched;
m_sel_o <= sl_sel_i;
sl_rty_o <= '0';
sl_err_o <= '0';
m_adr_o <= sl_adr_i;
m_dat_o <= sl_dat_i;
sl_dat_o <= m_dat_i;
m_cyc_o <= sl_cyc_i;
end RTL;
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