ifs_reset='1'ors_mainFSMreset='1'ors_blockTransferLimitPulse='1'orVME_IACKIN_n_oversampled='0'then-- FSM is also reset on rising edge of address strobe (which indicates end of transfer) and on rising edge of block transfer limit signal
--s_dtackOE <= '0';
s_dataDir<='0';
s_dataOE<='0';
s_addrDir<='0';
s_addrOE<='0';
s_mainDTACK<='1';-- it was 'Z'
s_memReq<='0';
s_DSlatch<='1';
--s_WrRd <= '0';
s_incrementAddr<='0';
s_resetAddrOffset<='1';
s_dataPhase<='0';
s_dataToOutput<='0';
s_dataToAddrBus<='0';
s_transferActive<='0';
s_setLock<='0';
s_cyc<='0';
s_2eLatchAddr<="00";
s_TWOeInProgress<='0';
--s_readFIFO <= '0';
s_retry<='0';
s_berr<='0';
s_mainFSMstate<=IDLE;
transfer_done_flag<='0';
else
cases_mainFSMstateis
whenIDLE=>
-- if IACKinProgress_i='1' then
-- --s_dtackOE <= '1';
-- else
-- --s_dtackOE <= '0';
-- end if;
s_dataDir<='0';
s_dataOE<='0';
s_addrDir<='0';
s_addrOE<='0';
s_mainDTACK<='1';
s_memReq<='0';
s_DSlatch<='1';
--s_WrRd <= '0';
s_incrementAddr<='0';
s_resetAddrOffset<='1';
s_dataPhase<='0';
s_dataToOutput<='0';
s_dataToAddrBus<='0';
s_transferActive<='0';
s_setLock<='0';
s_cyc<='0';
s_2eLatchAddr<="00";
s_TWOeInProgress<='0';
--s_readFIFO <= '0';
s_retry<='0';
s_berr<='0';
transfer_done_flag<='0';
ifs_VMEaddrLatch='1'then-- If address strobe goes low, check if this slave is addressed
s_mainFSMstate<=DECODE_ACCESS;
else
s_mainFSMstate<=IDLE;
endif;
whenDECODE_ACCESS=>
--s_dtackOE <= '0';
s_dataDir<='0';
s_dataOE<='0';
s_addrDir<='0';
s_addrOE<='0';
s_mainDTACK<='1';
s_memReq<='0';
s_DSlatch<='1';
--s_WrRd <= '0';
s_incrementAddr<='0';
s_resetAddrOffset<='0';
s_dataPhase<='0';
s_dataToOutput<='0';
s_dataToAddrBus<='0';
s_transferActive<='0';
s_setLock<='0';
s_cyc<='0';
s_2eLatchAddr<="00";
s_TWOeInProgress<='0';
--s_readFIFO <= '0';
s_retry<='0';
s_berr<='0';
transfer_done_flag<='0';
ifs_lockSel='1'then-- LOCK request
s_mainFSMstate<=ACKNOWLEDGE_LOCK;
elsifs_addressingType=TWOedgethen-- start 2e transfer
s_mainFSMstate<=WAIT_FOR_DS_2e;
elsifs_confAccess='1'or(s_cardSel='1')then-- If this slave is addressed, start transfer
s_mainFSMstate<=WAIT_FOR_DS;
else
s_mainFSMstate<=DECODE_ACCESS;
endif;
whenWAIT_FOR_DS=>
--s_dtackOE <= '0';
s_dataDir<=VME_WRITE_n_oversampled;
s_dataOE<='0';
s_addrDir<=(s_is_d64)andVME_WRITE_n_oversampled;
s_addrOE<='0';
s_mainDTACK<='1';
s_memReq<='0';
s_DSlatch<='1';
--s_WrRd <= '0';
s_incrementAddr<='0';
s_resetAddrOffset<='0';
s_dataPhase<=s_dataPhase;
s_dataToOutput<='0';
s_dataToAddrBus<='0';
s_transferActive<='0';
s_setLock<='0';
s_cyc<='1';
s_2eLatchAddr<="00";
s_TWOeInProgress<='0';
--s_readFIFO <= '0';
s_retry<='0';
s_berr<='0';
ifVME_DS_n_oversampled/="11"then
s_mainFSMstate<=LATCH_DS;
else
s_mainFSMstate<=WAIT_FOR_DS;
endif;
whenLATCH_DS=>
--s_dtackOE <= '0';
s_dataDir<=VME_WRITE_n_oversampled;
s_dataOE<='0';
s_addrDir<=(s_is_d64)andVME_WRITE_n_oversampled;
s_addrOE<='0';
s_mainDTACK<='1';
s_memReq<='0';
s_DSlatch<='1';
--s_WrRd <= '0';
s_incrementAddr<='0';
s_resetAddrOffset<='0';
s_dataPhase<=s_dataPhase;
s_dataToOutput<='0';
s_dataToAddrBus<='0';
s_transferActive<='0';
s_setLock<='0';
s_cyc<='1';
s_2eLatchAddr<="00";
s_TWOeInProgress<='0';
--s_readFIFO <= '0';
s_retry<='0';
s_berr<='0';
s_mainFSMstate<=CHECK_TRANSFER_TYPE;
whenCHECK_TRANSFER_TYPE=>
--s_dtackOE <= '0';
s_dataDir<=VME_WRITE_n_oversampled;
s_dataOE<='0';
s_addrDir<=(s_is_d64)andVME_WRITE_n_oversampled;
s_addrOE<='0';
s_mainDTACK<='1';
s_memReq<='0';
s_DSlatch<='0';
s_incrementAddr<='0';
s_resetAddrOffset<='0';
s_dataPhase<=s_dataPhase;
s_dataToOutput<='0';
s_dataToAddrBus<='0';
s_transferActive<='1';
s_setLock<='0';
s_cyc<='1';
s_2eLatchAddr<="00";
s_TWOeInProgress<='0';
--s_readFIFO <= '0';
s_retry<='0';
s_berr<='0';
ifs_transferType=SINGLEors_transferType=BLTthen
s_mainFSMstate<=MEMORY_REQ;
s_memReq<='1';
elsifs_transferType=MBLTands_dataPhase='0'then
s_mainFSMstate<=DTACK_LOW;
s_memReq<='0';
elsifs_transferType=MBLTands_dataPhase='1'then
s_mainFSMstate<=MEMORY_REQ;
s_memReq<='0';
endif;
whenMEMORY_REQ=>
--s_dtackOE <= '1';
s_dataDir<=VME_WRITE_n_oversampled;
s_dataOE<='1';
s_addrDir<=(s_is_d64)andVME_WRITE_n_oversampled;
s_addrOE<='0';
s_mainDTACK<='1';
s_memReq<=stall_i;
s_DSlatch<='0';
s_incrementAddr<='0';
s_resetAddrOffset<='0';
s_dataPhase<='1';
s_dataToOutput<='0';
s_dataToAddrBus<='0';
s_transferActive<='1';
s_setLock<='0';
s_cyc<='1';
s_2eLatchAddr<="00";
s_TWOeInProgress<='0';
--s_readFIFO <= '0';
s_retry<='0';
s_berr<='0';
ifs_memAck='1'ands_RW='0'then
s_mainFSMstate<=DTACK_LOW;
--s_WrRd <= '0';
elsifs_memAck='1'ands_RW='1'then
s_mainFSMstate<=DATA_TO_BUS;
--s_WrRd <= '0';
else
s_mainFSMstate<=MEMORY_REQ;
--s_WrRd <= VME_WRITE_n_oversampled;
endif;
whenDATA_TO_BUS=>
--s_dtackOE <= '1';
s_dataDir<=VME_WRITE_n_oversampled;
s_dataOE<='1';
s_addrDir<=(s_is_d64)andVME_WRITE_n_oversampled;
s_addrOE<='0';
s_mainDTACK<='1';
s_memReq<='0';
s_DSlatch<='0';
--s_WrRd <= '0';
s_incrementAddr<='0';
s_resetAddrOffset<='0';
s_dataPhase<='1';
s_setLock<='0';
s_cyc<='1';
s_2eLatchAddr<="00";
s_TWOeInProgress<='0';
--s_readFIFO <= '0';
s_retry<='0';
ifs_transferType=MBLTthen
s_dataToOutput<='0';
s_dataToAddrBus<='1';
else
s_dataToOutput<='1';
s_dataToAddrBus<='0';
endif;
s_transferActive<='1';
s_berr<='0';
s_mainFSMstate<=DTACK_LOW;
whenDTACK_LOW=>
--s_dtackOE <= '1';
s_dataDir<=VME_WRITE_n_oversampled;
s_dataOE<='1';
s_addrDir<=(s_is_d64)andVME_WRITE_n_oversampled;
s_addrOE<='0';
s_mainDTACK<='0';
s_memReq<='0';
s_DSlatch<='0';
--s_WrRd <= '0';
s_incrementAddr<='0';
s_resetAddrOffset<='0';
s_dataPhase<=s_dataPhase;
s_dataToOutput<=s_dataToOutput;
s_dataToAddrBus<=s_dataToAddrBus;
s_transferActive<='1';
s_setLock<='0';
s_cyc<='1';
s_2eLatchAddr<="00";
s_TWOeInProgress<='0';
--s_readFIFO <= '0';
s_retry<='0';
s_berr<='0';
ifVME_DS_n_oversampled="11"then
s_mainFSMstate<=DECIDE_NEXT_CYCLE;
else
s_mainFSMstate<=DTACK_LOW;
endif;
whenDECIDE_NEXT_CYCLE=>
--s_dtackOE <= '0';
s_dataDir<=VME_WRITE_n_oversampled;
s_dataOE<='0';
s_addrDir<=(s_is_d64)andVME_WRITE_n_oversampled;
s_addrOE<='0';
s_mainDTACK<='1';
s_memReq<='0';
s_DSlatch<='0';
--s_WrRd <= '0';
s_incrementAddr<='0';
s_resetAddrOffset<='0';
s_dataPhase<=s_dataPhase;
s_dataToOutput<='0';
s_dataToAddrBus<='0';
s_transferActive<='1';
s_setLock<='0';
s_cyc<='1';
s_2eLatchAddr<="00";
s_TWOeInProgress<='0';
--s_readFIFO <= '0';
s_retry<='0';
s_berr<='0';
ifs_transferType=SINGLEthen
s_mainFSMstate<=WAIT_FOR_DS;
elsifs_transferType=BLTthen
s_mainFSMstate<=INCREMENT_ADDR;
elsifs_transferType=MBLTands_dataPhase='0'then
s_mainFSMstate<=SET_DATA_PHASE;
elsifs_transferType=MBLTands_dataPhase='1'then
s_mainFSMstate<=INCREMENT_ADDR;
endif;
whenINCREMENT_ADDR=>
--s_dtackOE <= '0';
s_dataDir<=VME_WRITE_n_oversampled;
s_dataOE<='0';
s_addrDir<=(s_is_d64)andVME_WRITE_n_oversampled;
s_addrOE<='0';
s_mainDTACK<='1';
s_memReq<='0';
s_DSlatch<='0';
--s_WrRd <= '0';
s_incrementAddr<='1';
s_resetAddrOffset<='0';
s_dataPhase<=s_dataPhase;
s_dataToOutput<='0';
s_dataToAddrBus<='0';
s_transferActive<='1';
s_setLock<='0';
s_cyc<='1';
s_2eLatchAddr<="00";
s_TWOeInProgress<='0';
--s_readFIFO <= '0';
s_retry<='0';
s_berr<='0';
s_mainFSMstate<=WAIT_FOR_DS;
whenSET_DATA_PHASE=>
--s_dtackOE <= '0';
s_dataDir<=VME_WRITE_n_oversampled;
s_dataOE<='0';
s_addrDir<=(s_is_d64)andVME_WRITE_n_oversampled;
s_addrOE<='0';
s_mainDTACK<='1';
s_memReq<='0';
s_DSlatch<='0';
--s_WrRd <= '0';
s_incrementAddr<='0';
s_resetAddrOffset<='0';
s_dataPhase<='1';
s_dataToOutput<='0';
s_dataToAddrBus<='0';
s_transferActive<='1';
s_setLock<='0';
s_cyc<='1';
s_2eLatchAddr<="00";
s_TWOeInProgress<='0';
--s_readFIFO <= '0';
s_retry<='0';
s_berr<='0';
s_mainFSMstate<=WAIT_FOR_DS;
whenACKNOWLEDGE_LOCK=>
--s_dtackOE <= '1';
s_dataDir<=VME_WRITE_n_oversampled;
s_dataOE<='0';
s_addrDir<=(s_is_d64)andVME_WRITE_n_oversampled;
s_addrOE<='0';
ifVME_DS_n_oversampled/="11"then
s_mainDTACK<='0';
else
s_mainDTACK<='1';
endif;
s_memReq<='0';
s_DSlatch<='0';
--s_WrRd <= '0';
s_incrementAddr<='0';
s_resetAddrOffset<='0';
s_dataPhase<='0';
s_dataToOutput<='0';
s_dataToAddrBus<='0';
s_transferActive<='0';
s_setLock<='1';
s_cyc<='0';
s_2eLatchAddr<="00";
s_TWOeInProgress<='0';
--s_readFIFO <= '0';
s_retry<='0';
s_berr<='0';
s_mainFSMstate<=ACKNOWLEDGE_LOCK;-- wait here until AS goes high, which resets the FSM
whenWAIT_FOR_DS_2e=>
--s_dtackOE <= '0';
s_dataDir<='0';
s_dataOE<='1';
s_addrDir<='0';
s_addrOE<='1';
s_mainDTACK<='1';
s_memReq<='0';
s_DSlatch<='0';
--s_WrRd <= '0';
s_incrementAddr<='0';
s_resetAddrOffset<='0';
s_dataPhase<='0';
s_dataToOutput<='0';
s_dataToAddrBus<='0';
s_transferActive<='0';
s_setLock<='0';
s_cyc<='0';
s_2eLatchAddr<="01";
s_TWOeInProgress<='0';
--s_readFIFO <= '0';
s_retry<='0';
s_berr<='0';
ifVME_DS_n_oversampled(0)='0'then
s_mainFSMstate<=ADDR_PHASE_1;
endif;
whenADDR_PHASE_1=>
--s_dtackOE <= '0';
s_dataDir<='0';
s_dataOE<='1';
s_addrDir<='0';
s_addrOE<='1';
s_mainDTACK<='1';
--s_WrRd <= '0';
s_memReq<='0';
s_DSlatch<='0';
s_incrementAddr<='0';
s_resetAddrOffset<='0';
s_dataPhase<='0';
s_dataToOutput<='0';
s_dataToAddrBus<='0';
s_transferActive<='0';
s_setLock<='0';
s_cyc<='0';
s_2eLatchAddr<="00";
s_TWOeInProgress<='0';
--s_readFIFO <= '0';
s_retry<='0';
s_berr<='0';
s_mainFSMstate<=DECODE_ACCESS_2e;
whenDECODE_ACCESS_2e=>
--s_dtackOE <= '1';
s_dataDir<='0';
s_dataOE<='1';
s_addrDir<='0';
s_addrOE<='1';
s_mainDTACK<='1';
--s_WrRd <= '0';
s_memReq<='0';
s_DSlatch<='0';
s_incrementAddr<='0';
s_resetAddrOffset<='0';
s_dataPhase<='0';
s_dataToOutput<='0';
s_dataToAddrBus<='0';
s_transferActive<='0';
s_setLock<='0';
s_cyc<='0';
s_2eLatchAddr<="00";
s_TWOeInProgress<='0';
--s_readFIFO <= '0';
s_retry<='0';
ifs_XAMtype=XAM_errorthen
s_berr<='1';
else
s_berr<='0';
endif;
ifs_cardSel='1'then-- if module is selected, proceed with DTACK, else wait here until FSM reset by AS going high
s_RW<=VME_WRITE_n_oversampled;--and s_WrRd; -- read if s_RW='1', write if s_RW='0'
s_memAck<=s_memAckCSR(0)ormemAckWB_i;
-- Access decode (NOTE: since A64 is supported, there are 4 64-bit FUNC_ADERs, because two consecutive 32-bit FUNC_ADERs are needed to decode a 64 bit address)
p_functMatch:process(clk_i)-- NOTE: interface will respond to different addressing types and will attempt to decode only the address width that it is given, even though the ADEM and ADER registers may contain a mask, that is greater than the current address width
begin
ifrising_edge(clk_i)then-- Added by pablo. Guess it should be clocked as the only signal in the