Commit a686b998 authored by Tomasz Wlostowski's avatar Tomasz Wlostowski

hdl/ip_cores: removed vme64x-core files from the repo

parent ec77872b
Please send any questions or opinions to:
Developers: rok.stefanic@cosylab.com, ziga.kroflic@cosylab.com
OHWR list: vme64x-core@ohwr.org
\ No newline at end of file
--==============================================================--
--Design Units : CTX1 Control and Statistics
--Size:
--Speed:
--File Name: MebRam.vhd
--
--Purpose: The dpblockram implements a synthetisable model of a
-- dual port RAM.
-- There are an input data and addr ports to allow the
-- writing at the reception of a GMT frame.
-- The output data and addr ports allow a simultanous
-- reading of the circular buffer by the user, at the
-- same time than it is beeing written.
--
-- The frame and the millisecond stamp are stored in the
-- same ram word. It is the task of the MEB block to
-- separate the frame data from the millisecond stamp data.
--
--Limitations:
--
--Errors:
--
--Libraries:
--
--Dependancies: It instantiates a synthetisable model of a DPRAM
-- See MebRam.vhd
--
--Author: Pablo Antonio Alvarez Sanchez
-- European Organisation for Nuclear Research
-- SL SPS/LHC -- Control -- Timing Division
-- CERN, Geneva, Switzerland, CH-1211
-- Building 864 Room 1 - A24
--
--Simulator: ModelSim XE 5.5e_p1
--==============================================================--
--Revision List
--Version Author Date Changes
--
--1.0 PAAS 30.09.2002 Added comments, tested with the
-- rest of the design
--==============================================================--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity dpblockram is
generic (dl : integer := 42; -- Length of the data word
al : integer := 10; -- Size of the addr map (10 = 1024 words)
nw : integer := 1024); -- Number of words
-- 'nw' has to be coherent with 'al'
port (clk : in std_logic; -- Global Clock
we : in std_logic; -- Write Enable
aw : in std_logic_vector(al - 1 downto 0); -- Write Address
ar : in std_logic_vector(al - 1 downto 0); -- Read Address
di : in std_logic_vector(dl - 1 downto 0); -- Data input
dw : out std_logic_vector(dl - 1 downto 0); -- Data write, normaly open
do : out std_logic_vector(dl - 1 downto 0)); -- Data output
end dpblockram;
-- DATA OUTPUT NOT REGISTERED!
--library synplify;
--use synplify.attributes.all;
architecture syn of dpblockram is
type ram_type is array (nw - 1 downto 0) of std_logic_vector (dl - 1 downto 0);
signal RAM : ram_type;
signal read_a : std_logic_vector(al - 1 downto 0);
signal read_ar : std_logic_vector(al - 1 downto 0);
--attribute syn_ramstyle of RAM : signal is "block_ram";
begin
process (clk)
begin
if (clk'event and clk = '1') then
if (we = '1') then
RAM(conv_integer(aw)) <= di;
end if;
read_a <= aw;
read_ar <= ar;
end if;
end process;
dw <= RAM(conv_integer(read_a));
do <= RAM(conv_integer(read_ar)); -- Notice that the Data Output is not registered
end syn;
-------------------------------------------------------------------------------
--
-- Title : IRQ_controller
-- Design : VME64xCore
-- Author : Ziga Kroflic
-- Company : Cosylab
--
-------------------------------------------------------------------------------
--
-- File : IRQ_controller.vhd
-- Generated : Thu Apr 1 08:48:48 2010
-- From : interface description file
-- By : Itf2Vhdl ver. 1.20
--
-------------------------------------------------------------------------------
--
-- Description :
--
-------------------------------------------------------------------------------
--{{ Section below this comment is automatically maintained
-- and may be overwritten
--{entity {IRQ_controller} architecture {RTL}}
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_unsigned.all;
entity IRQ_controller is
port(
clk_i : in std_logic;
reset_i : in std_logic;
VME_IRQ_n_o : out std_logic_vector(6 downto 0);
VME_IACKIN_n_i : in std_logic;
VME_IACKOUT_n_o : out std_logic;
VME_AS_n_i : in STD_LOGIC;
VME_DS_n_i : in STD_LOGIC_VECTOR(1 downto 0);
irqDTACK_o : out std_logic;
IACKinProgress_o: out std_logic;
IRQ_i: in std_logic;
locAddr_i: in std_logic_vector(3 downto 1);
IDtoData_o: out std_logic;
IRQlevelReg_i: in std_logic_vector(7 downto 0)
);
end IRQ_controller;
architecture RTL of IRQ_controller is
component RisEdgeDetection is
port (
sig_i, clk_i: in std_logic;
RisEdge_o: out std_logic );
end component;
component SigInputSample is
port (
sig_i, clk_i: in std_logic;
sig_o: out std_logic );
end component;
component RegInputSample is
generic(
width: natural:=8
);
port (
reg_i: in std_logic_vector(width-1 downto 0);
reg_o: out std_logic_vector(width-1 downto 0):=(others => '0');
clk_i: in std_logic
);
end component;
signal VME_IACKIN_n_oversampled: std_logic;
signal VME_DS_n_oversampled : STD_LOGIC_VECTOR(1 downto 0);
signal s_reset: std_logic;
signal s_VME_IACKOUT: std_logic;
signal s_irqDTACK: std_logic; -- acknowledge of IACK cycle
signal s_applyIRQmask: std_logic; -- clears acknowlegded interrupt
signal s_IDtoData: std_logic; -- puts IRQ Status/ID register on data bus
signal s_IACKmatch: std_logic; -- signals that an active interrupt is being acknowledged
signal s_wbIRQrisingEdge: std_logic; -- rising edge detection on interrupt line
signal s_IRQenabled: std_logic; -- indicates that interrupts are enabled (IRQlevelReg has a valid level value)
signal s_IRQreg: std_logic; -- registers pending interrupt
type t_IRQstates is ( IDLE,
WAIT_FOR_DS,
CHECK_MATCH,
APPLY_MASK_AND_DATA,
PROPAGATE_IACK,
APPLY_DTACK
);
signal s_IRQstate: t_IRQstates;
begin
s_reset <= reset_i;
irqDTACK_o <= '0' when s_irqDTACK='0' else 'Z';
VME_IACKOUT_n_o <= '0' when s_VME_IACKOUT='0' else 'Z';
p_IRQcontrolFSM: process(clk_i)
begin
if rising_edge(clk_i) then
if s_reset='1' then
s_VME_IACKOUT <= '1';
s_irqDTACK <= '1';
s_applyIRQmask <= '0';
s_IDtoData <= '0';
IACKinProgress_o <= '0';
s_IRQstate <= IDLE;
else
case s_IRQstate is
when IDLE =>
s_VME_IACKOUT <= '1';
s_irqDTACK <= '1';
s_applyIRQmask <= '0';
s_IDtoData <= '0';
IACKinProgress_o <= '0';
if VME_IACKIN_n_oversampled='0' then
s_IRQstate <= WAIT_FOR_DS;
else
s_IRQstate <= IDLE;
end if;
when WAIT_FOR_DS =>
s_VME_IACKOUT <= '1';
s_irqDTACK <= '1';
s_applyIRQmask <= '0';
s_IDtoData <= '0';
IACKinProgress_o <= '0';
if VME_DS_n_oversampled/="11" then
s_IRQstate <= CHECK_MATCH;
else
s_IRQstate <= WAIT_FOR_DS;
end if;
when CHECK_MATCH =>
s_VME_IACKOUT <= '1';
s_irqDTACK <= '1';
s_applyIRQmask <= '0';
s_IDtoData <= '0';
IACKinProgress_o <= '0';
if s_IACKmatch='1' then
s_IRQstate <= APPLY_MASK_AND_DATA;
else
s_IRQstate <= PROPAGATE_IACK;
end if;
when APPLY_MASK_AND_DATA =>
s_VME_IACKOUT <= '1';
s_irqDTACK <= '1';
s_applyIRQmask <= '1';
s_IDtoData <= '1';
IACKinProgress_o <= '1';
s_IRQstate <= APPLY_DTACK;
when APPLY_DTACK =>
s_VME_IACKOUT <= '1';
s_irqDTACK <= '0';
s_applyIRQmask <= '0';
s_IDtoData <= '1';
IACKinProgress_o <= '1';
if VME_IACKIN_n_oversampled='1' then
s_IRQstate <= IDLE;
else
s_IRQstate <= APPLY_DTACK;
end if;
when PROPAGATE_IACK =>
s_VME_IACKOUT <= VME_IACKIN_n_oversampled;
s_irqDTACK <= '1';
s_applyIRQmask <= '0';
s_IDtoData <= '0';
IACKinProgress_o <= '0';
if VME_IACKIN_n_oversampled='1' then
s_IRQstate <= IDLE;
else
s_IRQstate <= PROPAGATE_IACK;
end if;
when OTHERS =>
s_VME_IACKOUT <= '1';
s_irqDTACK <= '1';
s_applyIRQmask <= '0';
s_IDtoData <= '0';
IACKinProgress_o <= '0';
s_IRQstate <= IDLE;
end case;
end if;
end if;
end process;
s_IACKmatch <= '1' when "00000"&locAddr_i = IRQlevelReg_i else '0';
s_IRQenabled <= '1' when IRQlevelReg_i < 8 and IRQlevelReg_i /= 0 else '0';
IDtoData_o <= s_IDtoData;
-- Setting and clearing pending interrupt request register
p_IRQregHandling: process(clk_i)
begin
if rising_edge(clk_i) then
if s_reset='1' then
s_IRQreg <= '0';
elsif s_applyIRQmask='1' then
s_IRQreg <= '0';
else
s_IRQreg <= s_wbIRQrisingEdge and s_IRQenabled;
end if;
end if;
end process;
-- Driving VME_IRQ lines
gen_IRQoutput: for i in 0 to 6 generate
VME_IRQ_n_o(i) <= '0' when s_IRQreg='1' and IRQlevelReg_i=(i+1) else 'Z';
end generate;
-- Signal input oversample & rising edge detection
IRQrisingEdge: RisEdgeDetection
port map (
sig_i => IRQ_i,
clk_i => clk_i,
RisEdge_o => s_wbIRQrisingEdge
);
IACKINinputSample: SigInputSample
port map(
sig_i => VME_IACKIN_n_i,
sig_o => VME_IACKIN_n_oversampled,
clk_i => clk_i
);
DSinputSample: RegInputSample
generic map(
width => 2
)
port map(
reg_i => VME_DS_n_i,
reg_o => VME_DS_n_oversampled,
clk_i => clk_i
);
end RTL;
files = [
"VME_bus.vhd",
"VME_CR_pack.vhd",
"wb_dma.vhd",
"VME_CSR_pack.vhd",
"VME_pack.vhd",
"SharedComps.vhd",
"DpBlockRam.vhd",
"TrueDpBlockRam.vhd",
"common_components.vhd",
"VME64xCore_NoIpTop.vhd" ];
library IEEE;
use IEEE.STD_LOGIC_1164.all;
-- tripple sample sig_i signals to avoid metastable states
entity SigInputSample is
port (
sig_i, clk_i: in std_logic;
sig_o: out std_logic );
end SigInputSample;
architecture RTL of SigInputSample is
signal s_1: std_logic;
signal s_2: std_logic;
begin
process(clk_i)
begin
if rising_edge(clk_i) then
s_1 <= sig_i;
s_2 <= s_1;
sig_o <= s_2;
end if;
end process;
end RTL;
-- ***************************************************
library IEEE;
use IEEE.STD_LOGIC_1164.all;
-- double sample sig_i signals to avoid metastable states
entity DoubleSigInputSample is
port (
sig_i, clk_i: in std_logic;
sig_o: out std_logic );
end DoubleSigInputSample;
architecture RTL of DoubleSigInputSample is
signal s_1: std_logic;
-- signal s_2: std_logic;
begin
process(clk_i)
begin
if rising_edge(clk_i) then
s_1 <= sig_i;
sig_o <= s_1;
end if;
end process;
end RTL;
-- ***************************************************
library IEEE;
use IEEE.STD_LOGIC_1164.all;
-- detect rising edge
entity RisEdgeDetection is
port (
sig_i, clk_i: in std_logic;
RisEdge_o: out std_logic );
end RisEdgeDetection;
architecture RTL of RisEdgeDetection is
signal s_1: std_logic;
begin
process(clk_i)
begin
if rising_edge(clk_i) then
s_1 <= sig_i;
if s_1 = '0' and sig_i = '1' then
RisEdge_o <= '1';
else
RisEdge_o <= '0';
end if;
end if;
end process;
end RTL;
-- ***************************************************
library IEEE;
use IEEE.STD_LOGIC_1164.all;
-- detect falling edge
entity FallingEdgeDetection is
port (
sig_i, clk_i: in std_logic;
FallEdge_o: out std_logic );
end FallingEdgeDetection;
architecture RTL of FallingEdgeDetection is
signal s_1: std_logic;
begin
process(clk_i)
begin
if rising_edge(clk_i) then
s_1 <= sig_i;
if s_1 = '1' and sig_i = '0' then
FallEdge_o <= '1';
else
FallEdge_o <= '0';
end if;
end if;
end process;
end RTL;
-- ***************************************************
library IEEE;
use IEEE.STD_LOGIC_1164.all;
-- give pulse (sigEdge_o) at rising and falling edge
entity EdgeDetection is
port (
sig_i,
clk_i: in std_logic;
sigEdge_o: out std_logic
);
end EdgeDetection;
architecture RTL of EdgeDetection is
signal s_1: std_logic;
begin
process(clk_i)
begin
if rising_edge(clk_i) then
s_1 <= sig_i;
if (s_1 = '0' and sig_i = '1') or (s_1 = '1' and sig_i = '0') then
sigEdge_o <= '1';
else
sigEdge_o <= '0';
end if;
end if;
end process;
end RTL;
-- ***************************************************
library IEEE;
use IEEE.STD_LOGIC_1164.all;
-- triple sample input register reg_i to avoid metastable states
-- and catching of transition values
entity RegInputSample is
generic(
width: natural:=8
);
port (
reg_i: in std_logic_vector(width-1 downto 0);
reg_o: out std_logic_vector(width-1 downto 0);
clk_i: in std_logic
);
end RegInputSample;
architecture RTL of RegInputSample is
signal reg_1, reg_2: std_logic_vector(width-1 downto 0);
begin
process(clk_i)
begin
if rising_edge(clk_i) then
reg_1 <= reg_i;
reg_2 <= reg_1;
reg_o <= reg_2;
end if;
end process;
end RTL;
-- ***************************************************
library IEEE;
use IEEE.STD_LOGIC_1164.all;
-- triple sample input register reg_i to avoid metastable states
-- and catching of transition values
entity DoubleRegInputSample is
generic(
width: natural:=8
);
port (
reg_i: in std_logic_vector(width-1 downto 0);
reg_o: out std_logic_vector(width-1 downto 0);
clk_i: in std_logic
);
end DoubleRegInputSample;
architecture RTL of DoubleRegInputSample is
signal reg_1, reg_2: std_logic_vector(width-1 downto 0);
begin
process(clk_i)
begin
if rising_edge(clk_i) then
reg_1 <= reg_i;
reg_o <= reg_1;
end if;
end process;
end RTL;
\ No newline at end of file
--==============================================================--
--Design Units : CTX1 Control and Statistics
--Size:
--Speed:
--File Name: MebRam.vhd
--
--Purpose: The dpblockram implements a synthetisable model of a
-- dual port RAM.
-- There are an input data and addr ports to allow the
-- writing at the reception of a GMT frame.
-- The output data and addr ports allow a simultanous
-- reading of the circular buffer by the user, at the
-- same time than it is beeing written.
--
-- The frame and the millisecond stamp are stored in the
-- same ram word. It is the task of the MEB block to
-- separate the frame data from the millisecond stamp data.
--
--Limitations:
--
--Errors:
--
--Libraries:
--
--Dependancies: It instantiates a synthetisable model of a DPRAM
-- See MebRam.vhd
--
--Author: Pablo Antonio Alvarez Sanchez
-- European Organisation for Nuclear Research
-- SL SPS/LHC -- Control -- Timing Division
-- CERN, Geneva, Switzerland, CH-1211
-- Building 864 Room 1 - A24
--
--Simulator: ModelSim XE 5.5e_p1
--==============================================================--
--Revision List
--Version Author Date Changes
--
--1.0 PAAS 30.09.2002 Added comments, tested with the
-- rest of the design
--==============================================================--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity TrueDpblockram is
generic (dl : integer := 42; -- Length of the data word
al : integer := 10); -- Size of the addr map (10 = 1024 words)
-- 'nw' has to be coherent with 'al'
port (clk_a_i : in std_logic; -- Global Clock
we_a_i : in std_logic; -- Write Enable
a_a_i : in std_logic_vector(al - 1 downto 0); -- Write Address
di_a_i : in std_logic_vector(dl - 1 downto 0); -- Data input
do_a_o : out std_logic_vector(dl - 1 downto 0); -- Data write, normaly open
clk_b_i : in std_logic; -- Global Clock
we_b_i : in std_logic; -- Write Enable
a_b_i : in std_logic_vector(al - 1 downto 0); -- Write Address
di_b_i : in std_logic_vector(dl - 1 downto 0); -- Data input
do_b_o : out std_logic_vector(dl - 1 downto 0)); -- Data write, normaly open
end TrueDpblockram;
-- DATA OUTPUT NOT REGISTERED!
--library synplify;
--use synplify.attributes.all;
architecture syn of TrueDpblockram is
type t_ram is array (2**al-1 downto 0) of std_logic_vector (dl-1 downto 0);
shared variable ram: t_ram;
begin
process (clk_a_i)
begin
if (clk_a_i'event and clk_a_i = '1') then
-- if (<enableA> = '1') then
if (we_a_i = '1') then
ram(conv_integer(a_a_i)) := di_a_i;
end if;
do_a_o <= ram(conv_integer(a_a_i));
-- end if;
end if;
end process;
process (clk_b_i)
begin
if (clk_b_i'event and clk_b_i = '1') then
-- if (<enableB> = '1') then
if (we_b_i = '1') then
ram(conv_integer(a_b_i)) := di_b_i;
end if;
do_b_o <= ram(conv_integer(a_b_i));
end if;
-- end if;
end process;
end syn;
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library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.numeric_std.all;
use work.VME_pack.all;
package VME_CR_pack is
constant c_cr_array : t_cr_array(2**12 downto 0) :=
(
16#00# => (others => '0'),
-- Length of ROM
16#01# => x"01",
16#02# => x"00",
16#03# => x"00",
--Configuration ROM data acces width
16#04# => x"00",
--Configuration ROM data acces width
16#05# => x"01",
--Ascii "C"
16#06# => x"01",
--Ascii "R"
16#07# => x"43",
--Manufacturer's ID
16#08# => x"52",
16#09# => x"01",
16#0A# => x"02",
--board id
16#0B# => x"03",
16#0C# => x"03",
16#0D# => x"04",
16#0E# => x"04",
--Rev id
16#0F# => x"03",
16#10# => x"03",
16#11# => x"04",
16#12# => x"04",
--Point to ascii null terminatied
16#13# => x"03",
16#14# => x"03",
16#15# => x"04",
--Program Id code
16#1E# => x"12",
--Function data access width
16#40# => x"85", -- Fun 0 D32
16#41# => x"85", -- Fun 1 D32
16#42# => x"85", -- Fun 2
16#43# => x"85", -- Fun 3
16#44# => x"85", -- Fun 4
16#45# => x"85", -- Fun 5
16#46# => x"85", -- Fun 6
16#47# => x"85", -- Fun 7
--Function AM code Mask
16#48# => x"00", -- Fun 0
16#49# => x"00", -- Fun 0
16#4A# => x"00", -- Fun 0
16#4B# => x"01", -- Fun 0 X"01" AM=20
16#4C# => x"00", -- Fun 0
16#4D# => x"00", -- Fun 0
16#4E# => x"00", -- Fun 0
16#4F# => x"00", -- Fun 0
16#50# => x"03", -- Fun 1 x"02" AM=39, AM=38
16#51# => x"00", -- Fun 1
16#52# => x"00", -- Fun 1
16#53# => x"00", -- Fun 1
16#54# => x"00", -- Fun 1
16#55# => x"00", -- Fun 1
16#56# => x"00", -- Fun 1
16#57# => x"00", -- Fun 1
--
--
16#58# => x"03", -- Fun 2 x"02" AM=39, AM=38
16#59# => x"00", -- Fun 2
16#5a# => x"00", -- Fun 2
16#5b# => x"00", -- Fun 2
16#5c# => x"00", -- Fun 2
16#5d# => x"00", -- Fun 2
16#5e# => x"00", -- Fun 2 X"10" AM=0c
16#5f# => x"00", -- Fun 2
--
--
16#60# => x"00", -- Fun 3
16#61# => x"00", -- Fun 3
16#62# => x"00", -- Fun 3
16#63# => x"00", -- Fun 3
16#64# => x"00", -- Fun 3
16#65# => x"00", -- Fun 3
16#66# => x"03", -- Fun 3
16#67# => x"00", -- Fun 3
--
16#68# => x"00", -- Fun 4
16#69# => x"00", -- Fun 4
16#6a# => x"00", -- Fun 4
16#6b# => x"00", -- Fun 4
16#6c# => x"00", -- Fun 4
16#6d# => x"00", -- Fun 4
16#6e# => x"03", -- Fun 4
16#6f# => x"00", -- Fun 4
--XAMCAP
16#88# => x"00", -- Fun 0 XAMCAP MSB
16#a5# => x"06", -- Fun 0 XAMCAP=0x11
16#A7# => x"00",
16#108# => x"00", -- Fun 4 XAMCAP MSB
16#109# => x"06", -- Fun 4 XAMCAP=0x11
16#10a# => x"00", -- Fun 4
--...
--16#C6# => x"00", -- Fun 0 XAMCAP LSB
--16#C7# => x"01", -- Fun 0 XAMCAP LSB
--......
-- Address Decoder Mask ADEM
16#188# => x"00", -- Fun 0
16#189# => x"00", -- Fun 0
16#18A# => x"00", -- Fun 0
16#18B# => x"05", -- Fun 0
16#18c# => x"ff", -- Fun 1
16#18d# => x"ff", -- Fun 1
16#18e# => x"00", -- Fun 1
16#18f# => x"00", -- Fun 1
16#190# => x"00", -- Fun 2
16#191# => x"e0", -- Fun 2
16#192# => x"00", -- Fun 2
16#193# => x"00", -- Fun 2
16#194# => x"ff", -- Fun 3
16#195# => x"00", -- Fun 3
16#196# => x"00", -- Fun 3
16#197# => x"00", -- Fun 3
others => (others => '0'));
end VME_CR_pack;
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.numeric_std.all;
--type is array(BAR downto IRQ_level) of unsigned(7 downto 0);
use work.VME_pack.all;
package VME_CSR_pack is
constant c_csr_array : t_CSRarray :=
(
BAR => x"00", --CR/CSR BAR
BIT_SET_CLR_REG => x"00", --Bit set register
USR_BIT_SET_CLR_REG => x"00", --Bit clear register
CRAM_OWNER => x"00", --CRAM_OWNER
FUNC0_ADER_0 =>x"44",
FUNC0_ADER_1 =>x"00",
FUNC0_ADER_2 =>x"00",
FUNC0_ADER_3 =>x"00",
FUNC1_ADER_0 =>x"00",
FUNC1_ADER_1 =>x"00",
FUNC1_ADER_2 =>x"34",
FUNC1_ADER_3 =>x"12",
FUNC2_ADER_0 =>x"e4",
FUNC2_ADER_1 =>x"00",
FUNC2_ADER_2 =>x"80",
FUNC2_ADER_3 =>x"00",
FUNC3_ADER_0 =>x"24",
FUNC3_ADER_1 =>x"00",
FUNC3_ADER_2 =>x"00",
FUNC3_ADER_3 =>x"80",
FUNC4_ADER_0 =>x"44",
FUNC4_ADER_1 =>x"00",
FUNC4_ADER_2 =>x"00",
FUNC4_ADER_3 =>x"00",
FUNC5_ADER_0 =>x"00",
FUNC5_ADER_1 =>x"00",
FUNC5_ADER_2 =>x"34",
FUNC5_ADER_3 =>x"11",
others => (others => '0'));
-- constant BAR : integer := 255;
-- constant BIT_SET_CLR_REG : integer := 254;
-- constant USR_BIT_SET_CLR_REG : integer := 253;
-- constant CRAM_OWNER : integer := 252;
--
-- constant FUNC7_ADER_0 : integer := 251;
-- constant FUNC7_ADER_1 : integer := FUNC7_ADER_0 - 1;
-- constant FUNC7_ADER_2 : integer := FUNC7_ADER_0 - 2;
-- constant FUNC7_ADER_3 : integer := FUNC7_ADER_0 - 3;
-- constant FUNC6_ADER_0 : integer := FUNC7_ADER_0 - 4;
-- constant FUNC6_ADER_1 : integer := FUNC7_ADER_0 - 5;
-- constant FUNC6_ADER_2 : integer := FUNC7_ADER_0 - 6;
-- constant FUNC6_ADER_3 : integer := FUNC7_ADER_0 - 7;
-- constant FUNC5_ADER_0 : integer := FUNC7_ADER_0 - 8;
-- constant FUNC5_ADER_1 : integer := FUNC7_ADER_0 - 9;
-- constant FUNC5_ADER_2 : integer := FUNC7_ADER_0 - 10;
-- constant FUNC5_ADER_3 : integer := FUNC7_ADER_0 - 11;
-- constant FUNC4_ADER_0 : integer := FUNC7_ADER_0 - 12;
-- constant FUNC4_ADER_1 : integer := FUNC7_ADER_0 - 13;
-- constant FUNC4_ADER_2 : integer := FUNC7_ADER_0 - 14;
-- constant FUNC4_ADER_3 : integer := FUNC7_ADER_0 - 15;
-- constant FUNC3_ADER_0 : integer := FUNC7_ADER_0 - 16;
-- constant FUNC3_ADER_1 : integer := FUNC7_ADER_0 - 17;
-- constant FUNC3_ADER_2 : integer := FUNC7_ADER_0 - 18;
-- constant FUNC3_ADER_3 : integer := FUNC7_ADER_0 - 19;
-- constant FUNC2_ADER_0 : integer := FUNC7_ADER_0 - 20;
-- constant FUNC2_ADER_1 : integer := FUNC7_ADER_0 - 21;
-- constant FUNC2_ADER_2 : integer := FUNC7_ADER_0 - 22;
-- constant FUNC2_ADER_3 : integer := FUNC7_ADER_0 - 23;
-- constant FUNC1_ADER_0 : integer := FUNC7_ADER_0 - 24;
-- constant FUNC1_ADER_1 : integer := FUNC7_ADER_0 - 25;
-- constant FUNC1_ADER_2 : integer := FUNC7_ADER_0 - 26;
-- constant FUNC1_ADER_3 : integer := FUNC7_ADER_0 - 27;
-- constant FUNC0_ADER_0 : integer := FUNC7_ADER_0 - 28;
-- constant FUNC0_ADER_1 : integer := FUNC7_ADER_0 - 29;
-- constant FUNC0_ADER_2 : integer := FUNC7_ADER_0 - 30;
-- constant FUNC0_ADER_3 : integer := FUNC7_ADER_0 - 31;
end VME_CSR_pack;
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library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.numeric_std.all;
package VME_pack is
type t_reg52x8bit is array(51 downto 0) of unsigned(7 downto 0);
type t_reg52x12bit is array(51 downto 0) of unsigned(11 downto 0);
type t_cr_array is array (Natural range <>) of std_logic_vector(7 downto 0);
type t_rom_cell is
record
add : integer;
len : integer;
end record;
type t_cr_add_table is array (Natural range <>) of t_rom_cell;
constant c_A24 : std_logic_vector(5 downto 0) :="111001";
constant c_A24_S : std_logic_vector(5 downto 0) :="111101";
constant c_A24_BLT : std_logic_vector(5 downto 0) :="111111";
constant c_A24_MBLT : std_logic_vector(5 downto 0) :="111100";
constant c_A24_LCK : std_logic_vector(5 downto 0) :="110010";
constant c_CR_CSR : std_logic_vector(5 downto 0) :="101111";
constant c_A16 : std_logic_vector(5 downto 0) :="101101";
constant c_A16_LCK : std_logic_vector(5 downto 0) :="101100";
constant c_A32 : std_logic_vector(5 downto 0) :="001001";
constant c_A32_BLT : std_logic_vector(5 downto 0) :="001111";
constant c_A32_MBLT : std_logic_vector(5 downto 0) :="001100";
constant c_A32_LCK : std_logic_vector(5 downto 0) :="000101";
constant c_A64 : std_logic_vector(5 downto 0) :="000001";
constant c_A64_BLT : std_logic_vector(5 downto 0) :="000011";
constant c_A64_MBLT : std_logic_vector(5 downto 0) :="000000";
constant c_A64_LCK : std_logic_vector(5 downto 0) :="000100";
constant c_TWOedge : std_logic_vector(5 downto 0) :="100000";
constant c_cr_step : integer := 4;
constant BAR : integer := 255;
constant BIT_SET_CLR_REG : integer := 254;
constant USR_BIT_SET_CLR_REG : integer := 253;
constant CRAM_OWNER : integer := 252;
constant FUNC7_ADER_0 : integer := 251;
constant FUNC7_ADER_1 : integer := FUNC7_ADER_0 - 1;
constant FUNC7_ADER_2 : integer := FUNC7_ADER_0 - 2;
constant FUNC7_ADER_3 : integer := FUNC7_ADER_0 - 3;
constant FUNC6_ADER_0 : integer := FUNC7_ADER_0 - 4;
constant FUNC6_ADER_1 : integer := FUNC7_ADER_0 - 5;
constant FUNC6_ADER_2 : integer := FUNC7_ADER_0 - 6;
constant FUNC6_ADER_3 : integer := FUNC7_ADER_0 - 7;
constant FUNC5_ADER_0 : integer := FUNC7_ADER_0 - 8;
constant FUNC5_ADER_1 : integer := FUNC7_ADER_0 - 9;
constant FUNC5_ADER_2 : integer := FUNC7_ADER_0 - 10;
constant FUNC5_ADER_3 : integer := FUNC7_ADER_0 - 11;
constant FUNC4_ADER_0 : integer := FUNC7_ADER_0 - 12;
constant FUNC4_ADER_1 : integer := FUNC7_ADER_0 - 13;
constant FUNC4_ADER_2 : integer := FUNC7_ADER_0 - 14;
constant FUNC4_ADER_3 : integer := FUNC7_ADER_0 - 15;
constant FUNC3_ADER_0 : integer := FUNC7_ADER_0 - 16;
constant FUNC3_ADER_1 : integer := FUNC7_ADER_0 - 17;
constant FUNC3_ADER_2 : integer := FUNC7_ADER_0 - 18;
constant FUNC3_ADER_3 : integer := FUNC7_ADER_0 - 19;
constant FUNC2_ADER_0 : integer := FUNC7_ADER_0 - 20;
constant FUNC2_ADER_1 : integer := FUNC7_ADER_0 - 21;
constant FUNC2_ADER_2 : integer := FUNC7_ADER_0 - 22;
constant FUNC2_ADER_3 : integer := FUNC7_ADER_0 - 23;
constant FUNC1_ADER_0 : integer := FUNC7_ADER_0 - 24;
constant FUNC1_ADER_1 : integer := FUNC7_ADER_0 - 25;
constant FUNC1_ADER_2 : integer := FUNC7_ADER_0 - 26;
constant FUNC1_ADER_3 : integer := FUNC7_ADER_0 - 27;
constant FUNC0_ADER_0 : integer := FUNC7_ADER_0 - 28;
constant FUNC0_ADER_1 : integer := FUNC7_ADER_0 - 29;
constant FUNC0_ADER_2 : integer := FUNC7_ADER_0 - 30;
constant FUNC0_ADER_3 : integer := FUNC7_ADER_0 - 31;
constant IRQ_ID : integer := FUNC0_ADER_3 -1;
constant IRQ_level : integer := FUNC0_ADER_3 -2;
type t_CSRarray is array(BAR downto IRQ_level) of unsigned(7 downto 0);
----------------------------------
--Bit accronyms
constant DFS : integer := 2;
constant XAM_MODE : integer := 0;
--0x7FFFF CR/CSR (BAR) 1 byte VME64
-- Base Address Register
--0x7FFFB Bit Set Register 1 byte VME64
-- see Table 10-6
--0x7FFF7 Bit Clear Register 1 byte VME64
-- see Table 10-7
--0x7FFF3 CRAM_OWNER Register 1 byte VME64x
--0x7FFEF User-Defined Bit Set 1 byte VME64x
-- Register
--0x7FFEB User-Defined Bit Clear 1 byte VME64x
-- Register
--0x7FFE3 ... 0x7FFE7 RESERVED 2 bytes VME64x
--0x7FFD3 ... 0x7FFDF Function 7 ADER 4 bytes VME64x
-- see Table 10-8
--0x7FFC3 ... 0x7FFCF Function 6 ADER 4 bytes VME64x
--0x7FFB3 ... 0x7FFBF Function 5 ADER 4 bytes VME64x
--0x7FFA3 ... 0x7FFAF Function 4 ADER 4 bytes VME64x
--0x7FF93 ... 0x7FF9F Function 3 ADER 4 bytes VME64x
--0x7FF83 ... 0x7FF8F Function 2 ADER 4 bytes VME64x
--0x7FF73 ... 0x7FF7F Function 1 ADER 4 bytes VME64x
--0x7FF63 ... 0x7FF6F Function 0 ADER 4 bytes VME64x
--0x7FC00 ... 0x7FF5F RESERVED 216 bytes VME64x
--
-------------------
constant BAR_addr : integer := 16#7FFFF#;
constant BIT_SET_REG_addr : integer := 16#7FFFB#;
constant BIT_CLR_REG_addr : integer := 16#7FFF7#;
constant CRAM_OWNER_addr : integer := 16#7FFF3#;
constant USR_BIT_SET_REG_addr : integer := 16#7FFEF#;
constant USR_BIT_CLR_REG_addr : integer := 16#7FFEB#;
--Reserved 16#7FFE7#;
--Reserved 16#7FFE3#;
constant FUNC7_ADER_0_addr : integer := 16#7FFDF#;
constant FUNC7_ADER_1_addr : integer := 16#7FFDB#;
constant FUNC7_ADER_2_addr : integer := 16#7FFD7#;
constant FUNC7_ADER_3_addr : integer := 16#7FFD3#;
constant FUNC6_ADER_0_addr : integer := 16#7FFCF#;
constant FUNC6_ADER_1_addr : integer := 16#7FFCB#;
constant FUNC6_ADER_2_addr : integer := 16#7FFC7#;
constant FUNC6_ADER_3_addr : integer := 16#7FFC3#;
constant FUNC5_ADER_0_addr : integer := 16#7FFBF#;
constant FUNC5_ADER_1_addr : integer := 16#7FFBB#;
constant FUNC5_ADER_2_addr : integer := 16#7FFB7#;
constant FUNC5_ADER_3_addr : integer := 16#7FFB3#;
constant FUNC4_ADER_0_addr : integer := 16#7FFAF#;
constant FUNC4_ADER_1_addr : integer := 16#7FFAB#;
constant FUNC4_ADER_2_addr : integer := 16#7FFA7#;
constant FUNC4_ADER_3_addr : integer := 16#7FFA3#;
constant FUNC3_ADER_0_addr : integer := 16#7FF9F#;
constant FUNC3_ADER_1_addr : integer := 16#7FF9B#;
constant FUNC3_ADER_2_addr : integer := 16#7FF97#;
constant FUNC3_ADER_3_addr : integer := 16#7FF93#;
constant FUNC2_ADER_0_addr : integer := 16#7FF8F#;
constant FUNC2_ADER_1_addr : integer := 16#7FF8B#;
constant FUNC2_ADER_2_addr : integer := 16#7FF87#;
constant FUNC2_ADER_3_addr : integer := 16#7FF83#;
constant FUNC1_ADER_0_addr : integer := 16#7FF7F#;
constant FUNC1_ADER_1_addr : integer := 16#7FF7B#;
constant FUNC1_ADER_2_addr : integer := 16#7FF77#;
constant FUNC1_ADER_3_addr : integer := 16#7FF73#;
constant FUNC0_ADER_0_addr : integer := 16#7FF6F#;
constant FUNC0_ADER_1_addr : integer := 16#7FF6B#;
constant FUNC0_ADER_2_addr : integer := 16#7FF67#;
constant FUNC0_ADER_3_addr : integer := 16#7FF63#;
constant IRQ_ID_addr : integer := 16#7fbff#;
constant IRQ_level_addr : integer := 16#7fbef#;
----------------------------------
---------------------------------------------------------------------------
constant BEG_USER_CR: integer := 1;
constant END_USER_CR: integer := 2;
constant BEG_CRAM: integer := 3;
constant END_CRAM: integer := 4;
constant BEG_USER_CSR: integer := 5;
constant END_USER_CSR: integer := 6;
constant FUNC_AMCAP : integer := 7;
constant FUNC_XAMCAP : integer := 8;
constant FUNC_ADEM: integer := 9; -- 340
constant c_CRinitAddr: t_cr_add_table(BEG_USER_CR to FUNC_ADEM) := (
BEG_USER_CR => (add => 16#020#, len => 3),
END_USER_CR => (add => 16#023#, len => 3),
BEG_CRAM => (add => 16#26#, len => 3),
END_CRAM => (add => 16#29#, len => 3),
BEG_USER_CSR => (add => 16#02C#, len => 3),
END_USER_CSR => (add => 16#2F#, len => 3),
FUNC_AMCAP => (add => 16#048#, len => 64),
FUNC_XAMCAP => (add => 16#088#, len => 256),
FUNC_ADEM => (add => 16#188#, len => 32));
constant c_checksum_po : integer :=0;
constant c_length_of_rom_po : integer :=1;
constant c_csr_data_acc_width_po : integer :=2;
constant c_cr_space_specification_id_po : integer :=3;
constant c_ascii_c_po : integer :=4;
constant c_ascii_r_po : integer :=5;
constant c_manu_id_po : integer :=6;
constant c_board_id_po : integer :=7;
constant c_rev_id_po : integer :=8;
constant c_cus_ascii_po : integer :=9;
constant c_last_CR_pointer_po : integer := 9;
end VME_pack;
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-------------------------------------------------------------------------------
--
-- Title : WB_bus
-- Design : VME64xCore
-- Author : Pablo Alvarez
-- Company : CERN
--
-------------------------------------------------------------------------------
--
-- File : wb_dma.vhd
-- Generated : 25/02/2011
-- From : interface description file
--
-------------------------------------------------------------------------------
--
-- Description :
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.numeric_std.all;
use work.common_components.all;
entity wb_dma is
generic(c_dl : integer := 64;
c_al : integer := 64;
c_sell : integer := 8;
c_psizel : integer := 10);
port (
-- Common signals
clk_i : in std_logic;
reset_i : in std_logic;
transfer_done_o : out std_logic;
-- Slave WB with dma support
sl_dat_i : in std_logic_vector(c_dl -1 downto 0);
sl_dat_o : out std_logic_vector(c_dl -1 downto 0);
sl_adr_i : in std_logic_vector(c_al -1 downto 0);
sl_cyc_i : in std_logic;
sl_err_o : out std_logic;
sl_lock_i : in std_logic;
sl_rty_o : out std_logic;
sl_sel_i : in std_logic_vector(c_sell -1 downto 0);
sl_stb_i : in std_logic;
sl_ack_o : out std_logic;
sl_we_i : in std_logic;
sl_stall_o : out std_logic;
-- This signals are not WB compatible. Should be connected to 0 if not
-- used.
sl_psize_i : in std_logic_vector(c_psizel -1 downto 0);
-- sl_buff_access_i : in std_logic;
-- Master WB port to fabric
m_dat_i : in std_logic_vector(c_dl -1 downto 0);
m_dat_o : out std_logic_vector(c_dl -1 downto 0);
m_adr_o : out std_logic_vector(c_al -1 downto 0);
m_cyc_o : out std_logic;
m_err_i : in std_logic;
m_lock_o : out std_logic;
m_rty_i : in std_logic;
m_sel_o : out std_logic_vector(c_sell -1 downto 0);
m_stb_o : out std_logic;
m_ack_i : in std_logic;
m_we_o : out std_logic;
m_stall_i : in std_logic
);
end wb_dma;
architecture RTL of wb_dma is
signal ack_latched : std_logic;
begin
process(clk_i)
begin
if rising_edge(clk_i) then
if(sl_cyc_i = '1' and sl_stb_i = '1' and m_ack_i = '1') then
ack_latched <= '1';
elsif(sl_cyc_i = '0' or sl_stb_i = '0') then
ack_latched <= '0';
end if;
end if;
end process;
sl_stall_o <= m_stall_i;
m_we_o <= sl_we_i;
sl_ack_o <= m_ack_i;
m_stb_o <= sl_stb_i and not ack_latched;
m_sel_o <= sl_sel_i;
sl_rty_o <= '0';
sl_err_o <= '0';
m_adr_o <= sl_adr_i;
m_dat_o <= sl_dat_i;
sl_dat_o <= m_dat_i;
m_cyc_o <= sl_cyc_i;
end RTL;
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