Skip to content

F
FMC DEL 1ns 4cha
Commit a5b65f8f authored by Tomasz Wlostowski's avatar Tomasz Wlostowski
Browse files
Options

testbench/svec_wr_top: wip

parent 36d42326
Expand all Hide whitespace changes
Inline Side-by-side
Showing with 1091 additions and 18532 deletions
hdl/testbench/svec_wr_top/fdelay_board.svh
View file @ a5b65f8f
...@@ -197,21 +197,28 @@ module fdelay_board ( ...@@ -197,21 +197,28 @@ module fdelay_board (
); );
genvar gg; genvar gg;
function bit[9:0] reverse_bits (bit [9:0] x);
reg [9:0] tmp;
int i;
for(i=0;i<10;i++)
tmp[9-i]=x[i];
return tmp;
endfunction // reverse_bits
generate
for(gg=0;gg<4;gg++)
begin
// assign out_o[gg] = fmc.delay_pulse[gg];
mc100ep195 mc100ep195
U_delay_line( U_delay_line0(
.len(fmc.delay_len[gg]), .len(fmc.delay_len[0]),
.i(fmc.delay_pulse[gg]), .i(fmc.delay_pulse[0]),
.delay(fmc.delay_val), .delay(reverse_bits(fmc.delay_val)),
.o(out_o[gg]) .o(out_o[0]));
);
end
endgenerate
endmodule // main endmodule // main
......
hdl/testbench/svec_wr_top/main.sv
View file @ a5b65f8f
...@@ -43,6 +43,43 @@ module delay_meas(input enable, input a, input b); ...@@ -43,6 +43,43 @@ module delay_meas(input enable, input a, input b);
end end
endmodule // delay_meas endmodule // delay_meas
module period_meas(input enable, input a);
mailbox tag_a, tag_b;
event q_notempty;
initial begin
tag_a = new(1024);
end
time prev_a = 0;
always@(posedge a) begin
if(prev_a > 0)begin
if(enable) tag_a.put($time - prev_a);
end else
prev_a=$time;
end
initial forever begin
wait(tag_a.num() > 0);
while(tag_a.num() > 0)
begin
time delta;
tag_a.get(delta);
$display("Delay: %.3f ns", real'(delta) / real'(1ns) );
end
end
endmodule // delay_meas
module main; module main;
...@@ -85,7 +122,6 @@ module main; ...@@ -85,7 +122,6 @@ module main;
wire [3:0] out0, out1; wire [3:0] out0, out1;
reg pulse_enable = 0; reg pulse_enable = 0;
random_pulse_gen random_pulse_gen
#( #(
.g_pulse_width (50ns), .g_pulse_width (50ns),
...@@ -104,7 +140,12 @@ module main; ...@@ -104,7 +140,12 @@ module main;
.fmc(I_fmc0.board) .fmc(I_fmc0.board)
); );
delay_meas U_DMeas0 (pulse_enable, trig0, out0[0]); reg out0_delayed=0;
always@(out0[0]) out0_delayed <= #10ps out0[0];
period_meas U_DMeas0 (pulse_enable, out0[0]);
task automatic init_vme64x_core(ref CBusAccessor_VME64x acc); task automatic init_vme64x_core(ref CBusAccessor_VME64x acc);
/* map func0 to 0x80000000, A32 */ /* map func0 to 0x80000000, A32 */
...@@ -120,7 +161,7 @@ module main; ...@@ -120,7 +161,7 @@ module main;
initial begin initial begin
CBusAccessor_VME64x acc = new(VME.master); CBusAccessor_VME64x acc = new(VME.master);
CBusAccessor acc_casted = CBusAccessor'(acc); CBusAccessor acc_casted = CBusAccessor'(acc);
Timestamp dly; Timestamp dly, t_start;
CSimDrv_FineDelay drv0; CSimDrv_FineDelay drv0;
uint64_t d; uint64_t d;
...@@ -129,18 +170,34 @@ module main; ...@@ -129,18 +170,34 @@ module main;
init_vme64x_core(acc); init_vme64x_core(acc);
acc_casted.set_default_xfer_size(A32|SINGLE|D32); acc_casted.set_default_xfer_size(A32|SINGLE|D32);
// acc.read('h20000, d, D32|A32|SINGLE);
// $display("Vector 1 = %x", d);
acc.read('h80030080, d, D32|A32|SINGLE);
$display("Vector 0 = %x", d);
acc.read('h80030084, d, D32|A32|SINGLE);
$display("Vector 1 = %x", d);
acc.read('h80030088, d, D32|A32|SINGLE);
$display("Vector 2 = %x", d);
$stop;
drv0 = new(acc, 'h10000);
drv0 = new(acc, 'h80010000);
drv0.init(); drv0.init();
dly=new; t_start=new;
dly.from_ps(600000); drv0.get_time(t_start);
drv0.config_output(0, CSimDrv_FineDelay::DELAY, 1, dly, 200000); t_start.coarse += 2000;
drv0.config_output(0, CSimDrv_FineDelay::PULSE_GEN, 1, t_start, 200000, 1001000, -1);
$display("Init done"); $display("Init done");
pulse_enable = 1; pulse_enable = 1;
/* -----\/----- EXCLUDED -----\/-----
forever begin forever begin
drv0.rbuf_update(); drv0.rbuf_update();
...@@ -152,10 +209,13 @@ module main; ...@@ -152,10 +209,13 @@ module main;
end end
#1us; #1us;
end end
end -----/\----- EXCLUDED -----/\----- */
end // initial begin
endmodule // main endmodule // main
hdl/testbench/svec_wr_top/simdrv_fine_delay.svh
View file @ a5b65f8f
...@@ -177,7 +177,7 @@ class CSimDrv_FineDelay; ...@@ -177,7 +177,7 @@ class CSimDrv_FineDelay;
base = 'h100 + 'h100 * channel; base = 'h100 + 'h100 * channel;
writel(base + `ADDR_FD_FRR, 800); writel(base + `ADDR_FD_FRR, 865);
writel(base + `ADDR_FD_U_STARTH, t_start.utc >> 32); writel(base + `ADDR_FD_U_STARTH, t_start.utc >> 32);
writel(base + `ADDR_FD_U_STARTL, t_start.utc & 'hffffffff); writel(base + `ADDR_FD_U_STARTL, t_start.utc & 'hffffffff);
writel(base + `ADDR_FD_C_START, t_start.coarse); writel(base + `ADDR_FD_C_START, t_start.coarse);
......
hdl/testbench/svec_wr_top/wave.do
View file @ a5b65f8f
onerror {resume} onerror {resume}
quietly WaveActivateNextPane {} 0 quietly WaveActivateNextPane {} 0
add wave -noupdate /main/DUT/g_with_wr_phy
add wave -noupdate /main/DUT/g_simulation
add wave -noupdate /main/DUT/clk_20m_vcxo_i
add wave -noupdate /main/DUT/clk_125m_pllref_p_i
add wave -noupdate /main/DUT/clk_125m_pllref_n_i
add wave -noupdate /main/DUT/clk_125m_gtp_p_i
add wave -noupdate /main/DUT/clk_125m_gtp_n_i
add wave -noupdate /main/DUT/rst_n_i
add wave -noupdate /main/DUT/VME_AS_n_i
add wave -noupdate /main/DUT/VME_RST_n_i
add wave -noupdate /main/DUT/VME_WRITE_n_i
add wave -noupdate /main/DUT/VME_AM_i
add wave -noupdate /main/DUT/VME_DS_n_i
add wave -noupdate /main/DUT/VME_GA_i
add wave -noupdate /main/DUT/VME_BERR_o
add wave -noupdate /main/DUT/VME_DTACK_n_o
add wave -noupdate /main/DUT/VME_RETRY_n_o
add wave -noupdate /main/DUT/VME_RETRY_OE_o
add wave -noupdate /main/DUT/VME_LWORD_n_b
add wave -noupdate /main/DUT/VME_ADDR_b
add wave -noupdate /main/DUT/VME_DATA_b
add wave -noupdate /main/DUT/VME_BBSY_n_i
add wave -noupdate /main/DUT/VME_IRQ_n_o
add wave -noupdate /main/DUT/VME_IACK_n_i
add wave -noupdate /main/DUT/VME_IACKIN_n_i
add wave -noupdate /main/DUT/VME_IACKOUT_n_o
add wave -noupdate /main/DUT/VME_DTACK_OE_o
add wave -noupdate /main/DUT/VME_DATA_DIR_o
add wave -noupdate /main/DUT/VME_DATA_OE_N_o
add wave -noupdate /main/DUT/VME_ADDR_DIR_o
add wave -noupdate /main/DUT/VME_ADDR_OE_N_o
add wave -noupdate /main/DUT/sfp_txp_o
add wave -noupdate /main/DUT/sfp_txn_o
add wave -noupdate /main/DUT/sfp_rxp_i
add wave -noupdate /main/DUT/sfp_rxn_i
add wave -noupdate /main/DUT/sfp_mod_def0_b
add wave -noupdate /main/DUT/sfp_mod_def1_b
add wave -noupdate /main/DUT/sfp_mod_def2_b
add wave -noupdate /main/DUT/sfp_rate_select_b
add wave -noupdate /main/DUT/sfp_tx_fault_i
add wave -noupdate /main/DUT/sfp_tx_disable_o
add wave -noupdate /main/DUT/sfp_los_i
add wave -noupdate /main/DUT/fmc0_prsntm2c_n_i
add wave -noupdate /main/DUT/fmc1_prsntm2c_n_i
add wave -noupdate /main/DUT/fmc0_scl_b
add wave -noupdate /main/DUT/fmc0_sda_b
add wave -noupdate /main/DUT/fmc1_scl_b
add wave -noupdate /main/DUT/fmc1_sda_b
add wave -noupdate /main/DUT/pll20dac_din_o
add wave -noupdate /main/DUT/pll20dac_sclk_o
add wave -noupdate /main/DUT/pll20dac_sync_n_o
add wave -noupdate /main/DUT/pll25dac_din_o
add wave -noupdate /main/DUT/pll25dac_sclk_o
add wave -noupdate /main/DUT/pll25dac_sync_n_o
add wave -noupdate /main/DUT/tempid_dq_b
add wave -noupdate /main/DUT/fp_ledn_o
add wave -noupdate /main/DUT/fd0_tdc_start_p_i
add wave -noupdate /main/DUT/fd0_tdc_start_n_i
add wave -noupdate /main/DUT/fd0_clk_ref_p_i
add wave -noupdate /main/DUT/fd0_clk_ref_n_i
add wave -noupdate /main/DUT/fd0_trig_a_i
add wave -noupdate /main/DUT/fd0_tdc_cal_pulse_o
add wave -noupdate /main/DUT/fd0_tdc_d_b
add wave -noupdate /main/DUT/fd0_tdc_emptyf_i
add wave -noupdate /main/DUT/fd0_tdc_alutrigger_o
add wave -noupdate /main/DUT/fd0_tdc_wr_n_o
add wave -noupdate /main/DUT/fd0_tdc_rd_n_o
add wave -noupdate /main/DUT/fd0_tdc_oe_n_o
add wave -noupdate /main/DUT/fd0_led_trig_o
add wave -noupdate /main/DUT/fd0_tdc_start_dis_o
add wave -noupdate /main/DUT/fd0_tdc_stop_dis_o
add wave -noupdate /main/DUT/fd0_spi_cs_dac_n_o
add wave -noupdate /main/DUT/fd0_spi_cs_pll_n_o
add wave -noupdate /main/DUT/fd0_spi_cs_gpio_n_o
add wave -noupdate /main/DUT/fd0_spi_sclk_o
add wave -noupdate /main/DUT/fd0_spi_mosi_o
add wave -noupdate /main/DUT/fd0_spi_miso_i
add wave -noupdate /main/DUT/fd0_delay_len_o
add wave -noupdate /main/DUT/fd0_delay_val_o
add wave -noupdate /main/DUT/fd0_delay_pulse_o
add wave -noupdate /main/DUT/fd0_dmtd_clk_o
add wave -noupdate /main/DUT/fd0_dmtd_fb_in_i
add wave -noupdate /main/DUT/fd0_dmtd_fb_out_i
add wave -noupdate /main/DUT/fd0_pll_status_i
add wave -noupdate /main/DUT/fd0_ext_rst_n_o
add wave -noupdate /main/DUT/fd0_onewire_b
add wave -noupdate /main/DUT/fd1_tdc_start_p_i
add wave -noupdate /main/DUT/fd1_tdc_start_n_i
add wave -noupdate /main/DUT/fd1_clk_ref_p_i
add wave -noupdate /main/DUT/fd1_clk_ref_n_i
add wave -noupdate /main/DUT/fd1_trig_a_i
add wave -noupdate /main/DUT/fd1_tdc_cal_pulse_o
add wave -noupdate /main/DUT/fd1_tdc_d_b
add wave -noupdate /main/DUT/fd1_tdc_emptyf_i
add wave -noupdate /main/DUT/fd1_tdc_alutrigger_o
add wave -noupdate /main/DUT/fd1_tdc_wr_n_o
add wave -noupdate /main/DUT/fd1_tdc_rd_n_o
add wave -noupdate /main/DUT/fd1_tdc_oe_n_o
add wave -noupdate /main/DUT/fd1_led_trig_o
add wave -noupdate /main/DUT/fd1_tdc_start_dis_o
add wave -noupdate /main/DUT/fd1_tdc_stop_dis_o
add wave -noupdate /main/DUT/fd1_spi_cs_dac_n_o
add wave -noupdate /main/DUT/fd1_spi_cs_pll_n_o
add wave -noupdate /main/DUT/fd1_spi_cs_gpio_n_o
add wave -noupdate /main/DUT/fd1_spi_sclk_o
add wave -noupdate /main/DUT/fd1_spi_mosi_o
add wave -noupdate /main/DUT/fd1_spi_miso_i
add wave -noupdate /main/DUT/fd1_delay_len_o
add wave -noupdate /main/DUT/fd1_delay_val_o
add wave -noupdate /main/DUT/fd1_delay_pulse_o
add wave -noupdate /main/DUT/fd1_dmtd_clk_o
add wave -noupdate /main/DUT/fd1_dmtd_fb_in_i
add wave -noupdate /main/DUT/fd1_dmtd_fb_out_i
add wave -noupdate /main/DUT/fd1_pll_status_i
add wave -noupdate /main/DUT/fd1_ext_rst_n_o
add wave -noupdate /main/DUT/fd1_onewire_b
add wave -noupdate /main/DUT/uart_rxd_i
add wave -noupdate /main/DUT/uart_txd_o
add wave -noupdate /main/DUT/VME_DATA_b_out
add wave -noupdate /main/DUT/VME_ADDR_b_out
add wave -noupdate /main/DUT/VME_LWORD_n_b_out
add wave -noupdate /main/DUT/VME_DATA_DIR_int
add wave -noupdate /main/DUT/VME_ADDR_DIR_int
add wave -noupdate /main/DUT/dac_hpll_load_p1
add wave -noupdate /main/DUT/dac_dpll_load_p1
add wave -noupdate /main/DUT/dac_hpll_data
add wave -noupdate /main/DUT/dac_dpll_data
add wave -noupdate /main/DUT/phy_tx_data
add wave -noupdate /main/DUT/phy_tx_k
add wave -noupdate /main/DUT/phy_tx_disparity
add wave -noupdate /main/DUT/phy_tx_enc_err
add wave -noupdate /main/DUT/phy_rx_data
add wave -noupdate /main/DUT/phy_rx_rbclk
add wave -noupdate /main/DUT/phy_rx_k
add wave -noupdate /main/DUT/phy_rx_enc_err
add wave -noupdate /main/DUT/phy_rx_bitslide
add wave -noupdate /main/DUT/phy_rst
add wave -noupdate /main/DUT/phy_loopen
add wave -noupdate /main/DUT/cnx_master_out add wave -noupdate /main/DUT/cnx_master_out
add wave -noupdate /main/DUT/cnx_master_in add wave -noupdate /main/DUT/cnx_master_in
add wave -noupdate /main/DUT/cnx_slave_out add wave -noupdate /main/DUT/cnx_slave_out
add wave -noupdate /main/DUT/cnx_slave_in add wave -noupdate /main/DUT/cnx_slave_in
add wave -noupdate /main/DUT/dcm0_clk_ref_0
add wave -noupdate /main/DUT/dcm0_clk_ref_180
add wave -noupdate /main/DUT/fd0_tdc_start
add wave -noupdate /main/DUT/tdc0_data_out
add wave -noupdate /main/DUT/tdc0_data_in
add wave -noupdate /main/DUT/tdc0_data_oe
add wave -noupdate /main/DUT/dcm1_clk_ref_0
add wave -noupdate /main/DUT/dcm1_clk_ref_180
add wave -noupdate /main/DUT/fd1_tdc_start
add wave -noupdate /main/DUT/tdc1_data_out
add wave -noupdate /main/DUT/tdc1_data_in
add wave -noupdate /main/DUT/tdc1_data_oe
add wave -noupdate /main/DUT/tm_link_up
add wave -noupdate /main/DUT/tm_utc
add wave -noupdate /main/DUT/tm_cycles
add wave -noupdate /main/DUT/tm_time_valid
add wave -noupdate /main/DUT/tm0_clk_aux_lock_en
add wave -noupdate /main/DUT/tm0_clk_aux_locked
add wave -noupdate /main/DUT/tm1_clk_aux_lock_en
add wave -noupdate /main/DUT/tm1_clk_aux_locked
add wave -noupdate /main/DUT/tm_dac_value
add wave -noupdate /main/DUT/tm0_dac_wr
add wave -noupdate /main/DUT/tm1_dac_wr
add wave -noupdate /main/DUT/ddr0_pll_reset
add wave -noupdate /main/DUT/ddr0_pll_locked
add wave -noupdate /main/DUT/fd0_pll_status
add wave -noupdate /main/DUT/ddr1_pll_reset
add wave -noupdate /main/DUT/ddr1_pll_locked
add wave -noupdate /main/DUT/fd1_pll_status
add wave -noupdate /main/DUT/wrc_scl_out
add wave -noupdate /main/DUT/wrc_scl_in
add wave -noupdate /main/DUT/wrc_sda_out
add wave -noupdate /main/DUT/wrc_sda_in
add wave -noupdate /main/DUT/fd0_scl_out
add wave -noupdate /main/DUT/fd0_scl_in
add wave -noupdate /main/DUT/fd0_sda_out
add wave -noupdate /main/DUT/fd0_sda_in
add wave -noupdate /main/DUT/fd1_scl_out
add wave -noupdate /main/DUT/fd1_scl_in
add wave -noupdate /main/DUT/fd1_sda_out
add wave -noupdate /main/DUT/fd1_sda_in
add wave -noupdate /main/DUT/sfp_scl_out
add wave -noupdate /main/DUT/sfp_scl_in
add wave -noupdate /main/DUT/sfp_sda_out
add wave -noupdate /main/DUT/sfp_sda_in
add wave -noupdate /main/DUT/wrc_owr_en
add wave -noupdate /main/DUT/wrc_owr_in
add wave -noupdate /main/DUT/fd0_owr_en
add wave -noupdate /main/DUT/fd0_owr_in
add wave -noupdate /main/DUT/fd1_owr_en
add wave -noupdate /main/DUT/fd1_owr_in
add wave -noupdate /main/DUT/fd0_irq
add wave -noupdate /main/DUT/fd1_irq
add wave -noupdate /main/DUT/pllout_clk_sys
add wave -noupdate /main/DUT/pllout_clk_dmtd
add wave -noupdate /main/DUT/pllout_clk_fb_pllref
add wave -noupdate /main/DUT/pllout_clk_fb_dmtd
add wave -noupdate /main/DUT/clk_20m_vcxo_buf
add wave -noupdate /main/DUT/clk_125m_pllref
add wave -noupdate /main/DUT/clk_125m_gtp
add wave -noupdate /main/DUT/clk_sys
add wave -noupdate /main/DUT/clk_dmtd
add wave -noupdate /main/DUT/local_reset_n
add wave -noupdate /main/DUT/vme_master_out
add wave -noupdate /main/DUT/vme_master_in
add wave -noupdate /main/DUT/pins
add wave -noupdate /main/DUT/rst_n_a
add wave -noupdate /main/DUT/pps
add wave -noupdate /main/DUT/led_divider
add wave -noupdate /main/DUT/leds
add wave -noupdate /main/DUT/etherbone_rst_n
add wave -noupdate /main/DUT/etherbone_src_out
add wave -noupdate /main/DUT/etherbone_src_in
add wave -noupdate /main/DUT/etherbone_snk_out
add wave -noupdate /main/DUT/etherbone_snk_in
add wave -noupdate /main/DUT/etherbone_cfg_in
add wave -noupdate /main/DUT/etherbone_cfg_out
TreeUpdate [SetDefaultTree] TreeUpdate [SetDefaultTree]
WaveRestoreCursors {{Cursor 1} {23693000000 fs} 0} WaveRestoreCursors {{Cursor 1} {53004000000 fs} 0}
configure wave -namecolwidth 183 configure wave -namecolwidth 183
configure wave -valuecolwidth 100 configure wave -valuecolwidth 100
configure wave -justifyvalue left configure wave -justifyvalue left
...@@ -235,4 +20,4 @@ configure wave -griddelta 40 ...@@ -235,4 +20,4 @@ configure wave -griddelta 40
configure wave -timeline 0 configure wave -timeline 0
configure wave -timelineunits ns configure wave -timelineunits ns
update update
WaveRestoreZoom {2400011620 fs} {12618218340 fs} WaveRestoreZoom {0 fs} {226247193600 fs}
hdl/testbench/svec_wr_top/wrc-simulation.ram 0 → 100644
View file @ a5b65f8f
This diff is collapsed.
hdl/testbench/svec_wr_top/wrc.ram deleted 100644 → 0
View file @ 36d42326
This diff is collapsed.
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment