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FMC DEL 1ns 4cha
Commit a5b65f8f authored by Tomasz Wlostowski's avatar Tomasz Wlostowski
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testbench/svec_wr_top: wip

parent 36d42326
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Showing with 1091 additions and 18532 deletions
hdl/testbench/svec_wr_top/fdelay_board.svh
View file @ a5b65f8f
......@@ -197,21 +197,28 @@ module fdelay_board (
);
genvar gg;
function bit[9:0] reverse_bits (bit [9:0] x);
reg [9:0] tmp;
int i;
for(i=0;i<10;i++)
tmp[9-i]=x[i];
return tmp;
endfunction // reverse_bits
generate
for(gg=0;gg<4;gg++)
begin
// assign out_o[gg] = fmc.delay_pulse[gg];
mc100ep195
U_delay_line(
.len(fmc.delay_len[gg]),
.i(fmc.delay_pulse[gg]),
.delay(fmc.delay_val),
.o(out_o[gg])
);
end
endgenerate
mc100ep195
U_delay_line0(
.len(fmc.delay_len[0]),
.i(fmc.delay_pulse[0]),
.delay(reverse_bits(fmc.delay_val)),
.o(out_o[0]));
endmodule // main
......
hdl/testbench/svec_wr_top/main.sv
View file @ a5b65f8f
......@@ -43,6 +43,43 @@ module delay_meas(input enable, input a, input b);
end
endmodule // delay_meas
module period_meas(input enable, input a);
mailbox tag_a, tag_b;
event q_notempty;
initial begin
tag_a = new(1024);
end
time prev_a = 0;
always@(posedge a) begin
if(prev_a > 0)begin
if(enable) tag_a.put($time - prev_a);
end else
prev_a=$time;
end
initial forever begin
wait(tag_a.num() > 0);
while(tag_a.num() > 0)
begin
time delta;
tag_a.get(delta);
$display("Delay: %.3f ns", real'(delta) / real'(1ns) );
end
end
endmodule // delay_meas
module main;
......@@ -85,7 +122,6 @@ module main;
wire [3:0] out0, out1;
reg pulse_enable = 0;
random_pulse_gen
#(
.g_pulse_width (50ns),
......@@ -104,7 +140,12 @@ module main;
.fmc(I_fmc0.board)
);
delay_meas U_DMeas0 (pulse_enable, trig0, out0[0]);
reg out0_delayed=0;
always@(out0[0]) out0_delayed <= #10ps out0[0];
period_meas U_DMeas0 (pulse_enable, out0[0]);
task automatic init_vme64x_core(ref CBusAccessor_VME64x acc);
/* map func0 to 0x80000000, A32 */
......@@ -120,7 +161,7 @@ module main;
initial begin
CBusAccessor_VME64x acc = new(VME.master);
CBusAccessor acc_casted = CBusAccessor'(acc);
Timestamp dly;
Timestamp dly, t_start;
CSimDrv_FineDelay drv0;
uint64_t d;
......@@ -129,18 +170,34 @@ module main;
init_vme64x_core(acc);
acc_casted.set_default_xfer_size(A32|SINGLE|D32);
// acc.read('h20000, d, D32|A32|SINGLE);
// $display("Vector 1 = %x", d);
acc.read('h80030080, d, D32|A32|SINGLE);
$display("Vector 0 = %x", d);
acc.read('h80030084, d, D32|A32|SINGLE);
$display("Vector 1 = %x", d);
acc.read('h80030088, d, D32|A32|SINGLE);
$display("Vector 2 = %x", d);
$stop;
drv0 = new(acc, 'h10000);
drv0 = new(acc, 'h80010000);
drv0.init();
dly=new;
dly.from_ps(600000);
drv0.config_output(0, CSimDrv_FineDelay::DELAY, 1, dly, 200000);
t_start=new;
drv0.get_time(t_start);
t_start.coarse += 2000;
drv0.config_output(0, CSimDrv_FineDelay::PULSE_GEN, 1, t_start, 200000, 1001000, -1);
$display("Init done");
pulse_enable = 1;
/* -----\/----- EXCLUDED -----\/-----
forever begin
drv0.rbuf_update();
......@@ -152,10 +209,13 @@ module main;
end
#1us;
end
end
-----/\----- EXCLUDED -----/\----- */
end // initial begin
endmodule // main
hdl/testbench/svec_wr_top/simdrv_fine_delay.svh
View file @ a5b65f8f
......@@ -177,7 +177,7 @@ class CSimDrv_FineDelay;
base = 'h100 + 'h100 * channel;
writel(base + `ADDR_FD_FRR, 800);
writel(base + `ADDR_FD_FRR, 865);
writel(base + `ADDR_FD_U_STARTH, t_start.utc >> 32);
writel(base + `ADDR_FD_U_STARTL, t_start.utc & 'hffffffff);
writel(base + `ADDR_FD_C_START, t_start.coarse);
......
hdl/testbench/svec_wr_top/wave.do
View file @ a5b65f8f
onerror {resume}
quietly WaveActivateNextPane {} 0
add wave -noupdate /main/DUT/g_with_wr_phy
add wave -noupdate /main/DUT/g_simulation
add wave -noupdate /main/DUT/clk_20m_vcxo_i
add wave -noupdate /main/DUT/clk_125m_pllref_p_i
add wave -noupdate /main/DUT/clk_125m_pllref_n_i
add wave -noupdate /main/DUT/clk_125m_gtp_p_i
add wave -noupdate /main/DUT/clk_125m_gtp_n_i
add wave -noupdate /main/DUT/rst_n_i
add wave -noupdate /main/DUT/VME_AS_n_i
add wave -noupdate /main/DUT/VME_RST_n_i
add wave -noupdate /main/DUT/VME_WRITE_n_i
add wave -noupdate /main/DUT/VME_AM_i
add wave -noupdate /main/DUT/VME_DS_n_i
add wave -noupdate /main/DUT/VME_GA_i
add wave -noupdate /main/DUT/VME_BERR_o
add wave -noupdate /main/DUT/VME_DTACK_n_o
add wave -noupdate /main/DUT/VME_RETRY_n_o
add wave -noupdate /main/DUT/VME_RETRY_OE_o
add wave -noupdate /main/DUT/VME_LWORD_n_b
add wave -noupdate /main/DUT/VME_ADDR_b
add wave -noupdate /main/DUT/VME_DATA_b
add wave -noupdate /main/DUT/VME_BBSY_n_i
add wave -noupdate /main/DUT/VME_IRQ_n_o
add wave -noupdate /main/DUT/VME_IACK_n_i
add wave -noupdate /main/DUT/VME_IACKIN_n_i
add wave -noupdate /main/DUT/VME_IACKOUT_n_o
add wave -noupdate /main/DUT/VME_DTACK_OE_o
add wave -noupdate /main/DUT/VME_DATA_DIR_o
add wave -noupdate /main/DUT/VME_DATA_OE_N_o
add wave -noupdate /main/DUT/VME_ADDR_DIR_o
add wave -noupdate /main/DUT/VME_ADDR_OE_N_o
add wave -noupdate /main/DUT/sfp_txp_o
add wave -noupdate /main/DUT/sfp_txn_o
add wave -noupdate /main/DUT/sfp_rxp_i
add wave -noupdate /main/DUT/sfp_rxn_i
add wave -noupdate /main/DUT/sfp_mod_def0_b
add wave -noupdate /main/DUT/sfp_mod_def1_b
add wave -noupdate /main/DUT/sfp_mod_def2_b
add wave -noupdate /main/DUT/sfp_rate_select_b
add wave -noupdate /main/DUT/sfp_tx_fault_i
add wave -noupdate /main/DUT/sfp_tx_disable_o
add wave -noupdate /main/DUT/sfp_los_i
add wave -noupdate /main/DUT/fmc0_prsntm2c_n_i
add wave -noupdate /main/DUT/fmc1_prsntm2c_n_i
add wave -noupdate /main/DUT/fmc0_scl_b
add wave -noupdate /main/DUT/fmc0_sda_b
add wave -noupdate /main/DUT/fmc1_scl_b
add wave -noupdate /main/DUT/fmc1_sda_b
add wave -noupdate /main/DUT/pll20dac_din_o
add wave -noupdate /main/DUT/pll20dac_sclk_o
add wave -noupdate /main/DUT/pll20dac_sync_n_o
add wave -noupdate /main/DUT/pll25dac_din_o
add wave -noupdate /main/DUT/pll25dac_sclk_o
add wave -noupdate /main/DUT/pll25dac_sync_n_o
add wave -noupdate /main/DUT/tempid_dq_b
add wave -noupdate /main/DUT/fp_ledn_o
add wave -noupdate /main/DUT/fd0_tdc_start_p_i
add wave -noupdate /main/DUT/fd0_tdc_start_n_i
add wave -noupdate /main/DUT/fd0_clk_ref_p_i
add wave -noupdate /main/DUT/fd0_clk_ref_n_i
add wave -noupdate /main/DUT/fd0_trig_a_i
add wave -noupdate /main/DUT/fd0_tdc_cal_pulse_o
add wave -noupdate /main/DUT/fd0_tdc_d_b
add wave -noupdate /main/DUT/fd0_tdc_emptyf_i
add wave -noupdate /main/DUT/fd0_tdc_alutrigger_o
add wave -noupdate /main/DUT/fd0_tdc_wr_n_o
add wave -noupdate /main/DUT/fd0_tdc_rd_n_o
add wave -noupdate /main/DUT/fd0_tdc_oe_n_o
add wave -noupdate /main/DUT/fd0_led_trig_o
add wave -noupdate /main/DUT/fd0_tdc_start_dis_o
add wave -noupdate /main/DUT/fd0_tdc_stop_dis_o
add wave -noupdate /main/DUT/fd0_spi_cs_dac_n_o
add wave -noupdate /main/DUT/fd0_spi_cs_pll_n_o
add wave -noupdate /main/DUT/fd0_spi_cs_gpio_n_o
add wave -noupdate /main/DUT/fd0_spi_sclk_o
add wave -noupdate /main/DUT/fd0_spi_mosi_o
add wave -noupdate /main/DUT/fd0_spi_miso_i
add wave -noupdate /main/DUT/fd0_delay_len_o
add wave -noupdate /main/DUT/fd0_delay_val_o
add wave -noupdate /main/DUT/fd0_delay_pulse_o
add wave -noupdate /main/DUT/fd0_dmtd_clk_o
add wave -noupdate /main/DUT/fd0_dmtd_fb_in_i
add wave -noupdate /main/DUT/fd0_dmtd_fb_out_i
add wave -noupdate /main/DUT/fd0_pll_status_i
add wave -noupdate /main/DUT/fd0_ext_rst_n_o
add wave -noupdate /main/DUT/fd0_onewire_b
add wave -noupdate /main/DUT/fd1_tdc_start_p_i
add wave -noupdate /main/DUT/fd1_tdc_start_n_i
add wave -noupdate /main/DUT/fd1_clk_ref_p_i
add wave -noupdate /main/DUT/fd1_clk_ref_n_i
add wave -noupdate /main/DUT/fd1_trig_a_i
add wave -noupdate /main/DUT/fd1_tdc_cal_pulse_o
add wave -noupdate /main/DUT/fd1_tdc_d_b
add wave -noupdate /main/DUT/fd1_tdc_emptyf_i
add wave -noupdate /main/DUT/fd1_tdc_alutrigger_o
add wave -noupdate /main/DUT/fd1_tdc_wr_n_o
add wave -noupdate /main/DUT/fd1_tdc_rd_n_o
add wave -noupdate /main/DUT/fd1_tdc_oe_n_o
add wave -noupdate /main/DUT/fd1_led_trig_o
add wave -noupdate /main/DUT/fd1_tdc_start_dis_o
add wave -noupdate /main/DUT/fd1_tdc_stop_dis_o
add wave -noupdate /main/DUT/fd1_spi_cs_dac_n_o
add wave -noupdate /main/DUT/fd1_spi_cs_pll_n_o
add wave -noupdate /main/DUT/fd1_spi_cs_gpio_n_o
add wave -noupdate /main/DUT/fd1_spi_sclk_o
add wave -noupdate /main/DUT/fd1_spi_mosi_o
add wave -noupdate /main/DUT/fd1_spi_miso_i
add wave -noupdate /main/DUT/fd1_delay_len_o
add wave -noupdate /main/DUT/fd1_delay_val_o
add wave -noupdate /main/DUT/fd1_delay_pulse_o
add wave -noupdate /main/DUT/fd1_dmtd_clk_o
add wave -noupdate /main/DUT/fd1_dmtd_fb_in_i
add wave -noupdate /main/DUT/fd1_dmtd_fb_out_i
add wave -noupdate /main/DUT/fd1_pll_status_i
add wave -noupdate /main/DUT/fd1_ext_rst_n_o
add wave -noupdate /main/DUT/fd1_onewire_b
add wave -noupdate /main/DUT/uart_rxd_i
add wave -noupdate /main/DUT/uart_txd_o
add wave -noupdate /main/DUT/VME_DATA_b_out
add wave -noupdate /main/DUT/VME_ADDR_b_out
add wave -noupdate /main/DUT/VME_LWORD_n_b_out
add wave -noupdate /main/DUT/VME_DATA_DIR_int
add wave -noupdate /main/DUT/VME_ADDR_DIR_int
add wave -noupdate /main/DUT/dac_hpll_load_p1
add wave -noupdate /main/DUT/dac_dpll_load_p1
add wave -noupdate /main/DUT/dac_hpll_data
add wave -noupdate /main/DUT/dac_dpll_data
add wave -noupdate /main/DUT/phy_tx_data
add wave -noupdate /main/DUT/phy_tx_k
add wave -noupdate /main/DUT/phy_tx_disparity
add wave -noupdate /main/DUT/phy_tx_enc_err
add wave -noupdate /main/DUT/phy_rx_data
add wave -noupdate /main/DUT/phy_rx_rbclk
add wave -noupdate /main/DUT/phy_rx_k
add wave -noupdate /main/DUT/phy_rx_enc_err
add wave -noupdate /main/DUT/phy_rx_bitslide
add wave -noupdate /main/DUT/phy_rst
add wave -noupdate /main/DUT/phy_loopen
add wave -noupdate /main/DUT/cnx_master_out
add wave -noupdate /main/DUT/cnx_master_in
add wave -noupdate /main/DUT/cnx_slave_out
add wave -noupdate /main/DUT/cnx_slave_in
add wave -noupdate /main/DUT/dcm0_clk_ref_0
add wave -noupdate /main/DUT/dcm0_clk_ref_180
add wave -noupdate /main/DUT/fd0_tdc_start
add wave -noupdate /main/DUT/tdc0_data_out
add wave -noupdate /main/DUT/tdc0_data_in
add wave -noupdate /main/DUT/tdc0_data_oe
add wave -noupdate /main/DUT/dcm1_clk_ref_0
add wave -noupdate /main/DUT/dcm1_clk_ref_180
add wave -noupdate /main/DUT/fd1_tdc_start
add wave -noupdate /main/DUT/tdc1_data_out
add wave -noupdate /main/DUT/tdc1_data_in
add wave -noupdate /main/DUT/tdc1_data_oe
add wave -noupdate /main/DUT/tm_link_up
add wave -noupdate /main/DUT/tm_utc
add wave -noupdate /main/DUT/tm_cycles
add wave -noupdate /main/DUT/tm_time_valid
add wave -noupdate /main/DUT/tm0_clk_aux_lock_en
add wave -noupdate /main/DUT/tm0_clk_aux_locked
add wave -noupdate /main/DUT/tm1_clk_aux_lock_en
add wave -noupdate /main/DUT/tm1_clk_aux_locked
add wave -noupdate /main/DUT/tm_dac_value
add wave -noupdate /main/DUT/tm0_dac_wr
add wave -noupdate /main/DUT/tm1_dac_wr
add wave -noupdate /main/DUT/ddr0_pll_reset
add wave -noupdate /main/DUT/ddr0_pll_locked
add wave -noupdate /main/DUT/fd0_pll_status
add wave -noupdate /main/DUT/ddr1_pll_reset
add wave -noupdate /main/DUT/ddr1_pll_locked
add wave -noupdate /main/DUT/fd1_pll_status
add wave -noupdate /main/DUT/wrc_scl_out
add wave -noupdate /main/DUT/wrc_scl_in
add wave -noupdate /main/DUT/wrc_sda_out
add wave -noupdate /main/DUT/wrc_sda_in
add wave -noupdate /main/DUT/fd0_scl_out
add wave -noupdate /main/DUT/fd0_scl_in
add wave -noupdate /main/DUT/fd0_sda_out
add wave -noupdate /main/DUT/fd0_sda_in
add wave -noupdate /main/DUT/fd1_scl_out
add wave -noupdate /main/DUT/fd1_scl_in
add wave -noupdate /main/DUT/fd1_sda_out
add wave -noupdate /main/DUT/fd1_sda_in
add wave -noupdate /main/DUT/sfp_scl_out
add wave -noupdate /main/DUT/sfp_scl_in
add wave -noupdate /main/DUT/sfp_sda_out
add wave -noupdate /main/DUT/sfp_sda_in
add wave -noupdate /main/DUT/wrc_owr_en
add wave -noupdate /main/DUT/wrc_owr_in
add wave -noupdate /main/DUT/fd0_owr_en
add wave -noupdate /main/DUT/fd0_owr_in
add wave -noupdate /main/DUT/fd1_owr_en
add wave -noupdate /main/DUT/fd1_owr_in
add wave -noupdate /main/DUT/fd0_irq
add wave -noupdate /main/DUT/fd1_irq
add wave -noupdate /main/DUT/pllout_clk_sys
add wave -noupdate /main/DUT/pllout_clk_dmtd
add wave -noupdate /main/DUT/pllout_clk_fb_pllref
add wave -noupdate /main/DUT/pllout_clk_fb_dmtd
add wave -noupdate /main/DUT/clk_20m_vcxo_buf
add wave -noupdate /main/DUT/clk_125m_pllref
add wave -noupdate /main/DUT/clk_125m_gtp
add wave -noupdate /main/DUT/clk_sys
add wave -noupdate /main/DUT/clk_dmtd
add wave -noupdate /main/DUT/local_reset_n
add wave -noupdate /main/DUT/vme_master_out
add wave -noupdate /main/DUT/vme_master_in
add wave -noupdate /main/DUT/pins
add wave -noupdate /main/DUT/rst_n_a
add wave -noupdate /main/DUT/pps
add wave -noupdate /main/DUT/led_divider
add wave -noupdate /main/DUT/leds
add wave -noupdate /main/DUT/etherbone_rst_n
add wave -noupdate /main/DUT/etherbone_src_out
add wave -noupdate /main/DUT/etherbone_src_in
add wave -noupdate /main/DUT/etherbone_snk_out
add wave -noupdate /main/DUT/etherbone_snk_in
add wave -noupdate /main/DUT/etherbone_cfg_in
add wave -noupdate /main/DUT/etherbone_cfg_out
TreeUpdate [SetDefaultTree]
WaveRestoreCursors {{Cursor 1} {23693000000 fs} 0}
WaveRestoreCursors {{Cursor 1} {53004000000 fs} 0}
configure wave -namecolwidth 183
configure wave -valuecolwidth 100
configure wave -justifyvalue left
......@@ -235,4 +20,4 @@ configure wave -griddelta 40
configure wave -timeline 0
configure wave -timelineunits ns
update
WaveRestoreZoom {2400011620 fs} {12618218340 fs}
WaveRestoreZoom {0 fs} {226247193600 fs}
hdl/testbench/svec_wr_top/wrc-simulation.ram 0 → 100644
View file @ a5b65f8f
write 0 98000000
write 1 D0000000
write 2 D0200000
write 3 78010000
write 4 38210000
write 5 D0E10000
write 6 98000000
write 7 781C0000
write 8 3B9C0FFC
write 9 781A0000
write a 3B5A8160
write b F800001F
write c 78030000
write d 3863013C
write e 28610000
write f 3802C49C
write 10 58220004
write 11 C3A00000
write 12 78030000
write 13 3863013C
write 14 28620000
write 15 28430000
write 16 20630001
write 17 5C60FFFE
write 18 78030000
write 19 3863013C
write 1a 28620000
write 1b 58410008
write 1c C3A00000
write 1d 379CFFF8
write 1e 5B8B0008
write 1f 5B9D0004
write 20 B8205800
write 21 E0000002
write 22 FBFFFFF0
write 23 41610000
write 24 356B0001
write 25 5C20FFFD
write 26 2B9D0004
write 27 2B8B0008
write 28 379C0008
write 29 C3A00000
write 2a 379CFFFC
write 2b 5B9D0004
write 2c 78020000
write 2d 38420140
write 2e 28410000
write 2f 78030000
write 30 34020012
write 31 38630144
write 32 58220000
write 33 28620000
write 34 78030000
write 35 38630148
write 36 58400000
write 37 28620000
write 38 78030000
write 39 3863014C
write 3a 58400000
write 3b 28620000
write 3c 58400000
write 3d 34020000
write 3e 38430008
write 3f 58230000
write 40 78030000
write 41 38630150
write 42 58220000
write 43 28610000
write 44 78030000
write 45 34020004
write 46 3863013C
write 47 58220000
write 48 28610000
write 49 3802C49C
write 4a 58220004
write 4b 78010000
write 4c 38210154
write 4d FBFFFFD0
write 4e E0000000
write 4f 00020500
write 50 00020300
write 51 00020314
write 52 00020318
write 53 00020310
write 54 0002031C
write 55 54686520
write 56 57522043
write 57 6F726520
write 58 73617973
write 59 2068656C
write 5a 6C6F210A
write 5b 00000000
write 5c 00000000
write 5d 00000000
write 5e 00000000
write 5f 00000000
write 60 00000000
write 61 00000000
write 62 00000000
write 63 00000000
write 64 00000000
write 65 00000000
write 66 00000000
write 67 00000000
write 68 00000000
write 69 00000000
write 6a 00000000
write 6b 00000000
write 6c 00000000
write 6d 00000000
write 6e 00000000
write 6f 00000000
write 70 00000000
write 71 00000000
write 72 00000000
write 73 00000000
write 74 00000000
write 75 00000000
write 76 00000000
write 77 00000000
write 78 00000000
write 79 00000000
write 7a 00000000
write 7b 00000000
write 7c 00000000
write 7d 00000000
write 7e 00000000
write 7f 00000000
write 80 00000000
write 81 00000000
write 82 00000000
write 83 00000000
write 84 00000000
write 85 00000000
write 86 00000000
write 87 00000000
write 88 00000000
write 89 00000000
write 8a 00000000
write 8b 00000000
write 8c 00000000
write 8d 00000000
write 8e 00000000
write 8f 00000000
write 90 00000000
write 91 00000000
write 92 00000000
write 93 00000000
write 94 00000000
write 95 00000000
write 96 00000000
write 97 00000000
write 98 00000000
write 99 00000000
write 9a 00000000
write 9b 00000000
write 9c 00000000
write 9d 00000000
write 9e 00000000
write 9f 00000000
write a0 00000000
write a1 00000000
write a2 00000000
write a3 00000000
write a4 00000000
write a5 00000000
write a6 00000000
write a7 00000000
write a8 00000000
write a9 00000000
write aa 00000000
write ab 00000000
write ac 00000000
write ad 00000000
write ae 00000000
write af 00000000
write b0 00000000
write b1 00000000
write b2 00000000
write b3 00000000
write b4 00000000
write b5 00000000
write b6 00000000
write b7 00000000
write b8 00000000
write b9 00000000
write ba 00000000
write bb 00000000
write bc 00000000
write bd 00000000
write be 00000000
write bf 00000000
write c0 00000000
write c1 00000000
write c2 00000000
write c3 00000000
write c4 00000000
write c5 00000000
write c6 00000000
write c7 00000000
write c8 00000000
write c9 00000000
write ca 00000000
write cb 00000000
write cc 00000000
write cd 00000000
write ce 00000000
write cf 00000000
write d0 00000000
write d1 00000000
write d2 00000000
write d3 00000000
write d4 00000000
write d5 00000000
write d6 00000000
write d7 00000000
write d8 00000000
write d9 00000000
write da 00000000
write db 00000000
write dc 00000000
write dd 00000000
write de 00000000
write df 00000000
write e0 00000000
write e1 00000000
write e2 00000000
write e3 00000000
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hdl/testbench/svec_wr_top/wrc.ram deleted 100644 → 0
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