Commit a3f68b19 authored by Tomasz Wlostowski's avatar Tomasz Wlostowski

fd_wbgen2_pkg: re-generated registers record

parent b2ff08f1
---------------------------------------------------------------------------------------
-- Title : Wishbone slave core for Fine Delay WB
-- Title : Wishbone slave core for Fine Delay Wishbone slave
---------------------------------------------------------------------------------------
-- File : fd_registers_pkg.vhd
-- Author : auto-generated by wbgen2 from fine_delay_wb.wb
-- Created : Mon May 30 19:41:22 2011
-- File : fd_wbgen2_pkg.vhd
-- Author : auto-generated by wbgen2 from fd_wishbone_slave.wb
-- Created : Wed Aug 31 11:09:47 2011
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE fine_delay_wb.wb
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE fd_wishbone_slave.wb
-- DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
---------------------------------------------------------------------------------------
......@@ -21,7 +21,9 @@ package fd_wbgen2_pkg is
rstr_wr_o : std_logic;
gcr_bypass_o : std_logic;
gcr_input_en_o : std_logic;
gcr_clr_stat_o : std_logic;
gcr_csync_int_o : std_logic;
gcr_csync_wr_o : std_logic;
gcr_wr_ready_i : std_logic;
tar_data_o : std_logic_vector(27 downto 0);
tar_data_i : std_logic_vector(27 downto 0);
tar_data_load_o : std_logic;
......@@ -36,9 +38,10 @@ package fd_wbgen2_pkg is
tdcsr_start_en_o : std_logic;
tdcsr_stop_dis_o : std_logic;
tdcsr_stop_en_o : std_logic;
dcr_dly_sel_o : std_logic_vector(3 downto 0);
dcr_dly_sel_wr_o : std_logic;
dcr_dly_val_o : std_logic_vector(9 downto 0);
adsfr_o : std_logic_vector(17 downto 0);
atmcr_c_thr_o : std_logic_vector(3 downto 0);
atmcr_f_thr_o : std_logic_vector(22 downto 0);
asor_offset_o : std_logic_vector(22 downto 0);
gpsr_cs_pll_o : std_logic;
gpsr_cs_pll_wr_o : std_logic;
gpsr_cs_gpio_o : std_logic;
......@@ -58,15 +61,88 @@ package fd_wbgen2_pkg is
gprr_miso_i : std_logic;
iecraw_i : std_logic_vector(31 downto 0);
iectag_i : std_logic_vector(31 downto 0);
iepd_i : std_logic_vector(7 downto 0);
pgcr_period_o : std_logic_vector(30 downto 0);
pgcr_enable_o : std_logic;
tsfifo_wr_req_i : std_logic;
tsfifo_wr_full_o : std_logic;
tsfifo_utc_i : std_logic_vector(31 downto 0);
tsfifo_coarse_i : std_logic_vector(27 downto 0);
tsfifo_frac_i : std_logic_vector(22 downto 0);
tsfifo_frac_raw_i : std_logic_vector(22 downto 0);
iepd_rst_stat_o : std_logic;
iepd_pdelay_i : std_logic_vector(7 downto 0);
vtr_dac_val_o : std_logic_vector(15 downto 0);
vtr_dac_val_wr_o : std_logic;
vtr_dac_rdy_i : std_logic;
tsbcr_enable_o : std_logic;
tsbcr_purge_o : std_logic;
tsbcr_rst_seq_o : std_logic;
tsbcr_full_i : std_logic;
tsbcr_empty_i : std_logic;
tsbr_u_i : std_logic_vector(31 downto 0);
tsbr_c_i : std_logic_vector(27 downto 0);
tsbr_fid_fine_i : std_logic_vector(11 downto 0);
tsbr_fid_seqid_i : std_logic_vector(15 downto 0);
dcr1_mode_dly_o : std_logic;
dcr1_mode_pg_o : std_logic;
dcr1_pg_arm_o : std_logic;
dcr1_pg_arm_i : std_logic;
dcr1_pg_arm_load_o : std_logic;
dcr1_pg_trig_i : std_logic;
dcr1_update_o : std_logic;
dcr1_upd_done_i : std_logic;
dcr1_force_cp_o : std_logic;
dcr1_pol_o : std_logic;
frr1_o : std_logic_vector(9 downto 0);
u_start1_o : std_logic_vector(31 downto 0);
c_start1_o : std_logic_vector(27 downto 0);
f_start1_o : std_logic_vector(9 downto 0);
u_end1_o : std_logic_vector(31 downto 0);
c_end1_o : std_logic_vector(27 downto 0);
f_end1_o : std_logic_vector(9 downto 0);
dcr2_mode_dly_o : std_logic;
dcr2_mode_pg_o : std_logic;
dcr2_pg_arm_o : std_logic;
dcr2_pg_arm_i : std_logic;
dcr2_pg_arm_load_o : std_logic;
dcr2_pg_trig_i : std_logic;
dcr2_update_o : std_logic;
dcr2_upd_done_i : std_logic;
dcr2_force_cp_o : std_logic;
dcr2_pol_o : std_logic;
frr2_o : std_logic_vector(9 downto 0);
u_start2_o : std_logic_vector(31 downto 0);
c_start2_o : std_logic_vector(27 downto 0);
f_start2_o : std_logic_vector(9 downto 0);
u_end2_o : std_logic_vector(31 downto 0);
c_end2_o : std_logic_vector(27 downto 0);
f_end2_o : std_logic_vector(9 downto 0);
dcr3_mode_dly_o : std_logic;
dcr3_mode_pg_o : std_logic;
dcr3_pg_arm_o : std_logic;
dcr3_pg_arm_i : std_logic;
dcr3_pg_arm_load_o : std_logic;
dcr3_pg_trig_i : std_logic;
dcr3_update_o : std_logic;
dcr3_upd_done_i : std_logic;
dcr3_force_cp_o : std_logic;
dcr3_pol_o : std_logic;
frr3_o : std_logic_vector(9 downto 0);
u_start3_o : std_logic_vector(31 downto 0);
c_start3_o : std_logic_vector(27 downto 0);
f_start3_o : std_logic_vector(9 downto 0);
u_end3_o : std_logic_vector(31 downto 0);
c_end3_o : std_logic_vector(27 downto 0);
f_end3_o : std_logic_vector(9 downto 0);
dcr4_mode_dly_o : std_logic;
dcr4_mode_pg_o : std_logic;
dcr4_pg_arm_o : std_logic;
dcr4_pg_arm_i : std_logic;
dcr4_pg_arm_load_o : std_logic;
dcr4_pg_trig_i : std_logic;
dcr4_update_o : std_logic;
dcr4_upd_done_i : std_logic;
dcr4_force_cp_o : std_logic;
dcr4_pol_o : std_logic;
frr4_o : std_logic_vector(9 downto 0);
u_start4_o : std_logic_vector(31 downto 0);
c_start4_o : std_logic_vector(27 downto 0);
f_start4_o : std_logic_vector(9 downto 0);
u_end4_o : std_logic_vector(31 downto 0);
c_end4_o : std_logic_vector(27 downto 0);
f_end4_o : std_logic_vector(9 downto 0);
end record;
constant c_fd_registers_init_value: t_fd_registers := (
......@@ -74,7 +150,9 @@ package fd_wbgen2_pkg is
rstr_wr_o => 'Z',
gcr_bypass_o => 'Z',
gcr_input_en_o => 'Z',
gcr_clr_stat_o => 'Z',
gcr_csync_int_o => 'Z',
gcr_csync_wr_o => 'Z',
gcr_wr_ready_i => 'Z',
tar_data_o => (others => 'Z'),
tar_data_i => (others => 'Z'),
tar_data_load_o => 'Z',
......@@ -89,9 +167,10 @@ package fd_wbgen2_pkg is
tdcsr_start_en_o => 'Z',
tdcsr_stop_dis_o => 'Z',
tdcsr_stop_en_o => 'Z',
dcr_dly_sel_o => (others => 'Z'),
dcr_dly_sel_wr_o => 'Z',
dcr_dly_val_o => (others => 'Z'),
adsfr_o => (others => 'Z'),
atmcr_c_thr_o => (others => 'Z'),
atmcr_f_thr_o => (others => 'Z'),
asor_offset_o => (others => 'Z'),
gpsr_cs_pll_o => 'Z',
gpsr_cs_pll_wr_o => 'Z',
gpsr_cs_gpio_o => 'Z',
......@@ -111,14 +190,87 @@ package fd_wbgen2_pkg is
gprr_miso_i => 'Z',
iecraw_i => (others => 'Z'),
iectag_i => (others => 'Z'),
iepd_i => (others => 'Z'),
pgcr_period_o => (others => 'Z'),
pgcr_enable_o => 'Z',
tsfifo_wr_req_i => 'Z',
tsfifo_wr_full_o => 'Z',
tsfifo_utc_i => (others => 'Z'),
tsfifo_coarse_i => (others => 'Z'),
tsfifo_frac_i => (others => 'Z'),
tsfifo_frac_raw_i => (others => 'Z')
iepd_rst_stat_o => 'Z',
iepd_pdelay_i => (others => 'Z'),
vtr_dac_val_o => (others => 'Z'),
vtr_dac_val_wr_o => 'Z',
vtr_dac_rdy_i => 'Z',
tsbcr_enable_o => 'Z',
tsbcr_purge_o => 'Z',
tsbcr_rst_seq_o => 'Z',
tsbcr_full_i => 'Z',
tsbcr_empty_i => 'Z',
tsbr_u_i => (others => 'Z'),
tsbr_c_i => (others => 'Z'),
tsbr_fid_fine_i => (others => 'Z'),
tsbr_fid_seqid_i => (others => 'Z'),
dcr1_mode_dly_o => 'Z',
dcr1_mode_pg_o => 'Z',
dcr1_pg_arm_o => 'Z',
dcr1_pg_arm_i => 'Z',
dcr1_pg_arm_load_o => 'Z',
dcr1_pg_trig_i => 'Z',
dcr1_update_o => 'Z',
dcr1_upd_done_i => 'Z',
dcr1_force_cp_o => 'Z',
dcr1_pol_o => 'Z',
frr1_o => (others => 'Z'),
u_start1_o => (others => 'Z'),
c_start1_o => (others => 'Z'),
f_start1_o => (others => 'Z'),
u_end1_o => (others => 'Z'),
c_end1_o => (others => 'Z'),
f_end1_o => (others => 'Z'),
dcr2_mode_dly_o => 'Z',
dcr2_mode_pg_o => 'Z',
dcr2_pg_arm_o => 'Z',
dcr2_pg_arm_i => 'Z',
dcr2_pg_arm_load_o => 'Z',
dcr2_pg_trig_i => 'Z',
dcr2_update_o => 'Z',
dcr2_upd_done_i => 'Z',
dcr2_force_cp_o => 'Z',
dcr2_pol_o => 'Z',
frr2_o => (others => 'Z'),
u_start2_o => (others => 'Z'),
c_start2_o => (others => 'Z'),
f_start2_o => (others => 'Z'),
u_end2_o => (others => 'Z'),
c_end2_o => (others => 'Z'),
f_end2_o => (others => 'Z'),
dcr3_mode_dly_o => 'Z',
dcr3_mode_pg_o => 'Z',
dcr3_pg_arm_o => 'Z',
dcr3_pg_arm_i => 'Z',
dcr3_pg_arm_load_o => 'Z',
dcr3_pg_trig_i => 'Z',
dcr3_update_o => 'Z',
dcr3_upd_done_i => 'Z',
dcr3_force_cp_o => 'Z',
dcr3_pol_o => 'Z',
frr3_o => (others => 'Z'),
u_start3_o => (others => 'Z'),
c_start3_o => (others => 'Z'),
f_start3_o => (others => 'Z'),
u_end3_o => (others => 'Z'),
c_end3_o => (others => 'Z'),
f_end3_o => (others => 'Z'),
dcr4_mode_dly_o => 'Z',
dcr4_mode_pg_o => 'Z',
dcr4_pg_arm_o => 'Z',
dcr4_pg_arm_i => 'Z',
dcr4_pg_arm_load_o => 'Z',
dcr4_pg_trig_i => 'Z',
dcr4_update_o => 'Z',
dcr4_upd_done_i => 'Z',
dcr4_force_cp_o => 'Z',
dcr4_pol_o => 'Z',
frr4_o => (others => 'Z'),
u_start4_o => (others => 'Z'),
c_start4_o => (others => 'Z'),
f_start4_o => (others => 'Z'),
u_end4_o => (others => 'Z'),
c_end4_o => (others => 'Z'),
f_end4_o => (others => 'Z')
);
end package;
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