Commit a3b85f12 authored by Federico Vaga's avatar Federico Vaga

Merge branch 'master' into develop

parents 531aecec 0bc3433c
......@@ -6,6 +6,21 @@
Changelog
=========
3.0.4 - 2020-12-11
==================
Changed
-------
- hdl: include fixes from SPEC and SVEC
Added
-----
- sw: add symlink to FMC slot in sysfs
Fixed
-----
- sw: IPMI header
- tst: timeout computation was wrong in some cases and very very long
3.0.3 - 2020-10-07
==================
......
modules = {
"local" : [
"hdl/rtl",
"hdl/platform",
],
}
Subproject commit 64f7e518bab2bf0489077f4b9eb26e8cccbf1411
Subproject commit 347e0de1e0d91834d298a146569530b71adeb33a
Subproject commit 91d5eface7608d306991d2c1aa4e6f5210e9305c
Subproject commit 461b30fe1f5e4e0c99f2265cdbf5843d31e31a4b
Subproject commit cd98b2689091a44726e64ec3e0bad4bf948e0078
Subproject commit fd485c8b31b50a681f1a72504f6969384cfb1d4f
Subproject commit 1b803764d842462233fb479d4cc0aa5418a9109f
Subproject commit 7afd1ca9d7413b360f96ebacf6d976f13cadebe1
Subproject commit a72a4223e2e1b521ba839f5623ee2857cf4fae10
Subproject commit dedbf24144915a9c5107027958516ea597ba0086
......@@ -19,7 +19,3 @@ files = ["fd_acam_timestamper.vhd",
"fd_dmtd_with_deglitcher.vhd"
];
fetchto = "../ip_cores"
modules = { "git" : [ "git@ohwr.org:hdl-core-lib/general-cores.git::master"] }
......@@ -6,7 +6,7 @@
-- Author : Tomasz Wlostowski
-- Company : CERN
-- Created : 2011-08-24
-- Last update: 2012-11-26
-- Last update: 2018-08-03
-- Platform : FPGA-generic
-- Standard : VHDL'93
-------------------------------------------------------------------------------
......@@ -229,14 +229,14 @@ begin -- behavioral
end if;
end process;
U_Sync_WR_Csync : gc_pulse_synchronizer
U_Sync_WR_Csync : gc_pulse_synchronizer2
port map (
clk_in_i => clk_sys_i,
clk_out_i => clk_ref_i,
rst_n_i => rst_n_ref_i,
d_p_i => csync_wr_sysclk,
q_p_o => csync_wr_refclk);
clk_in_i => clk_sys_i,
rst_in_n_i => rst_n_sys_i,
clk_out_i => clk_ref_i,
rst_out_n_i => rst_n_ref_i,
d_p_i => csync_wr_sysclk,
q_p_o => csync_wr_refclk);
tmo_restart <= wr_state_changed;
......
......@@ -6,7 +6,7 @@
-- Author : Tomasz Wlostowski
-- Company : CERN
-- Created : 2011-08-24
-- Last update: 2019-09-02
-- Last update: 2014-03-24
-- Platform : FPGA-generic
-- Standard : VHDL'93
-------------------------------------------------------------------------------
......
......@@ -6,7 +6,7 @@
-- Author : Tomasz Wlostowski
-- Company : CERN
-- Created : 2011-08-24
-- Last update: 2012-05-22
-- Last update: 2018-08-02
-- Platform : FPGA-generic
-- Standard : VHDL'93
-------------------------------------------------------------------------------
......@@ -176,16 +176,17 @@ begin -- behavioral
fifo_write <= not fifo_full and tag_valid_i;
U_Clock_Adjustment_Fifo : generic_async_fifo
U_Clock_Adjustment_Fifo : generic_async_fifo_dual_rst
generic map (
g_data_width => fifo_in'length,
g_size => c_FIFO_SIZE)
port map (
rst_n_i => rst_n_sys_i,
rst_wr_n_i => rst_n_ref_i,
clk_wr_i => clk_ref_i,
d_i => fifo_in,
we_i => fifo_write,
wr_full_o => fifo_full,
rst_rd_n_i => rst_n_sys_i,
clk_rd_i => clk_sys_i,
q_o => fifo_out,
rd_i => fifo_read,
......
......@@ -6,7 +6,7 @@
-- Author : Tomasz Wlostowski
-- Company : CERN
-- Created : 2011-08-24
-- Last update: 2020-05-26
-- Last update: 2014-03-24
-- Platform : FPGA-generic
-- Standard : VHDL'93
-------------------------------------------------------------------------------
......@@ -17,7 +17,7 @@
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
-- Public License as published by the Free Software Fsoundation;
-- Public License as published by the Free Software Foundation;
-- either version 2.1 of the License, or (at your option) any
-- later version.
--
......@@ -215,7 +215,7 @@ entity fine_delay_core is
idelay_cal_o : out std_logic;
idelay_ce_o : out std_logic;
idelay_rst_o : out std_logic;
idelay_busy_i : in std_logic;
idelay_busy_i : in std_logic := '0';
---------------------------------------------------------------------------
......@@ -367,7 +367,7 @@ architecture rtl of fine_delay_core is
signal spi_cs_dac_n, spi_cs_pll_n, spi_cs_gpio_n, spi_mosi : std_logic;
signal dmtd_tag_stb, dbg_tag_in, dbg_tag_out : std_logic;
signal iodelay_ntaps : std_logic_vector(7 downto 0);
signal iodelay_cnt : unsigned(7 downto 0);
signal iodelay_div : unsigned(6 downto 0);
......@@ -573,11 +573,12 @@ begin -- rtl
gen_with_direct_io_tdc : if(g_with_direct_timestamp_io) generate
U_Sync_TDC_Valid_Out : gc_pulse_synchronizer
U_Sync_TDC_Valid_Out : gc_pulse_synchronizer2
port map (
clk_in_i => clk_ref_0_i,
rst_in_n_i => rst_n_ref,
clk_out_i => clk_sys_i,
rst_n_i => rst_n_sys,
rst_out_n_i => rst_n_sys,
d_p_i => tag_valid,
q_p_o => tdc_valid_o);
......@@ -651,12 +652,12 @@ begin -- rtl
gen_with_direct_io : if g_with_direct_timestamp_io generate
U_Sync_Valid_Pulse : gc_pulse_synchronizer
U_Sync_Valid_Pulse : gc_pulse_synchronizer2
port map (
clk_in_i => clk_sys_i,
rst_in_n_i => rst_n_sys,
clk_out_i => clk_ref_0_i,
rst_n_i => rst_n_ref,
rst_out_n_i => rst_n_ref,
d_p_i => outx_valid_i(i),
q_p_o => channels(i).tag.valid);
......@@ -801,7 +802,7 @@ begin -- rtl
regs_towb_local.gcr_fmc_present_i <= not fmc_present_n_i;
regs_towb_local.fmc_slot_id_slot_id_i <= std_logic_vector(to_unsigned(g_fmc_slot_id, 4 ));
-- Debug PWM driver for adjusting Peltier temperature. Drivers SPI MOSI line
-- with PWM waveform when none of the SPI peripherals is in use (we have no
-- spare pins in the FMC connector left)
......@@ -883,8 +884,8 @@ begin -- rtl
p_latch_ntaps : process(clk_sys_i)
begin
if rising_edge(clk_sys_i) then
begin
if rising_edge(clk_sys_i) then
if regs_fromwb.iodelay_adj_n_taps_load_o = '1' then
iodelay_ntaps <= regs_fromwb.iodelay_adj_n_taps_o;
end if;
......@@ -909,7 +910,7 @@ begin -- rtl
if iodelay_cal_done = '0' then
idelay_cal_o <= '1';
iodelay_cal_done <= '1';
iodelay_cal_done <= '1';
else
idelay_cal_o <= '0';
end if;
......@@ -937,10 +938,13 @@ begin -- rtl
idelay_rst_o <= '0';
end if;
end if;
end if;
end process;
regs_towb_local.iodelay_adj_n_taps_i <= iodelay_ntaps;
......
......@@ -17,7 +17,7 @@ spec_base_ucf = ['wr', 'onewire', 'spi']
board = "spec"
ctrls = ["bank3_64b_32b" ]
files = [ "buildinfo_pkg.vhd" ]
files = [ "buildinfo_pkg.vhd", "sourceid_spec_fine_delay_top_pkg.vhd" ]
modules = {
"local" : [ "../../top/spec" ]
......@@ -29,4 +29,14 @@ try:
except:
pass
try:
# Assume this module is in fact a git submodule of a main project that
# is in the same directory as general-cores...
exec(open(fetchto + "/general-cores/tools/gen_sourceid.py").read(),
None, {'project': 'spec_fine_delay_top'})
except Exception as e:
print("Error: cannot generate source id file")
raise
syn_post_project_cmd = "$(TCL_INTERPRETER) syn_extra_steps.tcl $(PROJECT_FILE)"
......@@ -2,10 +2,10 @@ board = "svec"
target = "xilinx"
action = "synthesis"
syn_device = "xc6slx150t"
syn_grade = "-3"
syn_device = "xc6slx150t"
syn_grade = "-3"
syn_package = "fgg900"
syn_top = "svec_top"
syn_top = "svec_top"
syn_project = "svec_fine_delay.xise"
syn_tool = "ise"
......@@ -15,7 +15,7 @@ if locals().get('fetchto', None) is None:
fetchto = "../../ip_cores"
files = [
"buildinfo_pkg.vhd",
"buildinfo_pkg.vhd", "sourceid_svec_fine_delay_top_pkg.vhd"
]
modules = {
......@@ -30,6 +30,16 @@ try:
except:
pass
try:
# Assume this module is in fact a git submodule of a main project that
# is in the same directory as general-cores...
exec(open(fetchto + "/general-cores/tools/gen_sourceid.py").read(),
None, {'project': 'svec_fine_delay_top'})
except Exception as e:
print("Error: cannot generate source id file")
raise
syn_post_project_cmd = "$(TCL_INTERPRETER) syn_extra_steps.tcl $(PROJECT_FILE)"
svec_base_ucf = ['wr', 'led', 'gpio']
......
This source diff could not be displayed because it is too large. You can view the blob instead.
......@@ -3,18 +3,18 @@ action = "simulation"
target = "xilinx"
vcom_opt="-mixedsvvh l"
fetchto = "../../ip_cores"
include_dirs = ["gn4124_bfm",
"../../include",
include_dirs = ["../../include",
"../../ip_cores/general-cores/modules/wishbone/wb_spi/",
"../../ip_cores/general-cores/sim/",
"../../ip_cores/gn4124-core/hdl/sim/gn4124_bfm/",
"../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/"]
syn_device = "xc6slx45t"
sim_tool = "modelsim"
sim_top = "main"
top_module = "main"
files = ["main.sv","buildinfo_pkg.vhd"]
files = ["main.sv","buildinfo_pkg.vhd","../../syn/spec/sourceid_spec_fine_delay_top_pkg.vhd"]
modules = {"local": ["../../top/spec", "gn4124_bfm"]}
modules = {"local": ["../../top/spec", "../../ip_cores/gn4124-core/hdl/sim/gn4124_bfm/" ]}
#try:
exec(open(fetchto + "/general-cores/tools/gen_buildinfo.py").read())
......
......@@ -3,7 +3,8 @@
`include "simdrv_defs.svh"
`include "regs/fd_main_regs.vh"
`include "regs/simple_debug_recorder_regs.vh"
`include "vhd_wishbone_master.svh"
`include "gn4124_bfm.svh"
const uint64_t BASE_WRPC = 'h00c0000;
const uint64_t BASE_FINEDELAY = 'h0010000;
......@@ -136,101 +137,6 @@ class FineDelayDev extends IBusDevice;
endclass // FineDelayDev
/* -----\/----- EXCLUDED -----\/-----
`define ADDR_SDER_CSR 4'h0
`define SDER_CSR_START_OFFSET 0
`define SDER_CSR_START 32'h00000001
`define SDER_CSR_STOP_OFFSET 1
`define SDER_CSR_STOP 32'h00000002
`define SDER_CSR_FORCE_OFFSET 2
`define SDER_CSR_FORCE 32'h00000004
`define SDER_CSR_TRIG_SEL_OFFSET 3
`define SDER_CSR_TRIG_SEL 32'h000000f8
`define SDER_CSR_TRIG_EDGE_OFFSET 8
`define SDER_CSR_TRIG_EDGE 32'h00000100
`define SDER_CSR_TRIGGERED_OFFSET 9
`define SDER_CSR_TRIGGERED 32'h00000200
`define SDER_CSR_TRIG_PRE_SAMPLES_OFFSET 10
`define SDER_CSR_TRIG_PRE_SAMPLES 32'h03fffc00
`define ADDR_SDER_MEM_ADDR 4'h4
`define SDER_MEM_ADDR_ADDR_OFFSET 0
`define SDER_MEM_ADDR_ADDR 32'h0000ffff
`define ADDR_SDER_TRIG_POS 4'h8
`define SDER_TRIG_POS_POS_OFFSET 0
`define SDER_TRIG_POS_POS 32'h0000ffff
`define ADDR_SDER_MEM_DATA 4'hc
`define SDER_MEM_DATA_DATA_OFFSET 0
`define SDER_MEM_DATA_DATA 32'hffffffff
-----/\----- EXCLUDED -----/\----- */
class DebugRecorderDev extends IBusDevice;
function new(CBusAccessor bus, uint64_t base);
super.new(bus, base);
endfunction // new
task automatic configure(int trig_in, int trig_edge, int pre_samples);
uint32_t csr;
csr = (trig_in << `SDER_CSR_TRIG_SEL_OFFSET);
if(trig_edge)
csr|=`SDER_CSR_TRIG_EDGE;
csr |= (pre_samples << `SDER_CSR_TRIG_PRE_SAMPLES_OFFSET);
write32(`ADDR_SDER_CSR, csr);
endtask // configure
task automatic run();
uint32_t csr;
read32(`ADDR_SDER_CSR, csr);
csr |= `SDER_CSR_START;
write32(`ADDR_SDER_CSR, csr);
endtask // run
task automatic readout();
uint32_t csr, pos, mdata, mtag;
int i;
$error("RDS");
forever begin
read32(`ADDR_SDER_CSR, csr);
$display("trig CSR %x", csr);
if( csr & `SDER_CSR_TRIGGERED)
break;
#5us;
end
csr |= `SDER_CSR_STOP;
write32(`ADDR_SDER_CSR, csr);
$display("Readout!");
read32(`ADDR_SDER_TRIG_POS, pos);
$display("Trig pos: %x", pos);
for(i=0;i<10;i++)
begin
write32(`ADDR_SDER_MEM_ADDR, 2*i);
read32(`ADDR_SDER_MEM_DATA, mdata);
write32(`ADDR_SDER_MEM_ADDR, 2*i+1);
read32(`ADDR_SDER_MEM_DATA, mtag);
$display("pos %d %x %x", i, mdata, mtag);
end
endtask // readout
endclass // FineDelayDev
......@@ -249,12 +155,10 @@ module main;
wire clk_sys;
wire rst_sys_n;
wire t_wishbone_master_out sim_wb_in;
wire t_wishbone_master_in sim_wb_out;
IGN4124PCIMaster i_gn4124 ();
spec_fine_delay_top
#(.g_simulation(1)
)
......@@ -274,28 +178,33 @@ module main;
.fmc0_fd_tdc_start_p_i(tdc_start),
.fmc0_fd_tdc_start_n_i(~tdc_start),
.fmc0_fd_pll_status_i(1'b1),
.sim_wb_i(sim_wb_in),
.sim_wb_o(sim_wb_out)
// `GENNUM_WIRE_SPEC_PINS_V2(I_Gennum)
.gn_rst_n_i (i_gn4124.rst_n),
.gn_p2l_clk_n_i (i_gn4124.p2l_clk_n),
.gn_p2l_clk_p_i (i_gn4124.p2l_clk_p),
.gn_p2l_rdy_o (i_gn4124.p2l_rdy),
.gn_p2l_dframe_i (i_gn4124.p2l_dframe),
.gn_p2l_valid_i (i_gn4124.p2l_valid),
.gn_p2l_data_i (i_gn4124.p2l_data),
.gn_p_wr_req_i (i_gn4124.p_wr_req),
.gn_p_wr_rdy_o (i_gn4124.p_wr_rdy),
.gn_rx_error_o (i_gn4124.rx_error),
.gn_l2p_clk_n_o (i_gn4124.l2p_clk_n),
.gn_l2p_clk_p_o (i_gn4124.l2p_clk_p),
.gn_l2p_dframe_o (i_gn4124.l2p_dframe),
.gn_l2p_valid_o (i_gn4124.l2p_valid),
.gn_l2p_edb_o (i_gn4124.l2p_edb),
.gn_l2p_data_o (i_gn4124.l2p_data),
.gn_l2p_rdy_i (i_gn4124.l2p_rdy),
.gn_l_wr_rdy_i (i_gn4124.l_wr_rdy),
.gn_p_rd_d_rdy_i (i_gn4124.p_rd_d_rdy),
.gn_tx_error_i (i_gn4124.tx_error),
.gn_vc_rdy_i (i_gn4124.vc_rdy),
.gn_gpio_b ()
);
IVHDWishboneMaster Host
(
.clk_i (DUT.clk_sys_62m5),
.rst_n_i (DUT.rst_sys_62m5_n));
assign sim_wb_in = Host.out;
assign Host.in = sim_wb_out;
assign clk_sys = DUT.clk_sys_62m5;
assign rst_sys_n = DUT.rst_sys_62m5_n;
......@@ -306,13 +215,11 @@ module main;
CBusAccessor acc ;
FineDelayDev fd;
DebugRecorderDev rec;
acc = Host.get_accessor();
acc = i_gn4124.get_accessor();
fd = new(acc, BASE_FINEDELAY);
rec = new(acc, BASE_FINEDELAY + 'h180 * 4);
while (!rst_sys_n)
@(posedge clk_sys);
......@@ -333,20 +240,12 @@ module main;
fd.set_idelay_taps(20);
#10us;
$stop;
// rec.configure(4, 0, 100);
// rec.run();
acc.read('h1000, rval );
// fd.pll_readl('h1f, tmp);
// $error("done");
$display("R1000 = %x", rval );
// rec.readout();
$stop;
end
......
onerror {resume}
quietly WaveActivateNextPane {} 0
add wave -noupdate -expand -group fdcore /main/DUT/cmp0_fmc_fdelay_mezzanine/clk_ref_0_i
add wave -noupdate -expand -group fdcore /main/DUT/cmp0_fmc_fdelay_mezzanine/clk_ref_180_i
add wave -noupdate -expand -group fdcore /main/DUT/cmp0_fmc_fdelay_mezzanine/clk_sys_i
add wave -noupdate -expand -group fdcore /main/DUT/cmp0_fmc_fdelay_mezzanine/clk_dmtd_i
add wave -noupdate -expand -group fdcore /main/DUT/cmp0_fmc_fdelay_mezzanine/rst_n_i
add wave -noupdate -expand -group fdcore /main/DUT/cmp0_fmc_fdelay_mezzanine/dcm_reset_o
add wave -noupdate -expand -group fdcore /main/DUT/cmp0_fmc_fdelay_mezzanine/dcm_locked_i
add wave -noupdate -expand -group fdcore /main/DUT/cmp0_fmc_fdelay_mezzanine/trig_a_i
add wave -noupdate -expand -group fdcore /main/DUT/cmp0_fmc_fdelay_mezzanine/tdc_cal_pulse_o
add wave -noupdate -expand -group fdcore /main/DUT/cmp0_fmc_fdelay_mezzanine/tdc_start_i
add wave -noupdate -expand -group fdcore /main/DUT/cmp0_fmc_fdelay_mezzanine/dmtd_fb_in_i
add wave -noupdate -expand -group fdcore /main/DUT/cmp0_fmc_fdelay_mezzanine/dmtd_fb_out_i
add wave -noupdate -expand -group fdcore /main/DUT/cmp0_fmc_fdelay_mezzanine/dmtd_samp_o
add wave -noupdate -expand -group fdcore /main/DUT/cmp0_fmc_fdelay_mezzanine/led_trig_o
add wave -noupdate -expand -group fdcore /main/DUT/cmp0_fmc_fdelay_mezzanine/ext_rst_n_o
add wave -noupdate -expand -group fdcore /main/DUT/cmp0_fmc_fdelay_mezzanine/pll_status_i
add wave -noupdate -expand -group fdcore /main/DUT/cmp0_fmc_fdelay_mezzanine/acam_d_o
add wave -noupdate -expand -group fdcore /main/DUT/cmp0_fmc_fdelay_mezzanine/acam_d_i
add wave -noupdate -expand -group fdcore /main/DUT/cmp0_fmc_fdelay_mezzanine/acam_d_oen_o
add wave -noupdate -expand -group fdcore /main/DUT/cmp0_fmc_fdelay_mezzanine/acam_emptyf_i
add wave -noupdate -expand -group fdcore /main/DUT/cmp0_fmc_fdelay_mezzanine/acam_alutrigger_o
add wave -noupdate -expand -group fdcore /main/DUT/cmp0_fmc_fdelay_mezzanine/acam_wr_n_o
add wave -noupdate -expand -group fdcore /main/DUT/cmp0_fmc_fdelay_mezzanine/acam_rd_n_o
add wave -noupdate -expand -group fdcore /main/DUT/cmp0_fmc_fdelay_mezzanine/acam_start_dis_o
add wave -noupdate -expand -group fdcore /main/DUT/cmp0_fmc_fdelay_mezzanine/acam_stop_dis_o
add wave -noupdate -expand -group fdcore /main/DUT/cmp0_fmc_fdelay_mezzanine/spi_cs_dac_n_o
add wave -noupdate -expand -group fdcore /main/DUT/cmp0_fmc_fdelay_mezzanine/spi_cs_pll_n_o
add wave -noupdate -expand -group fdcore /main/DUT/cmp0_fmc_fdelay_mezzanine/spi_cs_gpio_n_o
add wave -noupdate -expand -group fdcore /main/DUT/cmp0_fmc_fdelay_mezzanine/spi_sclk_o
add wave -noupdate -expand -group fdcore /main/DUT/cmp0_fmc_fdelay_mezzanine/spi_mosi_o
add wave -noupdate -expand -group fdcore /main/DUT/cmp0_fmc_fdelay_mezzanine/spi_miso_i
add wave -noupdate -expand -group fdcore /main/DUT/cmp0_fmc_fdelay_mezzanine/delay_len_o
add wave -noupdate -expand -group fdcore /main/DUT/cmp0_fmc_fdelay_mezzanine/delay_val_o
add wave -noupdate -expand -group fdcore /main/DUT/cmp0_fmc_fdelay_mezzanine/delay_pulse_o
add wave -noupdate -expand -group fdcore /main/DUT/cmp0_fmc_fdelay_mezzanine/tm_link_up_i
add wave -noupdate -expand -group fdcore /main/DUT/cmp0_fmc_fdelay_mezzanine/tm_time_valid_i
add wave -noupdate -expand -group fdcore /main/DUT/cmp0_fmc_fdelay_mezzanine/tm_cycles_i
add wave -noupdate -expand -group fdcore /main/DUT/cmp0_fmc_fdelay_mezzanine/tm_utc_i
add wave -noupdate -expand -group fdcore /main/DUT/cmp0_fmc_fdelay_mezzanine/tm_clk_aux_lock_en_o
add wave -noupdate -expand -group fdcore /main/DUT/cmp0_fmc_fdelay_mezzanine/tm_clk_aux_locked_i
add wave -noupdate -expand -group fdcore /main/DUT/cmp0_fmc_fdelay_mezzanine/tm_clk_dmtd_locked_i
add wave -noupdate -expand -group fdcore /main/DUT/cmp0_fmc_fdelay_mezzanine/tm_dac_value_i
add wave -noupdate -expand -group fdcore /main/DUT/cmp0_fmc_fdelay_mezzanine/tm_dac_wr_i
add wave -noupdate -expand -group fdcore /main/DUT/cmp0_fmc_fdelay_mezzanine/owr_en_o
add wave -noupdate -expand -group fdcore /main/DUT/cmp0_fmc_fdelay_mezzanine/owr_i
add wave -noupdate -expand -group fdcore /main/DUT/cmp0_fmc_fdelay_mezzanine/i2c_scl_o
add wave -noupdate -expand -group fdcore /main/DUT/cmp0_fmc_fdelay_mezzanine/i2c_scl_oen_o
add wave -noupdate -expand -group fdcore /main/DUT/cmp0_fmc_fdelay_mezzanine/i2c_scl_i
add wave -noupdate -expand -group fdcore /main/DUT/cmp0_fmc_fdelay_mezzanine/i2c_sda_o
add wave -noupdate -expand -group fdcore /main/DUT/cmp0_fmc_fdelay_mezzanine/i2c_sda_oen_o
add wave -noupdate -expand -group fdcore /main/DUT/cmp0_fmc_fdelay_mezzanine/i2c_sda_i
add wave -noupdate -expand -group fdcore /main/DUT/cmp0_fmc_fdelay_mezzanine/fmc_present_n_i
add wave -noupdate -expand -group fdcore /main/DUT/cmp0_fmc_fdelay_mezzanine/idelay_inc_o
add wave -noupdate -expand -group fdcore /main/DUT/cmp0_fmc_fdelay_mezzanine/idelay_cal_o
add wave -noupdate -expand -group fdcore /main/DUT/cmp0_fmc_fdelay_mezzanine/idelay_ce_o
add wave -noupdate -expand -group fdcore /main/DUT/cmp0_fmc_fdelay_mezzanine/idelay_rst_o
add wave -noupdate -expand -group fdcore /main/DUT/cmp0_fmc_fdelay_mezzanine/idelay_busy_i
add wave -noupdate -expand -group fdcore /main/DUT/cmp0_fmc_fdelay_mezzanine/wb_adr_i
add wave -noupdate -expand -group fdcore /main/DUT/cmp0_fmc_fdelay_mezzanine/wb_dat_i
add wave -noupdate -expand -group fdcore /main/DUT/cmp0_fmc_fdelay_mezzanine/wb_dat_o
add wave -noupdate -expand -group fdcore /main/DUT/cmp0_fmc_fdelay_mezzanine/wb_sel_i
add wave -noupdate -expand -group fdcore /main/DUT/cmp0_fmc_fdelay_mezzanine/wb_cyc_i
add wave -noupdate -expand -group fdcore /main/DUT/cmp0_fmc_fdelay_mezzanine/wb_stb_i
add wave -noupdate -expand -group fdcore /main/DUT/cmp0_fmc_fdelay_mezzanine/wb_we_i
add wave -noupdate -expand -group fdcore /main/DUT/cmp0_fmc_fdelay_mezzanine/wb_ack_o
add wave -noupdate -expand -group fdcore /main/DUT/cmp0_fmc_fdelay_mezzanine/wb_stall_o
add wave -noupdate -expand -group fdcore /main/DUT/cmp0_fmc_fdelay_mezzanine/wb_irq_o
add wave -noupdate -expand -group fdcore /main/DUT/cmp0_fmc_fdelay_mezzanine/tdc_seconds_o
add wave -noupdate -expand -group fdcore /main/DUT/cmp0_fmc_fdelay_mezzanine/tdc_cycles_o
add wave -noupdate -expand -group fdcore /main/DUT/cmp0_fmc_fdelay_mezzanine/tdc_frac_o
add wave -noupdate -expand -group fdcore /main/DUT/cmp0_fmc_fdelay_mezzanine/tdc_valid_o
add wave -noupdate -expand -group fdcore /main/DUT/cmp0_fmc_fdelay_mezzanine/outx_seconds_i
add wave -noupdate -expand -group fdcore /main/DUT/cmp0_fmc_fdelay_mezzanine/outx_cycles_i
add wave -noupdate -expand -group fdcore /main/DUT/cmp0_fmc_fdelay_mezzanine/outx_frac_i
add wave -noupdate -expand -group fdcore /main/DUT/cmp0_fmc_fdelay_mezzanine/outx_valid_i
add wave -noupdate -expand -group fdcore /main/DUT/cmp0_fmc_fdelay_mezzanine/dbg_o
add wave -noupdate -expand -group fdcore /main/DUT/cmp0_fmc_fdelay_mezzanine/tag_frac
add wave -noupdate -expand -group fdcore /main/DUT/cmp0_fmc_fdelay_mezzanine/tag_coarse
add wave -noupdate -expand -group fdcore /main/DUT/cmp0_fmc_fdelay_mezzanine/tag_utc
add wave -noupdate -expand -group fdcore /main/DUT/cmp0_fmc_fdelay_mezzanine/tag_dbg
add wave -noupdate -expand -group fdcore /main/DUT/cmp0_fmc_fdelay_mezzanine/tag_valid
add wave -noupdate -expand -group fdcore /main/DUT/cmp0_fmc_fdelay_mezzanine/rbuf_mux_ts
add wave -noupdate -expand -group fdcore /main/DUT/cmp0_fmc_fdelay_mezzanine/rbuf_mux_valid
add wave -noupdate -expand -group fdcore /main/DUT/cmp0_fmc_fdelay_mezzanine/rbuf_mux_valid_masked
add wave -noupdate -expand -group fdcore /main/DUT/cmp0_fmc_fdelay_mezzanine/rbuf_in_ts
add wave -noupdate -expand -group fdcore /main/DUT/cmp0_fmc_fdelay_mezzanine/rbuf_source
add wave -noupdate -expand -group fdcore /main/DUT/cmp0_fmc_fdelay_mezzanine/rbuf_valid
add wave -noupdate -expand -group fdcore /main/DUT/cmp0_fmc_fdelay_mezzanine/rbuf_mux_d
add wave -noupdate -expand -group fdcore /main/DUT/cmp0_fmc_fdelay_mezzanine/rbuf_mux_q
add wave -noupdate -expand -group fdcore /main/DUT/cmp0_fmc_fdelay_mezzanine/master_csync_p1
add wave -noupdate -expand -group fdcore /main/DUT/cmp0_fmc_fdelay_mezzanine/master_csync_utc
add wave -noupdate -expand -group fdcore /main/DUT/cmp0_fmc_fdelay_mezzanine/master_csync_coarse
add wave -noupdate -expand -group fdcore /main/DUT/cmp0_fmc_fdelay_mezzanine/rst_n_sys
add wave -noupdate -expand -group fdcore /main/DUT/cmp0_fmc_fdelay_mezzanine/rst_n_ref
add wave -noupdate -expand -group fdcore /main/DUT/cmp0_fmc_fdelay_mezzanine/tsbcr_read_ack
add wave -noupdate -expand -group fdcore /main/DUT/cmp0_fmc_fdelay_mezzanine/fid_read_ack
add wave -noupdate -expand -group fdcore /main/DUT/cmp0_fmc_fdelay_mezzanine/irq_rbuf
add wave -noupdate -expand -group fdcore /main/DUT/cmp0_fmc_fdelay_mezzanine/irq_sync
add wave -noupdate -expand -group fdcore /main/DUT/cmp0_fmc_fdelay_mezzanine/channels
add wave -noupdate -expand -group fdcore /main/DUT/cmp0_fmc_fdelay_mezzanine/chx_delay_idle
add wave -noupdate -expand -group fdcore /main/DUT/cmp0_fmc_fdelay_mezzanine/cnx_out
add wave -noupdate -expand -group fdcore /main/DUT/cmp0_fmc_fdelay_mezzanine/cnx_in
add wave -noupdate -expand -group fdcore /main/DUT/cmp0_fmc_fdelay_mezzanine/slave_in
add wave -noupdate -expand -group fdcore /main/DUT/cmp0_fmc_fdelay_mezzanine/slave_out
add wave -noupdate -expand -group fdcore /main/DUT/cmp0_fmc_fdelay_mezzanine/regs_fromwb
add wave -noupdate -expand -group fdcore /main/DUT/cmp0_fmc_fdelay_mezzanine/regs_towb_csync
add wave -noupdate -expand -group fdcore /main/DUT/cmp0_fmc_fdelay_mezzanine/regs_towb_spi
add wave -noupdate -expand -group fdcore /main/DUT/cmp0_fmc_fdelay_mezzanine/regs_towb_tsu
add wave -noupdate -expand -group fdcore /main/DUT/cmp0_fmc_fdelay_mezzanine/regs_towb_rbuf
add wave -noupdate -expand -group fdcore /main/DUT/cmp0_fmc_fdelay_mezzanine/regs_towb_local
add wave -noupdate -expand -group fdcore /main/DUT/cmp0_fmc_fdelay_mezzanine/regs_towb_dmtd
add wave -noupdate -expand -group fdcore /main/DUT/cmp0_fmc_fdelay_mezzanine/regs_towb
add wave -noupdate -expand -group fdcore /main/DUT/cmp0_fmc_fdelay_mezzanine/owr_en_int
add wave -noupdate -expand -group fdcore /main/DUT/cmp0_fmc_fdelay_mezzanine/owr_int
add wave -noupdate -expand -group fdcore /main/DUT/cmp0_fmc_fdelay_mezzanine/dbg_acam
add wave -noupdate -expand -group fdcore /main/DUT/cmp0_fmc_fdelay_mezzanine/gen_cal_pulse
add wave -noupdate -expand -group fdcore /main/DUT/cmp0_fmc_fdelay_mezzanine/cal_pulse_mask
add wave -noupdate -expand -group fdcore /main/DUT/cmp0_fmc_fdelay_mezzanine/cal_pulse_trigger
add wave -noupdate -expand -group fdcore /main/DUT/cmp0_fmc_fdelay_mezzanine/tm_dac_val_int
add wave -noupdate -expand -group fdcore /main/DUT/cmp0_fmc_fdelay_mezzanine/tcr_rd_ack
add wave -noupdate -expand -group fdcore /main/DUT/cmp0_fmc_fdelay_mezzanine/tag_valid_masked
add wave -noupdate -expand -group fdcore /main/DUT/cmp0_fmc_fdelay_mezzanine/dmtd_pattern
add wave -noupdate -expand -group fdcore /main/DUT/cmp0_fmc_fdelay_mezzanine/csync_pps
add wave -noupdate -expand -group fdcore /main/DUT/cmp0_fmc_fdelay_mezzanine/tdc_cal_pulse
add wave -noupdate -expand -group fdcore /main/DUT/cmp0_fmc_fdelay_mezzanine/dmtr_in_rd_ack
add wave -noupdate -expand -group fdcore /main/DUT/cmp0_fmc_fdelay_mezzanine/dmtr_out_rd_ack
add wave -noupdate -expand -group fdcore /main/DUT/cmp0_fmc_fdelay_mezzanine/pwm_count
add wave -noupdate -expand -group fdcore /main/DUT/cmp0_fmc_fdelay_mezzanine/pwm_out
add wave -noupdate -expand -group fdcore /main/DUT/cmp0_fmc_fdelay_mezzanine/spi_cs_dac_n
add wave -noupdate -expand -group fdcore /main/DUT/cmp0_fmc_fdelay_mezzanine/spi_cs_pll_n
add wave -noupdate -expand -group fdcore /main/DUT/cmp0_fmc_fdelay_mezzanine/spi_cs_gpio_n
add wave -noupdate -expand -group fdcore /main/DUT/cmp0_fmc_fdelay_mezzanine/spi_mosi
add wave -noupdate -expand -group fdcore /main/DUT/cmp0_fmc_fdelay_mezzanine/dmtd_tag_stb
add wave -noupdate -expand -group fdcore /main/DUT/cmp0_fmc_fdelay_mezzanine/dbg_tag_in
add wave -noupdate -expand -group fdcore /main/DUT/cmp0_fmc_fdelay_mezzanine/dbg_tag_out
add wave -noupdate -expand -group fdcore /main/DUT/cmp0_fmc_fdelay_mezzanine/iodelay_ntaps
add wave -noupdate -expand -group fdcore /main/DUT/cmp0_fmc_fdelay_mezzanine/iodelay_cnt
add wave -noupdate -expand -group fdcore /main/DUT/cmp0_fmc_fdelay_mezzanine/iodelay_div
add wave -noupdate -expand -group fdcore /main/DUT/cmp0_fmc_fdelay_mezzanine/iodelay_tick
add wave -noupdate -expand -group fdcore /main/DUT/cmp0_fmc_fdelay_mezzanine/iodelay_cal_done
add wave -noupdate -expand -group fdcore /main/DUT/cmp0_fmc_fdelay_mezzanine/iodelay_cal_in_progress
add wave -noupdate -expand -group fdcore /main/DUT/cmp0_fmc_fdelay_mezzanine/iodelay_n_taps_load_refclk_p
add wave -noupdate -expand -group fdcore /main/DUT/cmp0_fmc_fdelay_mezzanine/iodelay_busy_synced
add wave -noupdate -expand -group fdcore /main/DUT/cmp0_fmc_fdelay_mezzanine/iodelay_latch_reset
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add wave -noupdate /main/DUT/inst_spec_base/gen_wr/cmp_xwrc_board_spec/cmp_board_common/cmp_xwr_core/WRPC/wb_dat_i
add wave -noupdate /main/DUT/inst_spec_base/gen_wr/cmp_xwrc_board_spec/cmp_board_common/cmp_xwr_core/WRPC/wb_dat_o
add wave -noupdate /main/DUT/inst_spec_base/gen_wr/cmp_xwrc_board_spec/cmp_board_common/cmp_xwr_core/WRPC/wb_sel_i
add wave -noupdate /main/DUT/inst_spec_base/gen_wr/cmp_xwrc_board_spec/cmp_board_common/cmp_xwr_core/WRPC/wb_we_i
add wave -noupdate /main/DUT/inst_spec_base/gen_wr/cmp_xwrc_board_spec/cmp_board_common/cmp_xwr_core/WRPC/wb_cyc_i
add wave -noupdate /main/DUT/inst_spec_base/gen_wr/cmp_xwrc_board_spec/cmp_board_common/cmp_xwr_core/WRPC/wb_stb_i
add wave -noupdate /main/DUT/inst_spec_base/gen_wr/cmp_xwrc_board_spec/cmp_board_common/cmp_xwr_core/WRPC/wb_ack_o
add wave -noupdate /main/DUT/inst_spec_base/gen_wr/cmp_xwrc_board_spec/cmp_board_common/cmp_xwr_core/WRPC/wb_err_o
add wave -noupdate /main/DUT/inst_spec_base/gen_wr/cmp_xwrc_board_spec/cmp_board_common/cmp_xwr_core/WRPC/wb_rty_o
add wave -noupdate /main/DUT/inst_spec_base/gen_wr/cmp_xwrc_board_spec/cmp_board_common/cmp_xwr_core/WRPC/wb_stall_o
add wave -noupdate /main/DUT/inst_spec_base/gen_wr/cmp_xwrc_board_spec/cmp_board_common/cmp_xwr_core/WRPC/aux_adr_o
add wave -noupdate /main/DUT/inst_spec_base/gen_wr/cmp_xwrc_board_spec/cmp_board_common/cmp_xwr_core/WRPC/aux_dat_o
add wave -noupdate /main/DUT/inst_spec_base/gen_wr/cmp_xwrc_board_spec/cmp_board_common/cmp_xwr_core/WRPC/aux_dat_i
add wave -noupdate /main/DUT/inst_spec_base/gen_wr/cmp_xwrc_board_spec/cmp_board_common/cmp_xwr_core/WRPC/aux_sel_o
add wave -noupdate /main/DUT/inst_spec_base/gen_wr/cmp_xwrc_board_spec/cmp_board_common/cmp_xwr_core/WRPC/aux_we_o
add wave -noupdate /main/DUT/inst_spec_base/gen_wr/cmp_xwrc_board_spec/cmp_board_common/cmp_xwr_core/WRPC/aux_cyc_o
add wave -noupdate /main/DUT/inst_spec_base/gen_wr/cmp_xwrc_board_spec/cmp_board_common/cmp_xwr_core/WRPC/aux_stb_o
add wave -noupdate /main/DUT/inst_spec_base/gen_wr/cmp_xwrc_board_spec/cmp_board_common/cmp_xwr_core/WRPC/aux_ack_i
add wave -noupdate /main/DUT/inst_spec_base/gen_wr/cmp_xwrc_board_spec/cmp_board_common/cmp_xwr_core/WRPC/aux_stall_i
add wave -noupdate /main/DUT/inst_spec_base/gen_wr/cmp_xwrc_board_spec/cmp_board_common/cmp_xwr_core/WRPC/ext_snk_adr_i
add wave -noupdate /main/DUT/inst_spec_base/gen_wr/cmp_xwrc_board_spec/cmp_board_common/cmp_xwr_core/WRPC/ext_snk_dat_i
add wave -noupdate /main/DUT/inst_spec_base/gen_wr/cmp_xwrc_board_spec/cmp_board_common/cmp_xwr_core/WRPC/ext_snk_sel_i
add wave -noupdate /main/DUT/inst_spec_base/gen_wr/cmp_xwrc_board_spec/cmp_board_common/cmp_xwr_core/WRPC/ext_snk_cyc_i
add wave -noupdate /main/DUT/inst_spec_base/gen_wr/cmp_xwrc_board_spec/cmp_board_common/cmp_xwr_core/WRPC/ext_snk_we_i
add wave -noupdate /main/DUT/inst_spec_base/gen_wr/cmp_xwrc_board_spec/cmp_board_common/cmp_xwr_core/WRPC/ext_snk_stb_i
add wave -noupdate /main/DUT/inst_spec_base/gen_wr/cmp_xwrc_board_spec/cmp_board_common/cmp_xwr_core/WRPC/ext_snk_ack_o
add wave -noupdate /main/DUT/inst_spec_base/gen_wr/cmp_xwrc_board_spec/cmp_board_common/cmp_xwr_core/WRPC/ext_snk_err_o
add wave -noupdate /main/DUT/inst_spec_base/gen_wr/cmp_xwrc_board_spec/cmp_board_common/cmp_xwr_core/WRPC/ext_snk_stall_o
add wave -noupdate /main/DUT/inst_spec_base/gen_wr/cmp_xwrc_board_spec/cmp_board_common/cmp_xwr_core/WRPC/ext_src_adr_o
add wave -noupdate /main/DUT/inst_spec_base/gen_wr/cmp_xwrc_board_spec/cmp_board_common/cmp_xwr_core/WRPC/ext_src_dat_o
add wave -noupdate /main/DUT/inst_spec_base/gen_wr/cmp_xwrc_board_spec/cmp_board_common/cmp_xwr_core/WRPC/ext_src_sel_o
add wave -noupdate /main/DUT/inst_spec_base/gen_wr/cmp_xwrc_board_spec/cmp_board_common/cmp_xwr_core/WRPC/ext_src_cyc_o
add wave -noupdate /main/DUT/inst_spec_base/gen_wr/cmp_xwrc_board_spec/cmp_board_common/cmp_xwr_core/WRPC/ext_src_stb_o
add wave -noupdate /main/DUT/inst_spec_base/gen_wr/cmp_xwrc_board_spec/cmp_board_common/cmp_xwr_core/WRPC/ext_src_we_o
add wave -noupdate /main/DUT/inst_spec_base/gen_wr/cmp_xwrc_board_spec/cmp_board_common/cmp_xwr_core/WRPC/ext_src_ack_i
add wave -noupdate /main/DUT/inst_spec_base/gen_wr/cmp_xwrc_board_spec/cmp_board_common/cmp_xwr_core/WRPC/ext_src_err_i
add wave -noupdate /main/DUT/inst_spec_base/gen_wr/cmp_xwrc_board_spec/cmp_board_common/cmp_xwr_core/WRPC/ext_src_stall_i
add wave -noupdate /main/DUT/inst_spec_base/gen_wr/cmp_xwrc_board_spec/cmp_board_common/cmp_xwr_core/WRPC/txtsu_port_id_o
add wave -noupdate /main/DUT/inst_spec_base/gen_wr/cmp_xwrc_board_spec/cmp_board_common/cmp_xwr_core/WRPC/txtsu_frame_id_o
add wave -noupdate /main/DUT/inst_spec_base/gen_wr/cmp_xwrc_board_spec/cmp_board_common/cmp_xwr_core/WRPC/txtsu_ts_value_o
add wave -noupdate /main/DUT/inst_spec_base/gen_wr/cmp_xwrc_board_spec/cmp_board_common/cmp_xwr_core/WRPC/txtsu_ts_incorrect_o
add wave -noupdate /main/DUT/inst_spec_base/gen_wr/cmp_xwrc_board_spec/cmp_board_common/cmp_xwr_core/WRPC/txtsu_stb_o
add wave -noupdate /main/DUT/inst_spec_base/gen_wr/cmp_xwrc_board_spec/cmp_board_common/cmp_xwr_core/WRPC/txtsu_ack_i
add wave -noupdate /main/DUT/inst_spec_base/gen_wr/cmp_xwrc_board_spec/cmp_board_common/cmp_xwr_core/WRPC/abscal_txts_o
add wave -noupdate /main/DUT/inst_spec_base/gen_wr/cmp_xwrc_board_spec/cmp_board_common/cmp_xwr_core/WRPC/abscal_rxts_o
add wave -noupdate /main/DUT/inst_spec_base/gen_wr/cmp_xwrc_board_spec/cmp_board_common/cmp_xwr_core/WRPC/fc_tx_pause_req_i
add wave -noupdate /main/DUT/inst_spec_base/gen_wr/cmp_xwrc_board_spec/cmp_board_common/cmp_xwr_core/WRPC/fc_tx_pause_delay_i
add wave -noupdate /main/DUT/inst_spec_base/gen_wr/cmp_xwrc_board_spec/cmp_board_common/cmp_xwr_core/WRPC/fc_tx_pause_ready_o
add wave -noupdate /main/DUT/inst_spec_base/gen_wr/cmp_xwrc_board_spec/cmp_board_common/cmp_xwr_core/WRPC/tm_link_up_o
add wave -noupdate /main/DUT/inst_spec_base/gen_wr/cmp_xwrc_board_spec/cmp_board_common/cmp_xwr_core/WRPC/tm_dac_value_o
add wave -noupdate /main/DUT/inst_spec_base/gen_wr/cmp_xwrc_board_spec/cmp_board_common/cmp_xwr_core/WRPC/tm_dac_wr_o
add wave -noupdate /main/DUT/inst_spec_base/gen_wr/cmp_xwrc_board_spec/cmp_board_common/cmp_xwr_core/WRPC/tm_clk_aux_lock_en_i
add wave -noupdate /main/DUT/inst_spec_base/gen_wr/cmp_xwrc_board_spec/cmp_board_common/cmp_xwr_core/WRPC/tm_clk_aux_locked_o
add wave -noupdate /main/DUT/inst_spec_base/gen_wr/cmp_xwrc_board_spec/cmp_board_common/cmp_xwr_core/WRPC/tm_time_valid_o
add wave -noupdate /main/DUT/inst_spec_base/gen_wr/cmp_xwrc_board_spec/cmp_board_common/cmp_xwr_core/WRPC/tm_tai_o
add wave -noupdate /main/DUT/inst_spec_base/gen_wr/cmp_xwrc_board_spec/cmp_board_common/cmp_xwr_core/WRPC/tm_cycles_o
add wave -noupdate /main/DUT/inst_spec_base/gen_wr/cmp_xwrc_board_spec/cmp_board_common/cmp_xwr_core/WRPC/pps_csync_o
add wave -noupdate /main/DUT/inst_spec_base/gen_wr/cmp_xwrc_board_spec/cmp_board_common/cmp_xwr_core/WRPC/pps_valid_o
add wave -noupdate /main/DUT/inst_spec_base/gen_wr/cmp_xwrc_board_spec/cmp_board_common/cmp_xwr_core/WRPC/pps_p_o
add wave -noupdate /main/DUT/inst_spec_base/gen_wr/cmp_xwrc_board_spec/cmp_board_common/cmp_xwr_core/WRPC/pps_led_o
add wave -noupdate /main/DUT/inst_spec_base/gen_wr/cmp_xwrc_board_spec/cmp_board_common/cmp_xwr_core/WRPC/rst_aux_n_o
add wave -noupdate /main/DUT/inst_spec_base/gen_wr/cmp_xwrc_board_spec/cmp_board_common/cmp_xwr_core/WRPC/link_ok_o
add wave -noupdate /main/DUT/inst_spec_base/gen_wr/cmp_xwrc_board_spec/cmp_board_common/cmp_xwr_core/WRPC/aux_diag_i
add wave -noupdate /main/DUT/inst_spec_base/gen_wr/cmp_xwrc_board_spec/cmp_board_common/cmp_xwr_core/WRPC/aux_diag_o
add wave -noupdate /main/DUT/inst_spec_base/gen_wr/cmp_xwrc_board_spec/cmp_board_common/cmp_xwr_core/WRPC/rst_wrc_n
add wave -noupdate /main/DUT/inst_spec_base/gen_wr/cmp_xwrc_board_spec/cmp_board_common/cmp_xwr_core/WRPC/rst_net_n
add wave -noupdate /main/DUT/inst_spec_base/gen_wr/cmp_xwrc_board_spec/cmp_board_common/cmp_xwr_core/WRPC/rst_net_resync_ref_n
add wave -noupdate /main/DUT/inst_spec_base/gen_wr/cmp_xwrc_board_spec/cmp_board_common/cmp_xwr_core/WRPC/rst_net_resync_ext_n
add wave -noupdate /main/DUT/inst_spec_base/gen_wr/cmp_xwrc_board_spec/cmp_board_common/cmp_xwr_core/WRPC/rst_net_resync_dmtd_n
add wave -noupdate /main/DUT/inst_spec_base/gen_wr/cmp_xwrc_board_spec/cmp_board_common/cmp_xwr_core/WRPC/rst_net_resync_rxclk_n
add wave -noupdate /main/DUT/inst_spec_base/gen_wr/cmp_xwrc_board_spec/cmp_board_common/cmp_xwr_core/WRPC/rst_net_resync_txclk_n
add wave -noupdate /main/DUT/inst_spec_base/gen_wr/cmp_xwrc_board_spec/cmp_board_common/cmp_xwr_core/WRPC/s_pps_csync
add wave -noupdate /main/DUT/inst_spec_base/gen_wr/cmp_xwrc_board_spec/cmp_board_common/cmp_xwr_core/WRPC/pps_valid
add wave -noupdate /main/DUT/inst_spec_base/gen_wr/cmp_xwrc_board_spec/cmp_board_common/cmp_xwr_core/WRPC/ppsg_link_ok
add wave -noupdate /main/DUT/inst_spec_base/gen_wr/cmp_xwrc_board_spec/cmp_board_common/cmp_xwr_core/WRPC/ppsg_wb_in
add wave -noupdate /main/DUT/inst_spec_base/gen_wr/cmp_xwrc_board_spec/cmp_board_common/cmp_xwr_core/WRPC/ppsg_wb_out
add wave -noupdate /main/DUT/inst_spec_base/gen_wr/cmp_xwrc_board_spec/cmp_board_common/cmp_xwr_core/WRPC/phy_rx_clk
add wave -noupdate /main/DUT/inst_spec_base/gen_wr/cmp_xwrc_board_spec/cmp_board_common/cmp_xwr_core/WRPC/phy_tx_clk
add wave -noupdate /main/DUT/inst_spec_base/gen_wr/cmp_xwrc_board_spec/cmp_board_common/cmp_xwr_core/WRPC/spll_wb_in
add wave -noupdate /main/DUT/inst_spec_base/gen_wr/cmp_xwrc_board_spec/cmp_board_common/cmp_xwr_core/WRPC/spll_wb_out
add wave -noupdate /main/DUT/inst_spec_base/gen_wr/cmp_xwrc_board_spec/cmp_board_common/cmp_xwr_core/WRPC/ep_txtsu_port_id
add wave -noupdate /main/DUT/inst_spec_base/gen_wr/cmp_xwrc_board_spec/cmp_board_common/cmp_xwr_core/WRPC/ep_txtsu_frame_id
add wave -noupdate /main/DUT/inst_spec_base/gen_wr/cmp_xwrc_board_spec/cmp_board_common/cmp_xwr_core/WRPC/ep_txtsu_ts_value
add wave -noupdate /main/DUT/inst_spec_base/gen_wr/cmp_xwrc_board_spec/cmp_board_common/cmp_xwr_core/WRPC/ep_txtsu_ts_incorrect
add wave -noupdate /main/DUT/inst_spec_base/gen_wr/cmp_xwrc_board_spec/cmp_board_common/cmp_xwr_core/WRPC/ep_txtsu_stb
add wave -noupdate /main/DUT/inst_spec_base/gen_wr/cmp_xwrc_board_spec/cmp_board_common/cmp_xwr_core/WRPC/ep_txtsu_ack
add wave -noupdate /main/DUT/inst_spec_base/gen_wr/cmp_xwrc_board_spec/cmp_board_common/cmp_xwr_core/WRPC/ep_led_link
add wave -noupdate /main/DUT/inst_spec_base/gen_wr/cmp_xwrc_board_spec/cmp_board_common/cmp_xwr_core/WRPC/phy_rst
add wave -noupdate /main/DUT/inst_spec_base/gen_wr/cmp_xwrc_board_spec/cmp_board_common/cmp_xwr_core/WRPC/mnic_mem_data_o
add wave -noupdate /main/DUT/inst_spec_base/gen_wr/cmp_xwrc_board_spec/cmp_board_common/cmp_xwr_core/WRPC/mnic_mem_addr_o
add wave -noupdate /main/DUT/inst_spec_base/gen_wr/cmp_xwrc_board_spec/cmp_board_common/cmp_xwr_core/WRPC/mnic_mem_wr_o
add wave -noupdate /main/DUT/inst_spec_base/gen_wr/cmp_xwrc_board_spec/cmp_board_common/cmp_xwr_core/WRPC/mnic_txtsu_ack
add wave -noupdate /main/DUT/inst_spec_base/gen_wr/cmp_xwrc_board_spec/cmp_board_common/cmp_xwr_core/WRPC/mnic_txtsu_stb
add wave -noupdate /main/DUT/inst_spec_base/gen_wr/cmp_xwrc_board_spec/cmp_board_common/cmp_xwr_core/WRPC/dpram_wbb_i
add wave -noupdate /main/DUT/inst_spec_base/gen_wr/cmp_xwrc_board_spec/cmp_board_common/cmp_xwr_core/WRPC/periph_slave_i
add wave -noupdate /main/DUT/inst_spec_base/gen_wr/cmp_xwrc_board_spec/cmp_board_common/cmp_xwr_core/WRPC/periph_slave_o
add wave -noupdate /main/DUT/inst_spec_base/gen_wr/cmp_xwrc_board_spec/cmp_board_common/cmp_xwr_core/WRPC/sysc_in_regs
add wave -noupdate /main/DUT/inst_spec_base/gen_wr/cmp_xwrc_board_spec/cmp_board_common/cmp_xwr_core/WRPC/sysc_out_regs
add wave -noupdate /main/DUT/inst_spec_base/gen_wr/cmp_xwrc_board_spec/cmp_board_common/cmp_xwr_core/WRPC/secbar_master_i
add wave -noupdate /main/DUT/inst_spec_base/gen_wr/cmp_xwrc_board_spec/cmp_board_common/cmp_xwr_core/WRPC/secbar_master_o
add wave -noupdate /main/DUT/inst_spec_base/gen_wr/cmp_xwrc_board_spec/cmp_board_common/cmp_xwr_core/WRPC/cbar_slave_i
add wave -noupdate /main/DUT/inst_spec_base/gen_wr/cmp_xwrc_board_spec/cmp_board_common/cmp_xwr_core/WRPC/cbar_slave_o
add wave -noupdate /main/DUT/inst_spec_base/gen_wr/cmp_xwrc_board_spec/cmp_board_common/cmp_xwr_core/WRPC/cbar_master_i
add wave -noupdate /main/DUT/inst_spec_base/gen_wr/cmp_xwrc_board_spec/cmp_board_common/cmp_xwr_core/WRPC/cbar_master_o
add wave -noupdate /main/DUT/inst_spec_base/gen_wr/cmp_xwrc_board_spec/cmp_board_common/cmp_xwr_core/WRPC/ext_wb_in
add wave -noupdate /main/DUT/inst_spec_base/gen_wr/cmp_xwrc_board_spec/cmp_board_common/cmp_xwr_core/WRPC/ext_wb_out
add wave -noupdate /main/DUT/inst_spec_base/gen_wr/cmp_xwrc_board_spec/cmp_board_common/cmp_xwr_core/WRPC/hpll_auxout
add wave -noupdate /main/DUT/inst_spec_base/gen_wr/cmp_xwrc_board_spec/cmp_board_common/cmp_xwr_core/WRPC/dmpll_auxout
add wave -noupdate /main/DUT/inst_spec_base/gen_wr/cmp_xwrc_board_spec/cmp_board_common/cmp_xwr_core/WRPC/clk_ref_slv
add wave -noupdate /main/DUT/inst_spec_base/gen_wr/cmp_xwrc_board_spec/cmp_board_common/cmp_xwr_core/WRPC/clk_rx_slv
add wave -noupdate /main/DUT/inst_spec_base/gen_wr/cmp_xwrc_board_spec/cmp_board_common/cmp_xwr_core/WRPC/s_dummy_addr
add wave -noupdate /main/DUT/inst_spec_base/gen_wr/cmp_xwrc_board_spec/cmp_board_common/cmp_xwr_core/WRPC/softpll_irq
add wave -noupdate /main/DUT/inst_spec_base/gen_wr/cmp_xwrc_board_spec/cmp_board_common/cmp_xwr_core/WRPC/lm32_irq_slv
add wave -noupdate /main/DUT/inst_spec_base/gen_wr/cmp_xwrc_board_spec/cmp_board_common/cmp_xwr_core/WRPC/ep_wb_in
add wave -noupdate /main/DUT/inst_spec_base/gen_wr/cmp_xwrc_board_spec/cmp_board_common/cmp_xwr_core/WRPC/ep_wb_out
add wave -noupdate /main/DUT/inst_spec_base/gen_wr/cmp_xwrc_board_spec/cmp_board_common/cmp_xwr_core/WRPC/minic_wb_in
add wave -noupdate /main/DUT/inst_spec_base/gen_wr/cmp_xwrc_board_spec/cmp_board_common/cmp_xwr_core/WRPC/minic_wb_out
add wave -noupdate /main/DUT/inst_spec_base/gen_wr/cmp_xwrc_board_spec/cmp_board_common/cmp_xwr_core/WRPC/ep_src_out
add wave -noupdate /main/DUT/inst_spec_base/gen_wr/cmp_xwrc_board_spec/cmp_board_common/cmp_xwr_core/WRPC/ep_src_in
add wave -noupdate /main/DUT/inst_spec_base/gen_wr/cmp_xwrc_board_spec/cmp_board_common/cmp_xwr_core/WRPC/ep_snk_out
add wave -noupdate /main/DUT/inst_spec_base/gen_wr/cmp_xwrc_board_spec/cmp_board_common/cmp_xwr_core/WRPC/ep_snk_in
add wave -noupdate /main/DUT/inst_spec_base/gen_wr/cmp_xwrc_board_spec/cmp_board_common/cmp_xwr_core/WRPC/mux_src_out
add wave -noupdate /main/DUT/inst_spec_base/gen_wr/cmp_xwrc_board_spec/cmp_board_common/cmp_xwr_core/WRPC/mux_src_in
add wave -noupdate /main/DUT/inst_spec_base/gen_wr/cmp_xwrc_board_spec/cmp_board_common/cmp_xwr_core/WRPC/mux_snk_out
add wave -noupdate /main/DUT/inst_spec_base/gen_wr/cmp_xwrc_board_spec/cmp_board_common/cmp_xwr_core/WRPC/mux_snk_in
add wave -noupdate /main/DUT/inst_spec_base/gen_wr/cmp_xwrc_board_spec/cmp_board_common/cmp_xwr_core/WRPC/mux_class
add wave -noupdate /main/DUT/inst_spec_base/gen_wr/cmp_xwrc_board_spec/cmp_board_common/cmp_xwr_core/WRPC/spll_out_locked
add wave -noupdate /main/DUT/inst_spec_base/gen_wr/cmp_xwrc_board_spec/cmp_board_common/cmp_xwr_core/WRPC/dac_dpll_data
add wave -noupdate /main/DUT/inst_spec_base/gen_wr/cmp_xwrc_board_spec/cmp_board_common/cmp_xwr_core/WRPC/dac_dpll_sel
add wave -noupdate /main/DUT/inst_spec_base/gen_wr/cmp_xwrc_board_spec/cmp_board_common/cmp_xwr_core/WRPC/dac_dpll_load_p1
add wave -noupdate /main/DUT/inst_spec_base/gen_wr/cmp_xwrc_board_spec/cmp_board_common/cmp_xwr_core/WRPC/clk_fb
add wave -noupdate /main/DUT/inst_spec_base/gen_wr/cmp_xwrc_board_spec/cmp_board_common/cmp_xwr_core/WRPC/out_enable
TreeUpdate [SetDefaultTree]
WaveRestoreCursors {{Cursor 1} {1471987790 fs} 0}
configure wave -namecolwidth 150
WaveRestoreCursors {{Cursor 1} {25805352090 fs} 0}
configure wave -namecolwidth 339
configure wave -valuecolwidth 100
configure wave -justifyvalue left
configure wave -signalnamewidth 1
......@@ -160,4 +487,4 @@ configure wave -griddelta 40
configure wave -timeline 0
configure wave -timelineunits ns
update
WaveRestoreZoom {1167510930 fs} {3176489070 fs}
WaveRestoreZoom {24701267760 fs} {27643595600 fs}
......@@ -34,6 +34,8 @@ use work.wishbone_pkg.all;
use work.wr_board_pkg.all;
use work.wr_fabric_pkg.all;
use work.fine_delay_pkg.all;
use work.sourceid_spec_fine_delay_top_pkg;
library unisim;
use unisim.vcomponents.all;
......@@ -175,16 +177,7 @@ entity spec_fine_delay_top is
fmc0_prsnt_m2c_n_i : in std_logic;
fmc0_scl_b : inout std_logic;
fmc0_sda_b : inout std_logic
-- synthesis translate_off
;
sim_wb_i : in t_wishbone_slave_in;
sim_wb_o : out t_wishbone_slave_out
-- synthesis translate_on
);
fmc0_sda_b : inout std_logic);
end entity spec_fine_delay_top;
......@@ -282,7 +275,7 @@ architecture arch of spec_fine_delay_top is
-- Interrupts and status
signal fmc0_irq : std_logic;
signal irq_vector : std_logic_vector(0 downto 0);
signal irq_vector : std_logic_vector(4 downto 0);
signal gn4124_access : std_logic;
......@@ -305,7 +298,6 @@ architecture arch of spec_fine_delay_top is
signal fmc0_tdc_start_iodelay_rst : std_logic;
signal fmc0_tdc_start_iodelay_cal : std_logic;
signal fmc0_tdc_start_iodelay_ce : std_logic;
signal fmc0_tdc_start_iodelay_busy : std_logic;
begin -- architecture arch
......@@ -314,9 +306,9 @@ begin -- architecture arch
generic map (
g_VENDOR_ID => x"0000_10DC",
g_DEVICE_ID => x"574f_0001", -- SPEC + 1xFine Delay
g_VERSION => x"0100_0000",
g_VERSION => x"0300_0004",
g_CAPABILITIES => x"0000_0000",
g_COMMIT_ID => (others => '0'))
g_COMMIT_ID => sourceid_spec_fine_delay_top_pkg.sourceid)
port map (
clk_i => clk_sys_62m5,
rst_n_i => rst_sys_62m5_n,
......@@ -331,12 +323,11 @@ begin -- architecture arch
g_WITH_WR => TRUE,
g_WITH_DDR => FALSE,
g_APP_OFFSET => c_METADATA_ADDR,
g_NUM_USER_IRQ => 1,
g_NUM_USER_IRQ => 5,
g_DPRAM_INITF => g_WRPC_INITF,
g_AUX_CLKS => 1,
g_FABRIC_IFACE => plain,
g_SIMULATION => f_int2bool(g_SIMULATION),
g_sim_bypass_gennum => true)
g_SIMULATION => f_int2bool(g_SIMULATION))
port map (
clk_125m_pllref_p_i => clk_125m_pllref_p_i,
clk_125m_pllref_n_i => clk_125m_pllref_n_i,
......@@ -415,13 +406,7 @@ begin -- architecture arch
pps_led_o => pps_led,
link_ok_o => wrabbit_en,
app_wb_o => cnx_master_out(c_WB_MASTER_GENNUM),
app_wb_i => cnx_master_in(c_WB_MASTER_GENNUM)
-- synthesis translate_off
,
sim_wb_i => sim_wb_i,
sim_wb_o => sim_wb_o
-- synthesis translate_on
);
app_wb_i => cnx_master_in(c_WB_MASTER_GENNUM));
------------------------------------------------------------------------------
-- Primary wishbone crossbar
......@@ -485,7 +470,7 @@ begin -- architecture arch
CE => fmc0_tdc_start_iodelay_ce,
RST => fmc0_tdc_start_iodelay_rst,
CLK => fmc0_dcm_clk_ref_0,
BUSY => fmc0_tdc_start_iodelay_busy,
BUSY => open,
ODATAIN => '0',
CAL => fmc0_tdc_start_iodelay_cal,
T => '1',
......@@ -527,7 +512,6 @@ begin -- architecture arch
idelay_rst_o => fmc0_tdc_start_iodelay_rst,
idelay_ce_o => fmc0_tdc_start_iodelay_ce,
idelay_inc_o => fmc0_tdc_start_iodelay_inc,
idelay_busy_i => fmc0_tdc_start_iodelay_busy,
trig_a_i => fmc0_fd_trig_a_i,
tdc_cal_pulse_o => fmc0_fd_tdc_cal_pulse_o,
......
--------------------------------------------------------------------------------
-- CERN (BE-CO-HT)
-- Bi-color LED controller
-- http://www.ohwr.org/projects/svec
--------------------------------------------------------------------------------
--
-- unit name: bicolor_led_ctrl
--
-- author: Matthieu Cattin (matthieu.cattin@cern.ch)
--
-- date: 11-07-2012
--
-- version: 1.0
--
-- description: Bi-color LED controller. It controls a matrix of bi-color LED.
-- The FPGA ouputs for the columns (C) are connected to buffers
-- and serial resistances and then to the LEDs. The FPGA outputs
-- for lines (L) are connected to tri-state buffers and the to
-- the LEDs. The FPGA outputs for lines output enable (L_OEN) are
-- connected to the output enable of the tri-state buffers.
--
-- Example with three lines and two columns:
--
-- |<refresh period>|
--
-- L1/L2/L3 __|--|__|--|__|--|__|--|__|--|__|--|__|--|__|--|__|--|__|--|__|--|__|--|__
--
-- L1_OEN -----|___________|-----|___________|-----|___________|-----|___________|--
--
-- L2_OEN _____|-----|___________|-----|___________|-----|___________|-----|________
--
-- L3_OEN ___________|-----|___________|-----|___________|-----|___________|-----|__
--
-- Cn __|--|__|--|__|--|_________________|-----------------|--|__|--|__|--|__|--
--
-- LED Ln/Cn OFF | color_1 | color_2 | both_colors |
--
--
-- dependencies:
--
--------------------------------------------------------------------------------
-- GNU LESSER GENERAL PUBLIC LICENSE
--------------------------------------------------------------------------------
-- This source file is free software; you can redistribute it and/or modify it
-- under the terms of the GNU Lesser General Public License as published by the
-- Free Software Foundation; either version 2.1 of the License, or (at your
-- option) any later version. This source is distributed in the hope that it
-- will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty
-- of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
-- See the GNU Lesser General Public License for more details. You should have
-- received a copy of the GNU Lesser General Public License along with this
-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html
--------------------------------------------------------------------------------
-- last changes: see log.
--------------------------------------------------------------------------------
-- TODO: -
--------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
library work;
use work.bicolor_led_ctrl_pkg.all;
entity bicolor_led_ctrl is
generic(
g_NB_COLUMN : natural := 4;
g_NB_LINE : natural := 2;
g_CLK_FREQ : natural := 125000000; -- in Hz
g_REFRESH_RATE : natural := 250 -- in Hz
);
port
(
rst_n_i : in std_logic;
clk_i : in std_logic;
led_intensity_i : in std_logic_vector(6 downto 0);
led_state_i : in std_logic_vector((g_NB_LINE * g_NB_COLUMN * 2) - 1 downto 0);
column_o : out std_logic_vector(g_NB_COLUMN - 1 downto 0);
line_o : out std_logic_vector(g_NB_LINE - 1 downto 0);
line_oen_o : out std_logic_vector(g_NB_LINE - 1 downto 0)
);
end bicolor_led_ctrl;
architecture rtl of bicolor_led_ctrl is
------------------------------------------------------------------------------
-- Components declaration
------------------------------------------------------------------------------
------------------------------------------------------------------------------
-- Constants declaration
------------------------------------------------------------------------------
constant c_REFRESH_CNT_INIT : natural := natural(g_CLK_FREQ/(2 * g_NB_LINE * g_REFRESH_RATE)) - 1;
constant c_REFRESH_CNT_NB_BITS : natural := log2_ceil(c_REFRESH_CNT_INIT);
constant c_LINE_OEN_CNT_NB_BITS : natural := log2_ceil(g_NB_LINE);
------------------------------------------------------------------------------
-- Signals declaration
------------------------------------------------------------------------------
signal refresh_rate_cnt : unsigned(c_REFRESH_CNT_NB_BITS - 1 downto 0);
signal refresh_rate : std_logic;
signal line_ctrl : std_logic;
signal intensity_ctrl_cnt : unsigned(c_REFRESH_CNT_NB_BITS - 1 downto 0);
signal intensity_ctrl : std_logic;
signal line_oen_cnt : unsigned(c_LINE_OEN_CNT_NB_BITS - 1 downto 0);
signal line_oen : std_logic_vector(2**c_LINE_OEN_CNT_NB_BITS - 1 downto 0);
signal led_state : std_logic_vector((g_NB_LINE * g_NB_COLUMN) -1 downto 0);
begin
------------------------------------------------------------------------------
-- Refresh rate counter
------------------------------------------------------------------------------
p_refresh_rate_cnt : process (clk_i)
begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
refresh_rate_cnt <= (others => '0');
refresh_rate <= '0';
elsif refresh_rate_cnt = 0 then
refresh_rate_cnt <= to_unsigned(c_REFRESH_CNT_INIT, c_REFRESH_CNT_NB_BITS);
refresh_rate <= '1';
else
refresh_rate_cnt <= refresh_rate_cnt - 1;
refresh_rate <= '0';
end if;
end if;
end process p_refresh_rate_cnt;
------------------------------------------------------------------------------
-- Intensity control
------------------------------------------------------------------------------
p_intensity_ctrl_cnt : process (clk_i)
begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
intensity_ctrl_cnt <= (others => '0');
elsif refresh_rate = '1' then
intensity_ctrl_cnt <= to_unsigned(natural(c_REFRESH_CNT_INIT/100) * to_integer(unsigned(led_intensity_i)), c_REFRESH_CNT_NB_BITS);
else
intensity_ctrl_cnt <= intensity_ctrl_cnt - 1;
end if;
end if;
end process p_intensity_ctrl_cnt;
p_intensity_ctrl : process (clk_i)
begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
intensity_ctrl <= '0';
elsif refresh_rate = '1' then
intensity_ctrl <= '1';
elsif intensity_ctrl_cnt = 0 then
intensity_ctrl <= '0';
end if;
end if;
end process p_intensity_ctrl;
------------------------------------------------------------------------------
-- Lines ouput
------------------------------------------------------------------------------
p_line_ctrl : process (clk_i)
begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
line_ctrl <= '0';
elsif refresh_rate = '1' then
line_ctrl <= not(line_ctrl);
end if;
end if;
end process p_line_ctrl;
f_line_o : for I in 0 to g_NB_LINE - 1 generate
line_o(I) <= line_ctrl and intensity_ctrl;
end generate f_line_o;
------------------------------------------------------------------------------
-- Lines output enable
------------------------------------------------------------------------------
p_line_oen_cnt : process (clk_i)
begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
line_oen_cnt <= (others => '0');
elsif line_ctrl = '1' and refresh_rate = '1' then
if line_oen_cnt = 0 then
line_oen_cnt <= to_unsigned(g_NB_LINE - 1, c_LINE_OEN_CNT_NB_BITS);
else
line_oen_cnt <= line_oen_cnt - 1;
end if;
end if;
end if;
end process p_line_oen_cnt;
p_line_oen_decode : process(line_oen_cnt)
variable v_onehot : std_logic_vector((2**line_oen_cnt'length)-1 downto 0);
variable v_index : integer range 0 to (2**line_oen_cnt'length)-1;
begin
v_onehot := (others => '0');
v_index := 0;
for i in line_oen_cnt'range loop
if (line_oen_cnt(i) = '1') then
v_index := 2*v_index+1;
else
v_index := 2*v_index;
end if;
end loop;
v_onehot(v_index) := '1';
line_oen <= v_onehot;
end process p_line_oen_decode;
line_oen_o <= line_oen(line_oen_o'left downto 0);
------------------------------------------------------------------------------
-- Columns output
------------------------------------------------------------------------------
f_led_state : for I in 0 to (g_NB_COLUMN * g_NB_LINE) - 1 generate
led_state(I) <= '0' when led_state_i(2 * I + 1 downto 2 * I) = c_LED_RED else
'1' when led_state_i(2 * I + 1 downto 2 * I) = c_LED_GREEN else
(line_ctrl and intensity_ctrl) when led_state_i(2 * I + 1 downto 2 * I) = c_LED_OFF else
not(line_ctrl and intensity_ctrl) when led_state_i(2 * I + 1 downto 2 * I) = c_LED_RED_GREEN else '0';
end generate f_led_state;
f_column_o : for C in 0 to g_NB_COLUMN - 1 generate
column_o(C) <= led_state(g_NB_COLUMN * to_integer(line_oen_cnt) + C);
end generate f_column_o;
end rtl;
--------------------------------------------------------------------------------
-- CERN (BE-CO-HT)
-- Bi-color LED controller package
-- http://www.ohwr.org/projects/svec
--------------------------------------------------------------------------------
--
-- unit name: bicolor_led_ctrl_pkg
--
-- author: Matthieu Cattin (matthieu.cattin@cern.ch)
--
-- date: 11-07-2012
--
-- version: 1.0
--
-- description: Package for Bi-color LED controller.
--
-- dependencies:
--
--------------------------------------------------------------------------------
-- GNU LESSER GENERAL PUBLIC LICENSE
--------------------------------------------------------------------------------
-- This source file is free software; you can redistribute it and/or modify it
-- under the terms of the GNU Lesser General Public License as published by the
-- Free Software Foundation; either version 2.1 of the License, or (at your
-- option) any later version. This source is distributed in the hope that it
-- will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty
-- of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
-- See the GNU Lesser General Public License for more details. You should have
-- received a copy of the GNU Lesser General Public License along with this
-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html
--------------------------------------------------------------------------------
-- last changes: see log.
--------------------------------------------------------------------------------
-- TODO: -
--------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
package bicolor_led_ctrl_pkg is
------------------------------------------------------------------------------
-- Constants declaration
------------------------------------------------------------------------------
constant c_LED_RED : std_logic_vector(1 downto 0) := "10";
constant c_LED_GREEN : std_logic_vector(1 downto 0) := "01";
constant c_LED_RED_GREEN : std_logic_vector(1 downto 0) := "11";
constant c_LED_OFF : std_logic_vector(1 downto 0) := "00";
------------------------------------------------------------------------------
-- Functions declaration
------------------------------------------------------------------------------
function log2_ceil(N : natural) return positive;
------------------------------------------------------------------------------
-- Components declaration
------------------------------------------------------------------------------
component bicolor_led_ctrl
generic(
g_NB_COLUMN : natural := 4;
g_NB_LINE : natural := 2;
g_CLK_FREQ : natural := 125000000; -- in Hz
g_REFRESH_RATE : natural := 250 -- in Hz
);
port
(
rst_n_i : in std_logic;
clk_i : in std_logic;
led_intensity_i : in std_logic_vector(6 downto 0);
led_state_i : in std_logic_vector((g_NB_LINE * g_NB_COLUMN * 2) - 1 downto 0);
column_o : out std_logic_vector(g_NB_COLUMN - 1 downto 0);
line_o : out std_logic_vector(g_NB_LINE - 1 downto 0);
line_oen_o : out std_logic_vector(g_NB_LINE - 1 downto 0)
);
end component;
end bicolor_led_ctrl_pkg;
package body bicolor_led_ctrl_pkg is
------------------------------------------------------------------------------
-- Function : Returns log of 2 of a natural number
------------------------------------------------------------------------------
function log2_ceil(N : natural) return positive is
begin
if N <= 2 then
return 1;
elsif N mod 2 = 0 then
return 1 + log2_ceil(N/2);
else
return 1 + log2_ceil((N+1)/2);
end if;
end;
end bicolor_led_ctrl_pkg;
......@@ -39,6 +39,7 @@ use work.wishbone_pkg.all;
use work.wr_board_pkg.all;
use work.wr_fabric_pkg.all;
use work.fine_delay_pkg.all;
use work.sourceid_svec_fine_delay_top_pkg;
library unisim;
use unisim.vcomponents.all;
......@@ -413,9 +414,9 @@ begin -- architecture arch
generic map (
g_VENDOR_ID => x"0000_10DC",
g_DEVICE_ID => x"574f_0002", -- SVEC + 2xFineDelay
g_VERSION => x"0100_0000",
g_VERSION => x"0300_0004",
g_CAPABILITIES => x"0000_0000",
g_COMMIT_ID => (others => '0'))
g_COMMIT_ID => sourceid_svec_fine_delay_top_pkg.sourceid)
port map (
clk_i => clk_sys_62m5,
rst_n_i => rst_sys_62m5_n,
......@@ -667,7 +668,7 @@ begin -- architecture arch
idelay_ce_o => fd0_tdc_start_iodelay_ce,
idelay_inc_o => fd0_tdc_start_iodelay_inc,
idelay_busy_i => '0',
wb_adr_i => cnx_slave_in(c_WB_SLAVE_FD0).adr,
wb_dat_i => cnx_slave_in(c_WB_SLAVE_FD0).dat,
wb_dat_o => cnx_slave_out(c_WB_SLAVE_FD0).dat,
......@@ -899,8 +900,8 @@ begin -- architecture arch
svec_led(9) <= '0';
-- Front panel IO configuration
fp_gpio1_b <= pps;
fp_gpio2_b <= '0';
fp_gpio1_b <= tm_clk_aux_locked(0);
fp_gpio2_b <= tm_clk_aux_locked(1);
fp_term_en_o <= (others => '0');
fp_gpio1_a2b_o <= '1';
......
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