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FMC DEL 1ns 4cha
Commit a21d0b54 authored by Tomasz Wlostowski's avatar Tomasz Wlostowski
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[top/syn]/svec/wr: SVEC top level with new VME Core, working WR Core and Etherbone

parent 57dd2715
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Showing with 638 additions and 615 deletions
hdl/syn/svec/wr/Manifest.py
View file @ a21d0b54
......@@ -9,4 +9,5 @@ syn_package = "fgg900"
syn_top = "svec_top"
syn_project = "svec_fine_delay.xise"
files = [ "wrc.ram" ]
modules = { "local" : [ "../../../top/svec/wr", "../../../platform" ] }
hdl/syn/svec/wr/svec_fine_delay.xise
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hdl/top/svec/wr/Manifest.py
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files = [ "svec_top.vhd", "svec_top.ucf", "xvme64x_core.vhd", "spec_serial_dac.vhd" ]
files = [ "svec_top.vhd", "svec_top.ucf", "xvme64x_core.vhd" ]
fetchto = "../../../ip_cores"
modules = {
"local" : ["../../../rtl", "../../../platform", "../../../ip_cores/vme64x-core" ],
"git" : [ "git://ohwr.org/hdl-core-lib/wr-cores.git::wishbonized" ]
# "svn" : [ "http://svn.ohwr.org/vme64x-core/trunk/hdl/vme64x-core/rtl" ]
"local" : ["../../../rtl", "../../../platform" ],
"git" : [ "git://ohwr.org/hdl-core-lib/wr-cores.git",
"git://ohwr.org/hdl-core-lib/etherbone-core.git" ],
"svn" : [ "http://svn.ohwr.org/vme64x-core/trunk/hdl/vme64x-core/rtl" ]
}
hdl/top/svec/wr/svec_top.ucf
View file @ a21d0b54
......@@ -360,8 +360,8 @@ NET "fd1_clk_ref_p_i" TNM_NET = fd1_clk_ref_p_i;
TIMESPEC TS_fd1_clk_ref_p_i = PERIOD "fd1_clk_ref_p_i" 8 ns HIGH 50%;
NET "fd1_clk_ref_n_i" TNM_NET = fd1_clk_ref_n_i;
TIMESPEC TS_fd1_clk_ref_n_i = PERIOD "fd1_clk_ref_n_i" 8 ns HIGH 50%;
NET "gen_with_phy.U_GTP/ch0_gtp_clkout_int<1>" TNM_NET = gen_with_phy.U_GTP/ch0_gtp_clkout_int<1>;
TIMESPEC TS_gen_with_phy_U_GTP_ch0_gtp_clkout_int_1_ = PERIOD "gen_with_phy.U_GTP/ch0_gtp_clkout_int<1>" 8 ns HIGH 50%;
#NET "gen_with_phy.U_GTP/ch0_gtp_clkout_int<1>" TNM_NET = gen_with_phy.U_GTP/ch0_gtp_clkout_int<1>;
#TIMESPEC TS_gen_with_phy_U_GTP_ch0_gtp_clkout_int_1_ = PERIOD "gen_with_phy.U_GTP/ch0_gtp_clkout_int<1>" 8 ns HIGH 50%;
NET "gen_with_phy.U_GTP/ch1_gtp_clkout_int<1>" TNM_NET = gen_with_phy.U_GTP/ch1_gtp_clkout_int<1>;
TIMESPEC TS_gen_with_phy_U_GTP_ch1_gtp_clkout_int_1_ = PERIOD "gen_with_phy.U_GTP/ch1_gtp_clkout_int<1>" 8 ns HIGH 50%;
......
hdl/top/svec/wr/svec_top.vhd
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hdl/top/svec/wr/xvme64x_core.vhd
View file @ a21d0b54
......@@ -8,6 +8,8 @@ entity xvme64x_core is
clk_i : in std_logic;
rst_n_i : in std_logic;
rst_n_o : out std_logic;
VME_AS_n_i : in std_logic;
VME_RST_n_i : in std_logic;
VME_WRITE_n_i : in std_logic;
......@@ -18,13 +20,15 @@ entity xvme64x_core is
VME_DTACK_n_o : out std_logic;
VME_RETRY_n_o : out std_logic;
VME_RETRY_OE_o : out std_logic;
VME_LWORD_n_b : inout std_logic;
VME_ADDR_b : inout std_logic_vector(31 downto 1);
VME_DATA_b : inout std_logic_vector(31 downto 0);
VME_BBSY_n_i : in std_logic;
VME_LWORD_n_b_i : in std_logic;
VME_LWORD_n_b_o : out std_logic;
VME_ADDR_b_i : in std_logic_vector(31 downto 1);
VME_ADDR_b_o : out std_logic_vector(31 downto 1);
VME_DATA_b_i : in std_logic_vector(31 downto 0);
VME_DATA_b_o : out std_logic_vector(31 downto 0);
VME_IRQ_n_o : out std_logic_vector(6 downto 0);
VME_IACK_n_i : in std_logic;
VME_IACKIN_n_i : in std_logic;
VME_IACK_n_i : in std_logic;
VME_IACKOUT_n_o : out std_logic;
VME_DTACK_OE_o : out std_logic;
VME_DATA_DIR_o : out std_logic;
......@@ -35,7 +39,8 @@ entity xvme64x_core is
master_o : out t_wishbone_master_out;
master_i : in t_wishbone_master_in;
irq_i : in std_logic
irq_i : in std_logic;
irq_ack_o : out std_logic
);
......@@ -44,8 +49,14 @@ end xvme64x_core;
architecture wrapper of xvme64x_core is
component VME64xCore_Top
generic(
g_width : integer := 32;
g_addr_width : integer := 64;
g_CRAM_SIZE : integer := 1024
);
port (
clk_i : in std_logic;
reset_o : out std_logic;
VME_AS_n_i : in std_logic;
VME_RST_n_i : in std_logic;
VME_WRITE_n_i : in std_logic;
......@@ -55,46 +66,51 @@ architecture wrapper of xvme64x_core is
VME_BERR_o : out std_logic;
VME_DTACK_n_o : out std_logic;
VME_RETRY_n_o : out std_logic;
VME_RETRY_OE_o : out std_logic;
VME_LWORD_n_b : inout std_logic;
VME_ADDR_b : inout std_logic_vector(31 downto 1);
VME_DATA_b : inout std_logic_vector(31 downto 0);
VME_BBSY_n_i : in std_logic;
VME_LWORD_n_b_i : in std_logic;
VME_LWORD_n_b_o : out std_logic;
VME_ADDR_b_i : in std_logic_vector(31 downto 1);
VME_ADDR_b_o : out std_logic_vector(31 downto 1);
VME_DATA_b_i : in std_logic_vector(31 downto 0);
VME_DATA_b_o : out std_logic_vector(31 downto 0);
VME_IRQ_n_o : out std_logic_vector(6 downto 0);
VME_IACK_n_i : in std_logic;
VME_IACKIN_n_i : in std_logic;
VME_IACK_n_i : in std_logic;
VME_IACKOUT_n_o : out std_logic;
VME_DTACK_OE_o : out std_logic;
VME_DATA_DIR_o : out std_logic;
VME_DATA_OE_N_o : out std_logic;
VME_ADDR_DIR_o : out std_logic;
VME_ADDR_OE_N_o : out std_logic;
RST_i : in std_logic;
DAT_i : in std_logic_vector(63 downto 0);
DAT_o : out std_logic_vector(63 downto 0);
ADR_o : out std_logic_vector(63 downto 0);
VME_RETRY_OE_o : out std_logic;
DAT_i : in std_logic_vector(g_width - 1 downto 0);
DAT_o : out std_logic_vector(g_width - 1 downto 0);
ADR_o : out std_logic_vector(g_addr_width - 1 downto 0);
CYC_o : out std_logic;
ERR_i : in std_logic;
LOCK_o : out std_logic;
RTY_i : in std_logic;
SEL_o : out std_logic_vector(7 downto 0);
SEL_o : out std_logic_vector(g_width / 8 - 1 downto 0);
STB_o : out std_logic;
ACK_i : in std_logic;
WE_o : out std_logic;
STALL_i : in std_logic;
IRQ_i : in std_logic);
INT_ack : out std_logic;
IRQ_i : in std_logic;
leds : out std_logic_vector(7 downto 0));
end component;
signal rst : std_logic;
signal dummy_adr, dummy_dat, dummy_sel : std_logic_vector(63 downto 0);
signal rst_in, rst_out : std_logic;
signal dat_out, dat_in : std_logic_vector(31 downto 0);
signal adr_out : std_logic_vector(63 downto 0);
begin -- wrapper
rst <= not rst_n_i;
rst_in <= not rst_n_i;
rst_n_o <= rst_n_i and (not rst_out);
U_Wrapped_VME : VME64xCore_Top
port map (
clk_i => clk_i,
reset_o => rst_out,
VME_AS_n_i => VME_AS_n_i,
VME_RST_n_i => VME_RST_n_i,
VME_WRITE_n_i => VME_WRITE_n_i,
......@@ -105,37 +121,41 @@ begin -- wrapper
VME_DTACK_n_o => VME_DTACK_n_o,
VME_RETRY_n_o => VME_RETRY_n_o,
VME_RETRY_OE_o => VME_RETRY_OE_o,
VME_LWORD_n_b => VME_LWORD_n_b,
VME_ADDR_b => VME_ADDR_b,
VME_DATA_b => VME_DATA_b,
VME_BBSY_n_i => VME_BBSY_n_i,
VME_LWORD_n_b_i => VME_LWORD_n_b_i,
VME_LWORD_n_b_o => VME_LWORD_n_b_o,
VME_ADDR_b_i => VME_ADDR_b_i,
VME_ADDR_b_o => VME_ADDR_b_o,
VME_DATA_b_i => VME_DATA_b_i,
VME_DATA_b_o => VME_DATA_b_o,
VME_IRQ_n_o => VME_IRQ_n_o,
VME_IACK_n_i => VME_IACK_n_i,
VME_IACKIN_n_i => VME_IACKIN_n_i,
VME_IACK_n_i => VME_IACK_n_i,
VME_IACKOUT_n_o => VME_IACKOUT_n_o,
VME_DTACK_OE_o => VME_DTACK_OE_o,
VME_DATA_DIR_o => VME_DATA_DIR_o,
VME_DATA_OE_N_o => VME_DATA_OE_N_o,
VME_ADDR_DIR_o => VME_ADDR_DIR_o,
VME_ADDR_OE_N_o => VME_ADDR_OE_N_o,
RST_i => rst_n_i,
DAT_i(31 downto 0) => master_i.dat,
DAT_i(63 downto 32) => x"00000000",
DAT_o(31 downto 0) => master_o.dat,
DAT_o(63 downto 32) => dummy_dat(63 downto 32),
ADR_o(31 downto 0) => master_o.adr,
ADR_o(63 downto 32) => dummy_adr(63 downto 32),
DAT_i => dat_in,
DAT_o => dat_out,
ADR_o => adr_out,
CYC_o => master_o.cyc,
ERR_i => master_i.err,
LOCK_o => open,
RTY_i => master_i.rty,
SEL_o(3 downto 0) => master_o.sel,
SEL_o(7 downto 4) => dummy_sel(7 downto 4),
SEL_o => open,
STB_o => master_o.stb,
ACK_i => master_i.ack,
WE_o => master_o.we,
STALL_i => master_i.stall,
IRQ_i => irq_i);
IRQ_i => irq_i,
INT_ack => irq_ack_o);
master_o.dat <= dat_out(31 downto 0);
master_o.sel <= (others => '1');
master_o.adr <= adr_out(29 downto 0) & "00";
dat_in <= master_i.dat;
end wrapper;
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