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FMC DEL 1ns 4cha
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FMC DEL 1ns 4cha
Commits
a21d0b54
Commit
a21d0b54
authored
Aug 13, 2012
by
Tomasz Wlostowski
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[top/syn]/svec/wr: SVEC top level with new VME Core, working WR Core and Etherbone
parent
57dd2715
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6 changed files
with
638 additions
and
615 deletions
+638
-615
Manifest.py
hdl/syn/svec/wr/Manifest.py
+1
-0
svec_fine_delay.xise
hdl/syn/svec/wr/svec_fine_delay.xise
+338
-268
Manifest.py
hdl/top/svec/wr/Manifest.py
+5
-4
svec_top.ucf
hdl/top/svec/wr/svec_top.ucf
+2
-2
svec_top.vhd
hdl/top/svec/wr/svec_top.vhd
+164
-233
xvme64x_core.vhd
hdl/top/svec/wr/xvme64x_core.vhd
+128
-108
No files found.
hdl/syn/svec/wr/Manifest.py
View file @
a21d0b54
...
@@ -9,4 +9,5 @@ syn_package = "fgg900"
...
@@ -9,4 +9,5 @@ syn_package = "fgg900"
syn_top
=
"svec_top"
syn_top
=
"svec_top"
syn_project
=
"svec_fine_delay.xise"
syn_project
=
"svec_fine_delay.xise"
files
=
[
"wrc.ram"
]
modules
=
{
"local"
:
[
"../../../top/svec/wr"
,
"../../../platform"
]
}
modules
=
{
"local"
:
[
"../../../top/svec/wr"
,
"../../../platform"
]
}
hdl/syn/svec/wr/svec_fine_delay.xise
View file @
a21d0b54
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hdl/top/svec/wr/Manifest.py
View file @
a21d0b54
files
=
[
"svec_top.vhd"
,
"svec_top.ucf"
,
"xvme64x_core.vhd"
,
"spec_serial_dac.vhd"
]
files
=
[
"svec_top.vhd"
,
"svec_top.ucf"
,
"xvme64x_core.vhd"
]
fetchto
=
"../../../ip_cores"
fetchto
=
"../../../ip_cores"
modules
=
{
modules
=
{
"local"
:
[
"../../../rtl"
,
"../../../platform"
,
"../../../ip_cores/vme64x-core"
],
"local"
:
[
"../../../rtl"
,
"../../../platform"
],
"git"
:
[
"git://ohwr.org/hdl-core-lib/wr-cores.git::wishbonized"
]
"git"
:
[
"git://ohwr.org/hdl-core-lib/wr-cores.git"
,
# "svn" : [ "http://svn.ohwr.org/vme64x-core/trunk/hdl/vme64x-core/rtl" ]
"git://ohwr.org/hdl-core-lib/etherbone-core.git"
],
"svn"
:
[
"http://svn.ohwr.org/vme64x-core/trunk/hdl/vme64x-core/rtl"
]
}
}
hdl/top/svec/wr/svec_top.ucf
View file @
a21d0b54
...
@@ -360,8 +360,8 @@ NET "fd1_clk_ref_p_i" TNM_NET = fd1_clk_ref_p_i;
...
@@ -360,8 +360,8 @@ NET "fd1_clk_ref_p_i" TNM_NET = fd1_clk_ref_p_i;
TIMESPEC TS_fd1_clk_ref_p_i = PERIOD "fd1_clk_ref_p_i" 8 ns HIGH 50%;
TIMESPEC TS_fd1_clk_ref_p_i = PERIOD "fd1_clk_ref_p_i" 8 ns HIGH 50%;
NET "fd1_clk_ref_n_i" TNM_NET = fd1_clk_ref_n_i;
NET "fd1_clk_ref_n_i" TNM_NET = fd1_clk_ref_n_i;
TIMESPEC TS_fd1_clk_ref_n_i = PERIOD "fd1_clk_ref_n_i" 8 ns HIGH 50%;
TIMESPEC TS_fd1_clk_ref_n_i = PERIOD "fd1_clk_ref_n_i" 8 ns HIGH 50%;
NET "gen_with_phy.U_GTP/ch0_gtp_clkout_int<1>" TNM_NET = gen_with_phy.U_GTP/ch0_gtp_clkout_int<1>;
#
NET "gen_with_phy.U_GTP/ch0_gtp_clkout_int<1>" TNM_NET = gen_with_phy.U_GTP/ch0_gtp_clkout_int<1>;
TIMESPEC TS_gen_with_phy_U_GTP_ch0_gtp_clkout_int_1_ = PERIOD "gen_with_phy.U_GTP/ch0_gtp_clkout_int<1>" 8 ns HIGH 50%;
#
TIMESPEC TS_gen_with_phy_U_GTP_ch0_gtp_clkout_int_1_ = PERIOD "gen_with_phy.U_GTP/ch0_gtp_clkout_int<1>" 8 ns HIGH 50%;
NET "gen_with_phy.U_GTP/ch1_gtp_clkout_int<1>" TNM_NET = gen_with_phy.U_GTP/ch1_gtp_clkout_int<1>;
NET "gen_with_phy.U_GTP/ch1_gtp_clkout_int<1>" TNM_NET = gen_with_phy.U_GTP/ch1_gtp_clkout_int<1>;
TIMESPEC TS_gen_with_phy_U_GTP_ch1_gtp_clkout_int_1_ = PERIOD "gen_with_phy.U_GTP/ch1_gtp_clkout_int<1>" 8 ns HIGH 50%;
TIMESPEC TS_gen_with_phy_U_GTP_ch1_gtp_clkout_int_1_ = PERIOD "gen_with_phy.U_GTP/ch1_gtp_clkout_int<1>" 8 ns HIGH 50%;
...
...
hdl/top/svec/wr/svec_top.vhd
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a21d0b54
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hdl/top/svec/wr/xvme64x_core.vhd
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a21d0b54
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