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FMC DEL 1ns 4cha
Commit a21d0b54 authored by Tomasz Wlostowski's avatar Tomasz Wlostowski
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[top/syn]/svec/wr: SVEC top level with new VME Core, working WR Core and Etherbone

parent 57dd2715
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Showing with 638 additions and 615 deletions
hdl/syn/svec/wr/Manifest.py
View file @ a21d0b54
......@@ -9,4 +9,5 @@ syn_package = "fgg900"
syn_top = "svec_top"
syn_project = "svec_fine_delay.xise"
files = [ "wrc.ram" ]
modules = { "local" : [ "../../../top/svec/wr", "../../../platform" ] }
hdl/syn/svec/wr/svec_fine_delay.xise
View file @ a21d0b54
......@@ -9,7 +9,7 @@
<!-- along with the project source files, is sufficient to open and -->
<!-- implement in ISE Project Navigator. -->
<!-- -->
<!-- Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved. -->
<!-- Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved. -->
</header>
<autoManagedFiles>
......@@ -161,6 +161,7 @@
<property xil_pn:name="Maximum Signal Name Length" xil_pn:value="20" xil_pn:valueState="default"/>
<property xil_pn:name="Move First Flip-Flop Stage" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Move Last Flip-Flop Stage" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="MultiBoot: Insert IPROG CMD in the Bitfile spartan6" xil_pn:value="Enable" xil_pn:valueState="default"/>
<property xil_pn:name="MultiBoot: Next Configuration Mode spartan6" xil_pn:value="001" xil_pn:valueState="default"/>
<property xil_pn:name="MultiBoot: Starting Address for Golden Configuration spartan6" xil_pn:value="0x00000000" xil_pn:valueState="default"/>
<property xil_pn:name="MultiBoot: Starting Address for Next Configuration spartan6" xil_pn:value="0x00000000" xil_pn:valueState="default"/>
......@@ -340,383 +341,380 @@
<files>
<file xil_pn:name="../../../top/svec/wr/svec_top.ucf" xil_pn:type="FILE_UCF">
<association xil_pn:name="Implementation" xil_pn:seqID="1"/>
<association xil_pn:name="Implementation" xil_pn:seqID="2"/>
</file>
<file xil_pn:name="../../../platform/chipscope_icon.ngc" xil_pn:type="FILE_NGC">
<association xil_pn:name="Implementation" xil_pn:seqID="2"/>
<association xil_pn:name="Implementation" xil_pn:seqID="3"/>
</file>
<file xil_pn:name="../../../platform/chipscope_ila.ngc" xil_pn:type="FILE_NGC">
<association xil_pn:name="Implementation" xil_pn:seqID="3"/>
<association xil_pn:name="Implementation" xil_pn:seqID="4"/>
</file>
<file xil_pn:name="../../../../../../wr-repos/wr-cores/platform/xilinx/chipscope/chipscope_icon.ngc" xil_pn:type="FILE_NGC">
<association xil_pn:name="Implementation" xil_pn:seqID="4"/>
<association xil_pn:name="Implementation" xil_pn:seqID="5"/>
</file>
<file xil_pn:name="../../../../../../wr-repos/wr-cores/platform/xilinx/chipscope/chipscope_ila.ngc" xil_pn:type="FILE_NGC">
<association xil_pn:name="Implementation" xil_pn:seqID="5"/>
<association xil_pn:name="Implementation" xil_pn:seqID="6"/>
</file>
<file xil_pn:name="../../../../../../wr-repos/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_v4_1_xst_comp.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="6"/>
<association xil_pn:name="Implementation" xil_pn:seqID="7"/>
<library xil_pn:name="blk_mem_gen_v4_1"/>
</file>
<file xil_pn:name="../../../../../../wr-repos/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_v4_1_defaults.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="7"/>
<association xil_pn:name="Implementation" xil_pn:seqID="8"/>
<library xil_pn:name="blk_mem_gen_v4_1"/>
</file>
<file xil_pn:name="../../../../../../wr-repos/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_v4_1_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="8"/>
<association xil_pn:name="Implementation" xil_pn:seqID="9"/>
<library xil_pn:name="blk_mem_gen_v4_1"/>
</file>
<file xil_pn:name="../../../../../../wr-repos/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_getinit_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="9"/>
<association xil_pn:name="Implementation" xil_pn:seqID="10"/>
<library xil_pn:name="blk_mem_gen_v4_1"/>
</file>
<file xil_pn:name="../../../../../../wr-repos/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_min_area_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="10"/>
<association xil_pn:name="Implementation" xil_pn:seqID="11"/>
<library xil_pn:name="blk_mem_gen_v4_1"/>
</file>
<file xil_pn:name="../../../../../../wr-repos/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_bindec.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="11"/>
<association xil_pn:name="Implementation" xil_pn:seqID="12"/>
<library xil_pn:name="blk_mem_gen_v4_1"/>
</file>
<file xil_pn:name="../../../../../../wr-repos/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_mux.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="12"/>
<association xil_pn:name="Implementation" xil_pn:seqID="13"/>
<library xil_pn:name="blk_mem_gen_v4_1"/>
</file>
<file xil_pn:name="../../../../../../wr-repos/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_wrapper_s6.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="13"/>
<association xil_pn:name="Implementation" xil_pn:seqID="14"/>
<library xil_pn:name="blk_mem_gen_v4_1"/>
</file>
<file xil_pn:name="../../../../../../wr-repos/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_wrapper_s6_init.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="14"/>
<association xil_pn:name="Implementation" xil_pn:seqID="15"/>
<library xil_pn:name="blk_mem_gen_v4_1"/>
</file>
<file xil_pn:name="../../../../../../wr-repos/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_wrapper_s3adsp.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="15"/>
<association xil_pn:name="Implementation" xil_pn:seqID="16"/>
<library xil_pn:name="blk_mem_gen_v4_1"/>
</file>
<file xil_pn:name="../../../../../../wr-repos/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_wrapper_s3adsp_init.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="16"/>
<association xil_pn:name="Implementation" xil_pn:seqID="17"/>
<library xil_pn:name="blk_mem_gen_v4_1"/>
</file>
<file xil_pn:name="../../../../../../wr-repos/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_wrapper_s3a.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="17"/>
<association xil_pn:name="Implementation" xil_pn:seqID="18"/>
<library xil_pn:name="blk_mem_gen_v4_1"/>
</file>
<file xil_pn:name="../../../../../../wr-repos/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_wrapper_s3a_init.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="18"/>
<association xil_pn:name="Implementation" xil_pn:seqID="19"/>
<library xil_pn:name="blk_mem_gen_v4_1"/>
</file>
<file xil_pn:name="../../../../../../wr-repos/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_wrapper_v6.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="19"/>
<association xil_pn:name="Implementation" xil_pn:seqID="20"/>
<library xil_pn:name="blk_mem_gen_v4_1"/>
</file>
<file xil_pn:name="../../../../../../wr-repos/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_wrapper_v6_init.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="20"/>
<association xil_pn:name="Implementation" xil_pn:seqID="21"/>
<library xil_pn:name="blk_mem_gen_v4_1"/>
</file>
<file xil_pn:name="../../../../../../wr-repos/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_wrapper_v5.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="21"/>
<association xil_pn:name="Implementation" xil_pn:seqID="22"/>
<library xil_pn:name="blk_mem_gen_v4_1"/>
</file>
<file xil_pn:name="../../../../../../wr-repos/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_wrapper_v5_init.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="22"/>
<association xil_pn:name="Implementation" xil_pn:seqID="23"/>
<library xil_pn:name="blk_mem_gen_v4_1"/>
</file>
<file xil_pn:name="../../../../../../wr-repos/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_wrapper_v4.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="23"/>
<association xil_pn:name="Implementation" xil_pn:seqID="24"/>
<library xil_pn:name="blk_mem_gen_v4_1"/>
</file>
<file xil_pn:name="../../../../../../wr-repos/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_wrapper_v4_init.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="24"/>
<association xil_pn:name="Implementation" xil_pn:seqID="25"/>
<library xil_pn:name="blk_mem_gen_v4_1"/>
</file>
<file xil_pn:name="../../../../../../wr-repos/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_wrapper_s3.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="25"/>
<association xil_pn:name="Implementation" xil_pn:seqID="26"/>
<library xil_pn:name="blk_mem_gen_v4_1"/>
</file>
<file xil_pn:name="../../../../../../wr-repos/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_wrapper_s3_init.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="26"/>
<association xil_pn:name="Implementation" xil_pn:seqID="27"/>
<library xil_pn:name="blk_mem_gen_v4_1"/>
</file>
<file xil_pn:name="../../../../../../wr-repos/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_width.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="27"/>
<association xil_pn:name="Implementation" xil_pn:seqID="28"/>
<library xil_pn:name="blk_mem_gen_v4_1"/>
</file>
<file xil_pn:name="../../../../../../wr-repos/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_generic_cstr.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="28"/>
<association xil_pn:name="Implementation" xil_pn:seqID="29"/>
<library xil_pn:name="blk_mem_gen_v4_1"/>
</file>
<file xil_pn:name="../../../../../../wr-repos/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_ecc_encoder.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="29"/>
<association xil_pn:name="Implementation" xil_pn:seqID="30"/>
<library xil_pn:name="blk_mem_gen_v4_1"/>
</file>
<file xil_pn:name="../../../../../../wr-repos/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_ecc_decoder.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="30"/>
<association xil_pn:name="Implementation" xil_pn:seqID="31"/>
<library xil_pn:name="blk_mem_gen_v4_1"/>
</file>
<file xil_pn:name="../../../../../../wr-repos/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_input_block.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="31"/>
<association xil_pn:name="Implementation" xil_pn:seqID="32"/>
<library xil_pn:name="blk_mem_gen_v4_1"/>
</file>
<file xil_pn:name="../../../../../../wr-repos/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_output_block.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="32"/>
<association xil_pn:name="Implementation" xil_pn:seqID="33"/>
<library xil_pn:name="blk_mem_gen_v4_1"/>
</file>
<file xil_pn:name="../../../../../../wr-repos/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_top.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="33"/>
<association xil_pn:name="Implementation" xil_pn:seqID="34"/>
<library xil_pn:name="blk_mem_gen_v4_1"/>
</file>
<file xil_pn:name="../../../../../../wr-repos/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_v4_1_xst.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="34"/>
<association xil_pn:name="Implementation" xil_pn:seqID="35"/>
<library xil_pn:name="blk_mem_gen_v4_1"/>
</file>
<file xil_pn:name="../../../../../../wr-repos/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/fifo_generator_v6_1_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="35"/>
<association xil_pn:name="Implementation" xil_pn:seqID="36"/>
<library xil_pn:name="fifo_generator_v6_1"/>
</file>
<file xil_pn:name="../../../../../../wr-repos/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/fifo_generator_v6_1_defaults.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="36"/>
<association xil_pn:name="Implementation" xil_pn:seqID="37"/>
<library xil_pn:name="fifo_generator_v6_1"/>
</file>
<file xil_pn:name="../../../../../../wr-repos/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/fifo_generator_v6_1_xst_comp.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="37"/>
<association xil_pn:name="Implementation" xil_pn:seqID="38"/>
<library xil_pn:name="fifo_generator_v6_1"/>
</file>
<file xil_pn:name="../../../../../../wr-repos/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/input_blk.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="38"/>
<association xil_pn:name="Implementation" xil_pn:seqID="39"/>
<library xil_pn:name="fifo_generator_v6_1"/>
</file>
<file xil_pn:name="../../../../../../wr-repos/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/output_blk.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="39"/>
<association xil_pn:name="Implementation" xil_pn:seqID="40"/>
<library xil_pn:name="fifo_generator_v6_1"/>
</file>
<file xil_pn:name="../../../../../../wr-repos/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/shft_wrapper.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="40"/>
<association xil_pn:name="Implementation" xil_pn:seqID="41"/>
<library xil_pn:name="fifo_generator_v6_1"/>
</file>
<file xil_pn:name="../../../../../../wr-repos/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/shft_ram.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="41"/>
<association xil_pn:name="Implementation" xil_pn:seqID="42"/>
<library xil_pn:name="fifo_generator_v6_1"/>
</file>
<file xil_pn:name="../../../../../../wr-repos/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/dmem.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="42"/>
<association xil_pn:name="Implementation" xil_pn:seqID="43"/>
<library xil_pn:name="fifo_generator_v6_1"/>
</file>
<file xil_pn:name="../../../../../../wr-repos/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/memory.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="43"/>
<association xil_pn:name="Implementation" xil_pn:seqID="44"/>
<library xil_pn:name="fifo_generator_v6_1"/>
</file>
<file xil_pn:name="../../../../../../wr-repos/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/compare.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="44"/>
<association xil_pn:name="Implementation" xil_pn:seqID="45"/>
<library xil_pn:name="fifo_generator_v6_1"/>
</file>
<file xil_pn:name="../../../../../../wr-repos/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/wr_bin_cntr.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="45"/>
<association xil_pn:name="Implementation" xil_pn:seqID="46"/>
<library xil_pn:name="fifo_generator_v6_1"/>
</file>
<file xil_pn:name="../../../../../../wr-repos/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/rd_bin_cntr.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="46"/>
<association xil_pn:name="Implementation" xil_pn:seqID="47"/>
<library xil_pn:name="fifo_generator_v6_1"/>
</file>
<file xil_pn:name="../../../../../../wr-repos/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/updn_cntr.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="47"/>
<association xil_pn:name="Implementation" xil_pn:seqID="48"/>
<library xil_pn:name="fifo_generator_v6_1"/>
</file>
<file xil_pn:name="../../../../../../wr-repos/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/rd_status_flags_as.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="48"/>
<association xil_pn:name="Implementation" xil_pn:seqID="49"/>
<library xil_pn:name="fifo_generator_v6_1"/>
</file>
<file xil_pn:name="../../../../../../wr-repos/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/rd_status_flags_ss.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="49"/>
<association xil_pn:name="Implementation" xil_pn:seqID="50"/>
<library xil_pn:name="fifo_generator_v6_1"/>
</file>
<file xil_pn:name="../../../../../../wr-repos/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/rd_pe_as.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="50"/>
<association xil_pn:name="Implementation" xil_pn:seqID="51"/>
<library xil_pn:name="fifo_generator_v6_1"/>
</file>
<file xil_pn:name="../../../../../../wr-repos/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/rd_pe_ss.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="51"/>
<association xil_pn:name="Implementation" xil_pn:seqID="52"/>
<library xil_pn:name="fifo_generator_v6_1"/>
</file>
<file xil_pn:name="../../../../../../wr-repos/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/rd_handshaking_flags.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="52"/>
<association xil_pn:name="Implementation" xil_pn:seqID="53"/>
<library xil_pn:name="fifo_generator_v6_1"/>
</file>
<file xil_pn:name="../../../../../../wr-repos/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/rd_dc_as.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="53"/>
<association xil_pn:name="Implementation" xil_pn:seqID="54"/>
<library xil_pn:name="fifo_generator_v6_1"/>
</file>
<file xil_pn:name="../../../../../../wr-repos/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/rd_dc_fwft_ext_as.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="54"/>
<association xil_pn:name="Implementation" xil_pn:seqID="55"/>
<library xil_pn:name="fifo_generator_v6_1"/>
</file>
<file xil_pn:name="../../../../../../wr-repos/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/dc_ss.vhd" xil_pn:type="FILE_VHDL">
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<association xil_pn:name="Implementation" xil_pn:seqID="56"/>
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<association xil_pn:name="Implementation" xil_pn:seqID="260"/>
</file>
<file xil_pn:name="../../../../../../wr-repos/wr-cores/modules/wr_endpoint/ep_wishbone_controller.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../../../../../wr-repos/wr-cores/modules/wr_endpoint/ep_leds_controller.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="261"/>
</file>
<file xil_pn:name="../../../../../../wr-repos/wr-cores/modules/wr_endpoint/ep_rx_pcs_8bit.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../../../../../wr-repos/wr-cores/modules/wr_endpoint/ep_rtu_header_extract.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="262"/>
</file>
<file xil_pn:name="../../../../../../wr-repos/wr-cores/modules/wr_endpoint/endpoint_pkg.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../../../../../wr-repos/wr-cores/modules/wr_endpoint/ep_rx_buffer.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="263"/>
</file>
<file xil_pn:name="../../../../../../wr-repos/wr-cores/modules/wr_endpoint/wr_endpoint.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../../../../../wr-repos/wr-cores/modules/wr_endpoint/ep_sync_detect.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="264"/>
</file>
<file xil_pn:name="../../../../../../wr-repos/wr-cores/modules/wr_endpoint/xwr_endpoint.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../../../../../wr-repos/wr-cores/modules/wr_endpoint/ep_sync_detect_16bit.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="265"/>
</file>
<file xil_pn:name="../../../../../../wr-repos/wr-cores/modules/wr_pps_gen/pps_gen_wb.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../../../../../wr-repos/wr-cores/modules/wr_endpoint/ep_wishbone_controller.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="266"/>
</file>
<file xil_pn:name="../../../../../../wr-repos/wr-cores/modules/wr_pps_gen/wr_pps_gen.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../../../../../wr-repos/wr-cores/modules/wr_endpoint/ep_rx_pcs_8bit.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="267"/>
</file>
<file xil_pn:name="../../../../../../wr-repos/wr-cores/modules/wr_pps_gen/xwr_pps_gen.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../../../../../wr-repos/wr-cores/modules/wr_endpoint/ep_rx_crc_size_check.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="268"/>
</file>
<file xil_pn:name="../../../../../../wr-repos/wr-cores/modules/wrc_core/wrcore_pkg.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../../../../../wr-repos/wr-cores/modules/wrc_core/wrc_syscon_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="269"/>
</file>
<file xil_pn:name="../../../../../../wr-repos/wr-cores/modules/wrc_core/wr_core.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../../../../../wr-repos/wr-cores/modules/wr_endpoint/wr_endpoint.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="270"/>
</file>
<file xil_pn:name="../../../../../../wr-repos/wr-cores/modules/wrc_core/wrc_dpram.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../../../../../wr-repos/wr-cores/modules/wr_endpoint/xwr_endpoint.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="271"/>
</file>
<file xil_pn:name="../../../top/svec/wr/svec_top.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../../../../../wr-repos/wr-cores/modules/wr_pps_gen/pps_gen_wb.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="272"/>
</file>
<file xil_pn:name="../../../../../../wr-repos/wr-cores/modules/wrc_core/wrc_periph.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../../../../../wr-repos/wr-cores/modules/wr_pps_gen/wr_pps_gen.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="273"/>
</file>
<file xil_pn:name="../../../../../../wr-repos/wr-cores/modules/wrc_core/wb_reset.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../../../../../wr-repos/wr-cores/modules/wr_pps_gen/xwr_pps_gen.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="274"/>
</file>
<file xil_pn:name="../../../../../../wr-repos/wr-cores/modules/wrc_core/wbp_mux.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../../../../../wr-repos/wr-cores/modules/wr_dacs/spec_serial_dac_arb.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="275"/>
</file>
<file xil_pn:name="../../../../../../wr-repos/wr-cores/modules/wrc_core/wrc_syscon_wb.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../../../../../wr-repos/wr-cores/modules/wr_dacs/spec_serial_dac.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="276"/>
</file>
<file xil_pn:name="../../../../../../wr-repos/wr-cores/modules/wrc_core/xwr_core.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../../../../../wr-repos/wr-cores/modules/wrc_core/wrcore_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="277"/>
</file>
<file xil_pn:name="../../../../../../wr-repos/wr-cores/modules/wrc_core/xwr_syscon_wb.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../../../../../wr-repos/wr-cores/modules/wrc_core/wr_core.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="278"/>
</file>
<file xil_pn:name="../../../../../../wr-repos/wr-cores/platform/xilinx/wr_gtp_phy/gtp_bitslide.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../../../../../wr-repos/wr-cores/modules/wrc_core/wrc_dpram.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="279"/>
</file>
<file xil_pn:name="../../../../../../wr-repos/wr-cores/platform/xilinx/wr_gtp_phy/gtp_phase_align.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../../../../../wr-repos/wr-cores/platform/xilinx/wr_xilinx_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="280"/>
</file>
<file xil_pn:name="../../../../../../wr-repos/wr-cores/platform/xilinx/wr_gtp_phy/gtp_phase_align_virtex6.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../../../../../wr-repos/wr-cores/modules/wrc_core/wrc_periph.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="281"/>
</file>
<file xil_pn:name="../../../../../../wr-repos/wr-cores/platform/xilinx/wr_gtp_phy/gtx_reset.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../../../../../wr-repos/wr-cores/modules/wrc_core/wb_reset.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="282"/>
</file>
<file xil_pn:name="../../../../../../wr-repos/wr-cores/platform/xilinx/wr_gtp_phy/whiterabbitgtx_wrapper_gtx.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../../../../../wr-repos/wr-cores/modules/wrc_core/wbp_mux.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="283"/>
</file>
<file xil_pn:name="../../../../../../wr-repos/wr-cores/platform/xilinx/wr_gtp_phy/whiterabbitgtp_wrapper_tile.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../../../../../wr-repos/wr-cores/modules/wrc_core/wrc_syscon_wb.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="284"/>
</file>
<file xil_pn:name="../../../../../../wr-repos/wr-cores/platform/xilinx/wr_gtp_phy/wr_gtp_phy_spartan6.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../../../../../wr-repos/wr-cores/modules/wrc_core/xwr_core.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="285"/>
</file>
<file xil_pn:name="../../../../../../wr-repos/wr-cores/platform/xilinx/wr_gtp_phy/wr_gtx_phy_virtex6.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../../../../../wr-repos/wr-cores/modules/wrc_core/xwr_syscon_wb.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="286"/>
</file>
<file xil_pn:name="../../../../../../wr-repos/etherbone-core/hdl/EB_SPEC_Test/etherbone_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="287"/>
</file>
<file xil_pn:name="../../../../../../wr-repos/wr-cores/platform/xilinx/wr_gtp_phy/gtp_bitslide.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="288"/>
</file>
<file xil_pn:name="../../../../../../wr-repos/wr-cores/platform/xilinx/wr_gtp_phy/gtp_phase_align.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="289"/>
</file>
<file xil_pn:name="../../../../../../wr-repos/wr-cores/platform/xilinx/wr_gtp_phy/gtp_phase_align_virtex6.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="290"/>
</file>
<file xil_pn:name="../../../../../../wr-repos/wr-cores/platform/xilinx/wr_gtp_phy/gtx_reset.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="291"/>
</file>
<file xil_pn:name="../../../../../../wr-repos/wr-cores/platform/xilinx/wr_gtp_phy/whiterabbitgtx_wrapper_gtx.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="292"/>
</file>
<file xil_pn:name="../../../../../../wr-repos/wr-cores/platform/xilinx/wr_gtp_phy/whiterabbitgtp_wrapper_tile.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="293"/>
</file>
<file xil_pn:name="../../../../../../wr-repos/wr-cores/platform/xilinx/wr_gtp_phy/wr_gtp_phy_spartan6.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="294"/>
</file>
<file xil_pn:name="../../../../../../wr-repos/wr-cores/platform/xilinx/wr_gtp_phy/wr_gtx_phy_virtex6.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="295"/>
</file>
<file xil_pn:name="../../../../../../wr-repos/etherbone-core/hdl/EB_SPEC_Test/EB_HDR_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="296"/>
</file>
<file xil_pn:name="../../../../../../wr-repos/etherbone-core/hdl/EB_SPEC_Test/EB_checksum.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="297"/>
</file>
<file xil_pn:name="../../../../../../wr-repos/etherbone-core/hdl/EB_SPEC_Test/wishbone_package32.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="298"/>
</file>
<file xil_pn:name="../../../../../../wr-repos/etherbone-core/hdl/EB_SPEC_Test/EB_CORE.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="299"/>
</file>
<file xil_pn:name="../../../../../../wr-repos/etherbone-core/hdl/EB_SPEC_Test/EB_2_wb_converter.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="300"/>
</file>
<file xil_pn:name="../../../../../../wr-repos/etherbone-core/hdl/EB_SPEC_Test/EB_RX_CTRL.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="301"/>
</file>
<file xil_pn:name="../../../../../../wr-repos/etherbone-core/hdl/EB_SPEC_Test/wishbone_package16.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="302"/>
</file>
<file xil_pn:name="../../../top/svec/wr/svec_top.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="303"/>
</file>
<file xil_pn:name="../../../../../../wr-repos/etherbone-core/hdl/EB_SPEC_Test/piso_flag.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="304"/>
</file>
<file xil_pn:name="../../../../../../wr-repos/etherbone-core/hdl/EB_SPEC_Test/vhdl_2008_workaround_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="305"/>
</file>
<file xil_pn:name="../../../../../../wr-repos/etherbone-core/hdl/EB_SPEC_Test/sipo_flag.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="306"/>
</file>
<file xil_pn:name="../../../../../../wr-repos/etherbone-core/hdl/EB_SPEC_Test/WB_bus_adapter_streaming_sg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="307"/>
</file>
<file xil_pn:name="../../../../../../wr-repos/etherbone-core/hdl/EB_SPEC_Test/EB_TX_CTRL.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="308"/>
</file>
<file xil_pn:name="../../../../../../wr-repos/etherbone-core/hdl/EB_SPEC_Test/eb_config_new.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="309"/>
</file>
<file xil_pn:name="../../../../../../wr-repos/etherbone-core/hdl/EB_SPEC_Test/xetherbone_core.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="310"/>
</file>
</files>
<bindings/>
<version xil_pn:ise_version="13.3" xil_pn:schema_version="2"/>
<version xil_pn:ise_version="14.1" xil_pn:schema_version="2"/>
</project>
hdl/top/svec/wr/Manifest.py
View file @ a21d0b54
files = [ "svec_top.vhd", "svec_top.ucf", "xvme64x_core.vhd", "spec_serial_dac.vhd" ]
files = [ "svec_top.vhd", "svec_top.ucf", "xvme64x_core.vhd" ]
fetchto = "../../../ip_cores"
modules = {
"local" : ["../../../rtl", "../../../platform", "../../../ip_cores/vme64x-core" ],
"git" : [ "git://ohwr.org/hdl-core-lib/wr-cores.git::wishbonized" ]
# "svn" : [ "http://svn.ohwr.org/vme64x-core/trunk/hdl/vme64x-core/rtl" ]
"local" : ["../../../rtl", "../../../platform" ],
"git" : [ "git://ohwr.org/hdl-core-lib/wr-cores.git",
"git://ohwr.org/hdl-core-lib/etherbone-core.git" ],
"svn" : [ "http://svn.ohwr.org/vme64x-core/trunk/hdl/vme64x-core/rtl" ]
}
hdl/top/svec/wr/svec_top.ucf
View file @ a21d0b54
......@@ -360,8 +360,8 @@ NET "fd1_clk_ref_p_i" TNM_NET = fd1_clk_ref_p_i;
TIMESPEC TS_fd1_clk_ref_p_i = PERIOD "fd1_clk_ref_p_i" 8 ns HIGH 50%;
NET "fd1_clk_ref_n_i" TNM_NET = fd1_clk_ref_n_i;
TIMESPEC TS_fd1_clk_ref_n_i = PERIOD "fd1_clk_ref_n_i" 8 ns HIGH 50%;
NET "gen_with_phy.U_GTP/ch0_gtp_clkout_int<1>" TNM_NET = gen_with_phy.U_GTP/ch0_gtp_clkout_int<1>;
TIMESPEC TS_gen_with_phy_U_GTP_ch0_gtp_clkout_int_1_ = PERIOD "gen_with_phy.U_GTP/ch0_gtp_clkout_int<1>" 8 ns HIGH 50%;
#NET "gen_with_phy.U_GTP/ch0_gtp_clkout_int<1>" TNM_NET = gen_with_phy.U_GTP/ch0_gtp_clkout_int<1>;
#TIMESPEC TS_gen_with_phy_U_GTP_ch0_gtp_clkout_int_1_ = PERIOD "gen_with_phy.U_GTP/ch0_gtp_clkout_int<1>" 8 ns HIGH 50%;
NET "gen_with_phy.U_GTP/ch1_gtp_clkout_int<1>" TNM_NET = gen_with_phy.U_GTP/ch1_gtp_clkout_int<1>;
TIMESPEC TS_gen_with_phy_U_GTP_ch1_gtp_clkout_int_1_ = PERIOD "gen_with_phy.U_GTP/ch1_gtp_clkout_int<1>" 8 ns HIGH 50%;
......
hdl/top/svec/wr/svec_top.vhd
View file @ a21d0b54
-------------------------------------------------------------------------------
-- Title : Fine Delay FMC SVEC (Simple VME FMC Carrier) top level
-- Project : Fine Delay FMC (fmc-delay-1ns-4cha)
-------------------------------------------------------------------------------
-- File : svec_top.vhd
-- Author : Tomasz Wlostowski
-- Company : CERN
-- Created : 2011-08-24
-- Last update: 2012-08-13
-- Platform : FPGA-generic
-- Standard : VHDL'93
-------------------------------------------------------------------------------
-- Description: Top level for the SVEC 1.0 card with two Fine Delay FMCs.
-- Supports:
-- - A24/A32/D32 VME addressing
-- - SDB enumeration (SDB descriptor at 0x60000)
-- - White Rabbit and Etherbone
-- Does not yet support:
-- - Interrupts
-------------------------------------------------------------------------------
--
-- Copyright (c) 2011 CERN / BE-CO-HT
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
-- Public License as published by the Free Software Foundation;
-- either version 2.1 of the License, or (at your option) any
-- later version.
--
-- This source is distributed in the hope that it will be
-- useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
-- PURPOSE. See the GNU Lesser General Public License for more
-- details.
--
-- You should have received a copy of the GNU Lesser General
-- Public License along with this source; if not, download it
-- from http://www.gnu.org/licenses/lgpl-2.1.html
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
......@@ -8,6 +49,8 @@ use work.wrcore_pkg.all;
use work.wr_fabric_pkg.all;
use work.wishbone_pkg.all;
use work.fine_delay_pkg.all;
use work.etherbone_pkg.all;
use work.wr_xilinx_pkg.all;
library UNISIM;
use UNISIM.vcomponents.all;
......@@ -49,6 +92,7 @@ entity svec_top is
VME_DTACK_n_o : inout std_logic;
VME_RETRY_n_o : out std_logic;
VME_RETRY_OE_o : out std_logic;
VME_LWORD_n_b : inout std_logic;
VME_ADDR_b : inout std_logic_vector(31 downto 1);
VME_DATA_b : inout std_logic_vector(31 downto 0);
......@@ -190,157 +234,42 @@ end svec_top;
architecture rtl of svec_top is
component xvme64x_core
port (
clk_i : in std_logic;
rst_n_i : in std_logic;
VME_AS_n_i : in std_logic;
VME_RST_n_i : in std_logic;
VME_WRITE_n_i : in std_logic;
VME_AM_i : in std_logic_vector(5 downto 0);
VME_DS_n_i : in std_logic_vector(1 downto 0);
VME_GA_i : in std_logic_vector(5 downto 0);
VME_BERR_o : out std_logic;
VME_DTACK_n_o : out std_logic;
VME_RETRY_n_o : out std_logic;
VME_RETRY_OE_o : out std_logic;
VME_LWORD_n_b : inout std_logic;
VME_ADDR_b : inout std_logic_vector(31 downto 1);
VME_DATA_b : inout std_logic_vector(31 downto 0);
VME_BBSY_n_i : in std_logic;
VME_IRQ_n_o : out std_logic_vector(6 downto 0);
VME_IACK_n_i : in std_logic;
VME_IACKIN_n_i : in std_logic;
VME_IACKOUT_n_o : out std_logic;
VME_DTACK_OE_o : out std_logic;
VME_DATA_DIR_o : out std_logic;
VME_DATA_OE_N_o : out std_logic;
VME_ADDR_DIR_o : out std_logic;
VME_ADDR_OE_N_o : out std_logic;
master_o : out t_wishbone_master_out;
master_i : in t_wishbone_master_in;
irq_i : in std_logic);
clk_i : in std_logic;
rst_n_i : in std_logic;
rst_n_o : out std_logic;
VME_AS_n_i : in std_logic;
VME_RST_n_i : in std_logic;
VME_WRITE_n_i : in std_logic;
VME_AM_i : in std_logic_vector(5 downto 0);
VME_DS_n_i : in std_logic_vector(1 downto 0);
VME_GA_i : in std_logic_vector(5 downto 0);
VME_BERR_o : out std_logic;
VME_DTACK_n_o : out std_logic;
VME_RETRY_n_o : out std_logic;
VME_RETRY_OE_o : out std_logic;
VME_LWORD_n_b_i : in std_logic;
VME_LWORD_n_b_o : out std_logic;
VME_ADDR_b_i : in std_logic_vector(31 downto 1);
VME_ADDR_b_o : out std_logic_vector(31 downto 1);
VME_DATA_b_i : in std_logic_vector(31 downto 0);
VME_DATA_b_o : out std_logic_vector(31 downto 0);
VME_IRQ_n_o : out std_logic_vector(6 downto 0);
VME_IACKIN_n_i : in std_logic;
VME_IACK_n_i : in std_logic;
VME_IACKOUT_n_o : out std_logic;
VME_DTACK_OE_o : out std_logic;
VME_DATA_DIR_o : out std_logic;
VME_DATA_OE_N_o : out std_logic;
VME_ADDR_DIR_o : out std_logic;
VME_ADDR_OE_N_o : out std_logic;
master_o : out t_wishbone_master_out;
master_i : in t_wishbone_master_in;
irq_i : in std_logic;
irq_ack_o : out std_logic);
end component;
component xwr_core is
generic(
g_simulation : integer := 0;
g_phys_uart : boolean := true;
g_virtual_uart : boolean := false;
g_with_external_clock_input : boolean := false;
g_aux_clks : integer := 1;
g_ep_rxbuf_size : integer := 1024;
g_dpram_initf : string := "wrc_stub.ram";
g_dpram_size : integer := 16384; --in 32-bit words
g_interface_mode : t_wishbone_interface_mode := PIPELINED;
g_address_granularity : t_wishbone_address_granularity := BYTE
);
port(
clk_sys_i : in std_logic;
clk_dmtd_i : in std_logic;
clk_ref_i : in std_logic;
clk_aux_i : in std_logic_vector(g_aux_clks-1 downto 0) := (others => '0');
rst_n_i : in std_logic;
dac_hpll_load_p1_o : out std_logic;
dac_hpll_data_o : out std_logic_vector(15 downto 0);
dac_dpll_load_p1_o : out std_logic;
dac_dpll_data_o : out std_logic_vector(15 downto 0);
phy_ref_clk_i : in std_logic;
phy_tx_data_o : out std_logic_vector(7 downto 0);
phy_tx_k_o : out std_logic;
phy_tx_disparity_i : in std_logic;
phy_tx_enc_err_i : in std_logic;
phy_rx_data_i : in std_logic_vector(7 downto 0);
phy_rx_rbclk_i : in std_logic;
phy_rx_k_i : in std_logic;
phy_rx_enc_err_i : in std_logic;
phy_rx_bitslide_i : in std_logic_vector(3 downto 0);
phy_rst_o : out std_logic;
phy_loopen_o : out std_logic;
led_red_o : out std_logic;
led_green_o : out std_logic;
scl_o : out std_logic;
scl_i : in std_logic;
sda_o : out std_logic;
sda_i : in std_logic;
sfp_scl_o : out std_logic;
sfp_scl_i : in std_logic;
sfp_sda_o : out std_logic;
sfp_sda_i : in std_logic;
sfp_det_i : in std_logic;
btn1_i : in std_logic := '1';
btn2_i : in std_logic := '1';
uart_rxd_i : in std_logic;
uart_txd_o : out std_logic;
owr_en_o : out std_logic_vector(1 downto 0);
owr_i : in std_logic_vector(1 downto 0);
wrf_src_o : out t_wrf_source_out;
wrf_src_i : in t_wrf_source_in := c_dummy_src_in;
wrf_snk_o : out t_wrf_sink_out;
wrf_snk_i : in t_wrf_sink_in := c_dummy_snk_in;
slave_i : in t_wishbone_slave_in;
slave_o : out t_wishbone_slave_out;
tm_link_up_o : out std_logic;
tm_dac_value_o : out std_logic_vector(23 downto 0);
tm_dac_wr_o : out std_logic;
tm_clk_aux_lock_en_i : in std_logic;
tm_clk_aux_locked_o : out std_logic;
tm_time_valid_o : out std_logic;
tm_utc_o : out std_logic_vector(39 downto 0);
tm_cycles_o : out std_logic_vector(27 downto 0);
pps_p_o : out std_logic;
rst_aux_n_o : out std_logic
);
end component;
component wr_gtp_phy_spartan6
generic (
g_simulation : integer);
port (
gtp_clk_i : in std_logic;
ch0_ref_clk_i : in std_logic;
ch0_tx_data_i : in std_logic_vector(7 downto 0);
ch0_tx_k_i : in std_logic;
ch0_tx_disparity_o : out std_logic;
ch0_tx_enc_err_o : out std_logic;
ch0_rx_rbclk_o : out std_logic;
ch0_rx_data_o : out std_logic_vector(7 downto 0);
ch0_rx_k_o : out std_logic;
ch0_rx_enc_err_o : out std_logic;
ch0_rx_bitslide_o : out std_logic_vector(3 downto 0);
ch0_rst_i : in std_logic;
ch0_loopen_i : in std_logic;
ch1_ref_clk_i : in std_logic;
ch1_tx_data_i : in std_logic_vector(7 downto 0) := "00000000";
ch1_tx_k_i : in std_logic := '0';
ch1_tx_disparity_o : out std_logic;
ch1_tx_enc_err_o : out std_logic;
ch1_rx_data_o : out std_logic_vector(7 downto 0);
ch1_rx_rbclk_o : out std_logic;
ch1_rx_k_o : out std_logic;
ch1_rx_enc_err_o : out std_logic;
ch1_rx_bitslide_o : out std_logic_vector(3 downto 0);
ch1_rst_i : in std_logic := '0';
ch1_loopen_i : in std_logic := '0';
pad_txn0_o : out std_logic;
pad_txp0_o : out std_logic;
pad_rxn0_i : in std_logic := '0';
pad_rxp0_i : in std_logic := '0';
pad_txn1_o : out std_logic;
pad_txp1_o : out std_logic;
pad_rxn1_i : in std_logic := '0';
pad_rxp1_i : in std_logic := '0');
end component;
component fd_ddr_pll
port (
......@@ -370,6 +299,11 @@ architecture rtl of svec_top is
xdone_o : out std_logic);
end component;
signal VME_DATA_b_out : std_logic_vector(31 downto 0);
signal VME_ADDR_b_out : std_logic_vector(31 downto 1);
signal VME_LWORD_n_b_out, VME_DATA_DIR_int, VME_ADDR_DIR_int : std_logic;
signal dac_hpll_load_p1 : std_logic;
signal dac_dpll_load_p1 : std_logic;
......@@ -399,17 +333,15 @@ architecture rtl of svec_top is
constant c_SLAVE_FD0 : integer := 1;
constant c_SLAVE_WRCORE : integer := 2;
constant c_cnx_base_addr : t_wishbone_address_array(c_NUM_WB_MASTERS-1 downto 0) :=
(c_SLAVE_FD1 => x"00050000",
c_SLAVE_FD0 => x"00040000",
c_SLAVE_WRCORE => x"00000000"
);
constant c_WRCORE_BRIDGE_SDB : t_sdb_bridge := f_xwb_bridge_manual_sdb(x"0003ffff", x"00030000");
constant c_INTERCONNECT_LAYOUT : t_sdb_record_array(c_NUM_WB_MASTERS-1 downto 0) :=
(c_SLAVE_WRCORE => f_sdb_embed_bridge(c_WRCORE_BRIDGE_SDB, x"00000000"),
c_SLAVE_FD0 => f_sdb_embed_device(c_FD_SDB_DEVICE, x"00040000"),
c_SLAVE_FD1 => f_sdb_embed_device(c_FD_SDB_DEVICE, x"00050000"));
constant c_SDB_ADDRESS : t_wishbone_address := x"00060000";
constant c_cnx_base_mask : t_wishbone_address_array(c_NUM_WB_MASTERS-1 downto 0) :=
(c_SLAVE_FD1 => x"000f0000",
c_SLAVE_FD0 => x"000f0000",
c_SLAVE_WRCORE => x"000c0000"
);
signal cnx_master_out : t_wishbone_master_out_array(c_NUM_WB_MASTERS-1 downto 0);
signal cnx_master_in : t_wishbone_master_in_array(c_NUM_WB_MASTERS-1 downto 0);
......@@ -487,62 +419,32 @@ architecture rtl of svec_top is
end if;
end f_int2bool;
component chipscope_ila
port (
CONTROL : inout std_logic_vector(35 downto 0);
CLK : in std_logic;
TRIG0 : in std_logic_vector(31 downto 0);
TRIG1 : in std_logic_vector(31 downto 0);
TRIG2 : in std_logic_vector(31 downto 0);
TRIG3 : in std_logic_vector(31 downto 0));
end component;
component chipscope_icon
port (
CONTROL0 : inout std_logic_vector (35 downto 0));
end component;
signal CONTROL : std_logic_vector(35 downto 0);
signal CLK : std_logic;
signal TRIG0 : std_logic_vector(31 downto 0);
signal TRIG1 : std_logic_vector(31 downto 0);
signal TRIG2 : std_logic_vector(31 downto 0);
signal TRIG3 : std_logic_vector(31 downto 0);
function f_resize_slv (x : std_logic_vector; len : integer) return std_logic_vector is
variable tmp : std_logic_vector(len-1 downto 0);
begin
if(len > x'length) then
tmp(x'length-1 downto 0) := x;
tmp(len-1 downto x'length) := (others => '0');
elsif(len < x'length) then
tmp := x(len-1 downto 0);
else
tmp := x;
end if;
return tmp;
end f_resize_slv;
signal etherbone_rst_n : std_logic;
signal etherbone_src_out : t_wrf_source_out;
signal etherbone_src_in : t_wrf_source_in;
signal etherbone_snk_out : t_wrf_sink_out;
signal etherbone_snk_in : t_wrf_sink_in;
signal etherbone_cfg_in : t_wishbone_slave_in;
signal etherbone_cfg_out : t_wishbone_slave_out;
attribute buffer_type : string; --" {bufgdll | ibufg | bufgp | ibuf | bufr | none}";
attribute buffer_type of clk_125m_pllref : signal is "BUFG";
begin
--chipscope_ila_1 : chipscope_ila
-- port map (
-- CONTROL => CONTROL,
-- CLK => clk_125m_pllref,
-- TRIG0 => TRIG0,
-- TRIG1 => TRIG1,
-- TRIG2 => TRIG2,
-- TRIG3 => TRIG3);
--chipscope_icon_1 : chipscope_icon
-- port map (
-- CONTROL0 => CONTROL);
TRIG0(31 downto 1) <= VME_ADDR_b;
TRIG1(31 downto 0) <= VME_DATA_b;
TRIG2(5 downto 0) <= VME_AM_i;
trig2(7 downto 6) <= VME_DS_n_i;
trig2(13 downto 8) <= VME_GA_i;
trig2(14) <= VME_DTACK_n_o;
trig2(15) <= VME_DTACK_oe_o;
trig2(16) <= VME_LWORD_n_b;
trig2(17) <= VME_WRITE_n_i;
trig2(18) <= VME_AS_n_i;
trig2(19) <= VME_DATA_DIR_o;
trig2(20) <= VME_DATA_OE_N_o;
trig2(21) <= VME_addr_DIR_o;
trig2(22) <= VME_addr_OE_N_o;
trig2(23) <= rst_n_i;
trig2(24) <= local_reset_n;
trig2(25) <= VME_RST_n_i;
U_Buf_CLK_GTP : IBUFDS
generic map (
DIFF_TERM => true,
......@@ -627,7 +529,7 @@ begin
data_i => rst_n_a,
synced_o => local_reset_n);
U_Buf_CLK_PLL : IBUFDS
U_Buf_CLK_PLL : IBUFGDS
generic map (
DIFF_TERM => true,
IBUF_LOW_PWR => true -- Low power (TRUE) vs. performance (FALSE) setting for referenced
......@@ -669,23 +571,32 @@ begin
VME_DTACK_n_o => VME_DTACK_n_o,
VME_RETRY_n_o => VME_RETRY_n_o,
VME_RETRY_OE_o => VME_RETRY_OE_o,
VME_LWORD_n_b => VME_LWORD_n_b,
VME_ADDR_b => VME_ADDR_b,
VME_DATA_b => VME_DATA_b,
VME_BBSY_n_i => VME_BBSY_n_i,
VME_LWORD_n_b_i => VME_LWORD_n_b,
VME_LWORD_n_b_o => VME_LWORD_n_b_out,
VME_ADDR_b_i => VME_ADDR_b,
VME_DATA_b_o => VME_DATA_b_out,
VME_ADDR_b_o => VME_ADDR_b_out,
VME_DATA_b_i => VME_DATA_b,
VME_IRQ_n_o => VME_IRQ_n_o,
VME_IACK_n_i => VME_IACK_n_i,
VME_IACKIN_n_i => VME_IACKIN_n_i,
VME_IACKOUT_n_o => VME_IACKOUT_n_o,
VME_DTACK_OE_o => VME_DTACK_OE_o,
VME_DATA_DIR_o => VME_DATA_DIR_o,
VME_DATA_DIR_o => VME_DATA_DIR_int,
VME_DATA_OE_N_o => VME_DATA_OE_N_o,
VME_ADDR_DIR_o => VME_ADDR_DIR_o,
VME_ADDR_DIR_o => VME_ADDR_DIR_int,
VME_ADDR_OE_N_o => VME_ADDR_OE_N_o,
master_o => vme_master_out,
master_i => vme_master_in,
irq_i => '0');
VME_DATA_b <= VME_DATA_b_out when VME_DATA_DIR_int = '1' else (others => 'Z');
VME_ADDR_b <= VME_ADDR_b_out when VME_ADDR_DIR_int = '1' else (others => 'Z');
VME_LWORD_n_b <= VME_LWORD_n_b_out when VME_ADDR_DIR_int = '1' else 'Z';
VME_ADDR_DIR_o <= VME_ADDR_DIR_int;
VME_DATA_DIR_o <= VME_DATA_DIR_int;
cnx_slave_in(c_MASTER_VME) <= vme_master_out;
vme_master_in <= cnx_slave_out(c_MASTER_VME);
......@@ -724,8 +635,8 @@ begin
g_with_external_clock_input => false,
g_aux_clks => 1,
g_ep_rxbuf_size => 1024,
g_dpram_initf => "",
g_dpram_size => 4096 * 5,
g_dpram_initf => "wrc.ram",
g_dpram_size => 90112/4, --16384,
g_interface_mode => PIPELINED,
g_address_granularity => BYTE)
port map (
......@@ -775,10 +686,16 @@ begin
slave_i => cnx_master_out(c_SLAVE_WRCORE),
slave_o => cnx_master_in(c_SLAVE_WRCORE),
--wrf_src_o => mbone_snk_in,
--wrf_src_i => mbone_snk_out,
--wrf_snk_o => mbone_src_in,
--wrf_snk_i => mbone_src_out,
aux_master_o => etherbone_cfg_in,
aux_master_i => etherbone_cfg_out,
wrf_src_o => etherbone_snk_in,
wrf_src_i => etherbone_snk_out,
wrf_snk_o => etherbone_src_in,
wrf_snk_i => etherbone_src_out,
btn1_i => '0',
btn2_i => '0',
tm_link_up_o => tm_link_up,
tm_dac_value_o => tm_dac_value,
......@@ -789,7 +706,7 @@ begin
tm_utc_o => tm_utc,
tm_cycles_o => tm_cycles,
rst_aux_n_o => open,
rst_aux_n_o => etherbone_rst_n,
pps_p_o => pps
);
......@@ -827,15 +744,30 @@ begin
dac_sdata_o => pll25dac_din_o,
xdone_o => open);
U_Etherbone : EB_CORE
generic map (
g_sdb_address => f_resize_slv(c_sdb_address, 64))
port map (
clk_i => clk_sys,
nRst_i => etherbone_rst_n,
src_o => etherbone_src_out,
src_i => etherbone_src_in,
snk_o => etherbone_snk_out,
snk_i => etherbone_snk_in,
cfg_slave_o => etherbone_cfg_out,
cfg_slave_i => etherbone_cfg_in,
master_o => cnx_slave_in(c_MASTER_ETHERBONE),
master_i => cnx_slave_out(c_MASTER_ETHERBONE));
U_Intercon : xwb_crossbar
U_Intercon : xwb_sdb_crossbar
generic map (
g_num_masters => c_NUM_WB_SLAVES,
g_num_slaves => c_NUM_WB_MASTERS,
g_registered => true,
g_address => c_cnx_base_addr,
g_mask => c_cnx_base_mask)
g_wraparound => true,
g_layout => c_INTERCONNECT_LAYOUT,
g_sdb_addr => c_SDB_ADDRESS)
port map (
clk_sys_i => clk_sys,
rst_n_i => local_reset_n,
......@@ -848,6 +780,8 @@ begin
U_GTP : wr_gtp_phy_spartan6
generic map (
g_enable_ch0 => 0,
g_enable_ch1 => 1,
g_simulation => g_simulation)
port map (
gtp_clk_i => clk_125m_gtp,
......@@ -887,9 +821,6 @@ begin
end generate gen_with_phy;
cnx_slave_in(c_MASTER_ETHERBONE).cyc <= '0';
-------------------------------------------------------------------------------
-- FINE DELAY 0 INSTANTIATION
-------------------------------------------------------------------------------
......@@ -993,8 +924,8 @@ begin
cnx_master_in(c_SLAVE_FD0).err <= '0';
cnx_master_in(c_SLAVE_FD0).rty <= '0';
-- tristate buffer for the TDC data bus:
fd0_tdc_d_b <= tdc0_data_out when tdc0_data_oe = '1' else (others => 'Z');
fd0_tdc_oe_n_o <= '1';
......
hdl/top/svec/wr/xvme64x_core.vhd
View file @ a21d0b54
......@@ -3,39 +3,44 @@ use ieee.STD_LOGIC_1164.all;
use WORK.wishbone_pkg.all;
entity xvme64x_core is
port (
clk_i : in std_logic;
rst_n_i : in std_logic;
VME_AS_n_i : in std_logic;
VME_RST_n_i : in std_logic;
VME_WRITE_n_i : in std_logic;
VME_AM_i : in std_logic_vector(5 downto 0);
VME_DS_n_i : in std_logic_vector(1 downto 0);
VME_GA_i : in std_logic_vector(5 downto 0);
VME_BERR_o : out std_logic;
VME_DTACK_n_o : out std_logic;
VME_RETRY_n_o : out std_logic;
VME_RETRY_OE_o : out std_logic;
VME_LWORD_n_b : inout std_logic;
VME_ADDR_b : inout std_logic_vector(31 downto 1);
VME_DATA_b : inout std_logic_vector(31 downto 0);
VME_BBSY_n_i : in std_logic;
VME_IRQ_n_o : out std_logic_vector(6 downto 0);
VME_IACK_n_i : in std_logic;
VME_IACKIN_n_i : in std_logic;
VME_IACKOUT_n_o : out std_logic;
VME_DTACK_OE_o : out std_logic;
VME_DATA_DIR_o : out std_logic;
VME_DATA_OE_N_o : out std_logic;
VME_ADDR_DIR_o : out std_logic;
VME_ADDR_OE_N_o : out std_logic;
rst_n_o : out std_logic;
VME_AS_n_i : in std_logic;
VME_RST_n_i : in std_logic;
VME_WRITE_n_i : in std_logic;
VME_AM_i : in std_logic_vector(5 downto 0);
VME_DS_n_i : in std_logic_vector(1 downto 0);
VME_GA_i : in std_logic_vector(5 downto 0);
VME_BERR_o : out std_logic;
VME_DTACK_n_o : out std_logic;
VME_RETRY_n_o : out std_logic;
VME_RETRY_OE_o : out std_logic;
VME_LWORD_n_b_i : in std_logic;
VME_LWORD_n_b_o : out std_logic;
VME_ADDR_b_i : in std_logic_vector(31 downto 1);
VME_ADDR_b_o : out std_logic_vector(31 downto 1);
VME_DATA_b_i : in std_logic_vector(31 downto 0);
VME_DATA_b_o : out std_logic_vector(31 downto 0);
VME_IRQ_n_o : out std_logic_vector(6 downto 0);
VME_IACKIN_n_i : in std_logic;
VME_IACK_n_i : in std_logic;
VME_IACKOUT_n_o : out std_logic;
VME_DTACK_OE_o : out std_logic;
VME_DATA_DIR_o : out std_logic;
VME_DATA_OE_N_o : out std_logic;
VME_ADDR_DIR_o : out std_logic;
VME_ADDR_OE_N_o : out std_logic;
master_o : out t_wishbone_master_out;
master_i : in t_wishbone_master_in;
irq_i : in std_logic
irq_i : in std_logic;
irq_ack_o : out std_logic
);
......@@ -44,98 +49,113 @@ end xvme64x_core;
architecture wrapper of xvme64x_core is
component VME64xCore_Top
generic(
g_width : integer := 32;
g_addr_width : integer := 64;
g_CRAM_SIZE : integer := 1024
);
port (
clk_i : in std_logic;
VME_AS_n_i : in std_logic;
VME_RST_n_i : in std_logic;
VME_WRITE_n_i : in std_logic;
VME_AM_i : in std_logic_vector(5 downto 0);
VME_DS_n_i : in std_logic_vector(1 downto 0);
VME_GA_i : in std_logic_vector(5 downto 0);
VME_BERR_o : out std_logic;
VME_DTACK_n_o : out std_logic;
VME_RETRY_n_o : out std_logic;
VME_RETRY_OE_o : out std_logic;
VME_LWORD_n_b : inout std_logic;
VME_ADDR_b : inout std_logic_vector(31 downto 1);
VME_DATA_b : inout std_logic_vector(31 downto 0);
VME_BBSY_n_i : in std_logic;
VME_IRQ_n_o : out std_logic_vector(6 downto 0);
VME_IACK_n_i : in std_logic;
VME_IACKIN_n_i : in std_logic;
VME_IACKOUT_n_o : out std_logic;
VME_DTACK_OE_o : out std_logic;
VME_DATA_DIR_o : out std_logic;
VME_DATA_OE_N_o : out std_logic;
VME_ADDR_DIR_o : out std_logic;
VME_ADDR_OE_N_o : out std_logic;
RST_i : in std_logic;
DAT_i : in std_logic_vector(63 downto 0);
DAT_o : out std_logic_vector(63 downto 0);
ADR_o : out std_logic_vector(63 downto 0);
CYC_o : out std_logic;
ERR_i : in std_logic;
LOCK_o : out std_logic;
RTY_i : in std_logic;
SEL_o : out std_logic_vector(7 downto 0);
STB_o : out std_logic;
ACK_i : in std_logic;
WE_o : out std_logic;
STALL_i : in std_logic;
IRQ_i : in std_logic);
clk_i : in std_logic;
reset_o : out std_logic;
VME_AS_n_i : in std_logic;
VME_RST_n_i : in std_logic;
VME_WRITE_n_i : in std_logic;
VME_AM_i : in std_logic_vector(5 downto 0);
VME_DS_n_i : in std_logic_vector(1 downto 0);
VME_GA_i : in std_logic_vector(5 downto 0);
VME_BERR_o : out std_logic;
VME_DTACK_n_o : out std_logic;
VME_RETRY_n_o : out std_logic;
VME_LWORD_n_b_i : in std_logic;
VME_LWORD_n_b_o : out std_logic;
VME_ADDR_b_i : in std_logic_vector(31 downto 1);
VME_ADDR_b_o : out std_logic_vector(31 downto 1);
VME_DATA_b_i : in std_logic_vector(31 downto 0);
VME_DATA_b_o : out std_logic_vector(31 downto 0);
VME_IRQ_n_o : out std_logic_vector(6 downto 0);
VME_IACKIN_n_i : in std_logic;
VME_IACK_n_i : in std_logic;
VME_IACKOUT_n_o : out std_logic;
VME_DTACK_OE_o : out std_logic;
VME_DATA_DIR_o : out std_logic;
VME_DATA_OE_N_o : out std_logic;
VME_ADDR_DIR_o : out std_logic;
VME_ADDR_OE_N_o : out std_logic;
VME_RETRY_OE_o : out std_logic;
DAT_i : in std_logic_vector(g_width - 1 downto 0);
DAT_o : out std_logic_vector(g_width - 1 downto 0);
ADR_o : out std_logic_vector(g_addr_width - 1 downto 0);
CYC_o : out std_logic;
ERR_i : in std_logic;
RTY_i : in std_logic;
SEL_o : out std_logic_vector(g_width / 8 - 1 downto 0);
STB_o : out std_logic;
ACK_i : in std_logic;
WE_o : out std_logic;
STALL_i : in std_logic;
INT_ack : out std_logic;
IRQ_i : in std_logic;
leds : out std_logic_vector(7 downto 0));
end component;
signal rst : std_logic;
signal dummy_adr, dummy_dat, dummy_sel : std_logic_vector(63 downto 0);
signal rst_in, rst_out : std_logic;
signal dat_out, dat_in : std_logic_vector(31 downto 0);
signal adr_out : std_logic_vector(63 downto 0);
begin -- wrapper
rst <= not rst_n_i;
rst_in <= not rst_n_i;
rst_n_o <= rst_n_i and (not rst_out);
U_Wrapped_VME : VME64xCore_Top
port map (
clk_i => clk_i,
VME_AS_n_i => VME_AS_n_i,
VME_RST_n_i => VME_RST_n_i,
VME_WRITE_n_i => VME_WRITE_n_i,
VME_AM_i => VME_AM_i,
VME_DS_n_i => VME_DS_n_i,
VME_GA_i => VME_GA_i,
VME_BERR_o => VME_BERR_o,
VME_DTACK_n_o => VME_DTACK_n_o,
VME_RETRY_n_o => VME_RETRY_n_o,
VME_RETRY_OE_o => VME_RETRY_OE_o,
VME_LWORD_n_b => VME_LWORD_n_b,
VME_ADDR_b => VME_ADDR_b,
VME_DATA_b => VME_DATA_b,
VME_BBSY_n_i => VME_BBSY_n_i,
VME_IRQ_n_o => VME_IRQ_n_o,
VME_IACK_n_i => VME_IACK_n_i,
VME_IACKIN_n_i => VME_IACKIN_n_i,
VME_IACKOUT_n_o => VME_IACKOUT_n_o,
VME_DTACK_OE_o => VME_DTACK_OE_o,
VME_DATA_DIR_o => VME_DATA_DIR_o,
VME_DATA_OE_N_o => VME_DATA_OE_N_o,
VME_ADDR_DIR_o => VME_ADDR_DIR_o,
VME_ADDR_OE_N_o => VME_ADDR_OE_N_o,
RST_i => rst_n_i,
DAT_i(31 downto 0) => master_i.dat,
DAT_i(63 downto 32) => x"00000000",
DAT_o(31 downto 0) => master_o.dat,
DAT_o(63 downto 32) => dummy_dat(63 downto 32),
ADR_o(31 downto 0) => master_o.adr,
ADR_o(63 downto 32) => dummy_adr(63 downto 32),
CYC_o => master_o.cyc,
ERR_i => master_i.err,
LOCK_o => open,
RTY_i => master_i.rty,
SEL_o(3 downto 0) => master_o.sel,
SEL_o(7 downto 4) => dummy_sel(7 downto 4),
STB_o => master_o.stb,
ACK_i => master_i.ack,
WE_o => master_o.we,
STALL_i => master_i.stall,
IRQ_i => irq_i);
clk_i => clk_i,
reset_o => rst_out,
VME_AS_n_i => VME_AS_n_i,
VME_RST_n_i => VME_RST_n_i,
VME_WRITE_n_i => VME_WRITE_n_i,
VME_AM_i => VME_AM_i,
VME_DS_n_i => VME_DS_n_i,
VME_GA_i => VME_GA_i,
VME_BERR_o => VME_BERR_o,
VME_DTACK_n_o => VME_DTACK_n_o,
VME_RETRY_n_o => VME_RETRY_n_o,
VME_RETRY_OE_o => VME_RETRY_OE_o,
VME_LWORD_n_b_i => VME_LWORD_n_b_i,
VME_LWORD_n_b_o => VME_LWORD_n_b_o,
VME_ADDR_b_i => VME_ADDR_b_i,
VME_ADDR_b_o => VME_ADDR_b_o,
VME_DATA_b_i => VME_DATA_b_i,
VME_DATA_b_o => VME_DATA_b_o,
VME_IRQ_n_o => VME_IRQ_n_o,
VME_IACKIN_n_i => VME_IACKIN_n_i,
VME_IACK_n_i => VME_IACK_n_i,
VME_IACKOUT_n_o => VME_IACKOUT_n_o,
VME_DTACK_OE_o => VME_DTACK_OE_o,
VME_DATA_DIR_o => VME_DATA_DIR_o,
VME_DATA_OE_N_o => VME_DATA_OE_N_o,
VME_ADDR_DIR_o => VME_ADDR_DIR_o,
VME_ADDR_OE_N_o => VME_ADDR_OE_N_o,
DAT_i => dat_in,
DAT_o => dat_out,
ADR_o => adr_out,
CYC_o => master_o.cyc,
ERR_i => master_i.err,
RTY_i => master_i.rty,
SEL_o => open,
STB_o => master_o.stb,
ACK_i => master_i.ack,
WE_o => master_o.we,
STALL_i => master_i.stall,
IRQ_i => irq_i,
INT_ack => irq_ack_o);
master_o.dat <= dat_out(31 downto 0);
master_o.sel <= (others => '1');
master_o.adr <= adr_out(29 downto 0) & "00";
dat_in <= master_i.dat;
end wrapper;
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