Commit 9fe7f7eb authored by Tomasz Wlostowski's avatar Tomasz Wlostowski

hdl: fixed version register layout to match specification

parent 351c88a7
......@@ -307,7 +307,7 @@ begin -- architecture arch
generic map (
g_VENDOR_ID => x"0000_10DC",
g_DEVICE_ID => x"574f_0001", -- SPEC + 1xFine Delay
g_VERSION => x"0003_0004",
g_VERSION => x"0300_0004",
g_CAPABILITIES => x"0000_0000",
g_COMMIT_ID => sourceid_spec_fine_delay_top_pkg.sourceid)
port map (
......
......@@ -414,7 +414,7 @@ begin -- architecture arch
generic map (
g_VENDOR_ID => x"0000_10DC",
g_DEVICE_ID => x"574f_0002", -- SVEC + 2xFineDelay
g_VERSION => x"0003_0004",
g_VERSION => x"0300_0004",
g_CAPABILITIES => x"0000_0000",
g_COMMIT_ID => sourceid_svec_fine_delay_top_pkg.sourceid)
port map (
......
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