added RTL code

99bea106 · Tomasz Wlostowski · 9ed14e39 · 99bea106 · 99bea106 · 99bea106
Commit 99bea106 authored Jun 05, 2011 by Tomasz Wlostowski
10 changed files
--- a/hdl/rtl/Manifest.py
+++ b/hdl/rtl/Manifest.py
+files = ["fd_acam_timestamper.vhd",
+	       "fd_cal_pulse_gen.vhd",
+				 "fd_delay_line_driver.vhd",
+         "fd_wbgen2_pkg.vhd",
+         "fine_delay_core.vhd",
+         "fine_delay_pkg.vhd",
+         "fine_delay_wb.vhd"]
+
+fetchto = "../ip_cores"
+
+modules = {
+
+					 "git" :  [
+										"git@ohwr.org:hdl-core-lib/wr-cores.git",
+										"git@ohwr.org:hdl-core-lib/general-cores.git" ],
+   				 "svn" : [ "http://svn.ohwr.org/gn4124-core/branches/hdlmake-compliant/rtl" ]
+
+					}
+
--- a/hdl/rtl/build_wb.sh
+++ b/hdl/rtl/build_wb.sh
+#!/bin/bash
+
+~/wbgen2/wishbone-gen/wbgen2 -V fine_delay_wb.vhd -H record -p fd_registers_pkg.vhd -K ../sim/fine_delay_regs.v -s defines -C fd_core.h -D 1.html fine_delay_wb.wb 
\ No newline at end of file
--- a/hdl/rtl/fd_acam_timestamper.vhd
+++ b/hdl/rtl/fd_acam_timestamper.vhd
--- a/hdl/rtl/fd_cal_pulse_gen.vhd
+++ b/hdl/rtl/fd_cal_pulse_gen.vhd
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity fd_cal_pulse_gen is
+
+  port(
+    clk_sys_i : in std_logic;
+    rst_n_i   : in std_logic;
+
+    pulse_o : out std_logic;
+
+    pgcr_enable_i : in std_logic;
+    pgcr_period_i : in std_logic_vector(30 downto 0)
+    );
+
+
+end fd_cal_pulse_gen;
+
+architecture behavioral of fd_cal_pulse_gen is
+
+  signal counter : unsigned(30 downto 0);
+  signal pulse_int : std_logic;
+  
+begin  -- behavioral
+
+  process(clk_sys_i)
+  begin
+    if rising_edge(clk_sys_i) then
+      if rst_n_i = '0' or pgcr_enable_i = '0' then
+        pulse_int <= '0';
+        counter <= to_unsigned(1, counter'length);
+      else
+        if(counter = unsigned(pgcr_period_i)) then
+          counter <= to_unsigned(1, counter'length);
+          pulse_int <= not pulse_int;
+        else
+          counter <= counter + 1;
+        end if;
+
+        pulse_o <= pulse_int;
+      end if;
+    end if;
+  end process;
+
+end behavioral;
--- a/hdl/rtl/fd_delay_line_driver.vhd
+++ b/hdl/rtl/fd_delay_line_driver.vhd
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+use work.fine_delay_pkg.all;
+
+entity delay_line_driver is
+  
+
+  port(
+    clk_ref_i : in std_logic;
+    rst_n_i   : in std_logic;
+
+    -- time base synchronization
+    csync_time_i : in t_fd_timestamp;
+    csync_p1_i   : in std_logic;
+
+    ch_start_i    : in  t_fd_timestamp_array;
+    ch_length_i   : in  t_fd_timestamp_array;
+    ch_load_p1_i  : in  std_logic_vector(c_fd_num_outputs-1 downto 0);
+    ch_polarity_i : in  std_logic_vector(c_fd_num_outputs-1 downto 0);
+    ch_ready_o    : out std_logic_vector(c_fd_num_outputs-1 downto 0);
+
+    delay_bus_o   : out std_logic_vector(9 downto 0);
+    delay_len_o   : out std_logic_vector(c_fd_num_outputs-1 downto 0);
+    delay_pulse_o : out std_logic_vector(c_fd_num_outputs-1 downto 0)
+    );
+
+
+end delay_line_driver;
+
+architecture behavioral of delay_line_driver is
+
+  signal t : t_fd_timestamp;
+
+  type t_adjustment_fsm_state is(A_IDLE, A_FIX_START, A_FIX_END, A_WAIT_ARM);
+
+  type t_channel is record
+    t_start: t_fd_timestamp;
+    t_stop: t_fd_timestamp;
+    t_length: t_fd_timestamp;
+    adj_state: t_adjustment_fsm_state;
+    armed: std_logic;
+    dly_adjusted: std_logic;
+    done: std_logic;
+    issued_start: std_logic;
+  end record;
+
+  type t_channel_array is array(0 to c_fd_num_outputs-1) of t_channel;
+  
+  signal C : t_channel_array;
+  
+begin  -- behavioral
+
+  p_timebase_counter : process(clk_ref_i)
+  begin
+    if rising_edge(clk_ref_i) then
+      if rst_n_i = '0' then
+        t.secs   <= (others => '0');
+        t.cycles <= (others => '0');
+        t.fine   <= (others => '0');
+      else
+        if(csync_p1_i = '1') then
+          t <= csync_time_i;
+        elsif(t.cycles = c_fd_refclk_freq - 1) then
+          t.secs   <= t.secs + 1;
+          t.cycles <= (others => '0');
+        else
+          t.cycles <= t.cycles + 1;
+        end if;
+      end if;
+    end if;
+  end process;
+
+  gen_channels : for i in 0 to c_fd_num_outputs-1 generate
+    
+    
+    p_load_adjust_start_stop : process(clk_ref_i)
+    begin
+
+      if rising_edge(clk_ref_i) then
+        if rst_n_i = '0' then
+          C(i).t_start.cycles <= (others => '0');
+          C(i).t_start.secs   <= (others => '0');
+          C(i).t_start.fine   <= (others => '0');
+          C(i).armed <= '0';
+        else
+
+          case C(i).adj_state is
+            when A_IDLE => 
+              if ch_load_p1_i(i) = '1' then
+                C(i).t_start.fine <= ch_start_i(i).fine;
+                C(i).t_start.cycles <= ch_start_i(i).cycles - 2;  -- 2 cycles in advance
+                C(i).t_start.secs <= ch_start_i(i).secs;
+                C(i).t_length <= ch_length_i(i);
+                C(i).armed <= '1';
+                C(i).adj_state <= A_FIX_START;
+              end if;
+
+            when A_FIX_START =>
+-- calculate the end-of-pulse timestamp
+              C(i).t_stop.fine <= C(i).t_start.fine + C(i).t_length.fine;
+              C(i).t_stop.cycles <= C(i).t_start.cycles + C(i).t_length.cycles;
+              C(i).t_stop.secs <= C(i).t_start.secs + C(i).t_length.secs;
+
+-- unwind start-of-pulse timestamp
+              if(C(i).t_start.cycles(27) = '1') then
+                C(i).t_start.secs <= C(i).t_start.secs + 1;
+                C(i).t_start.cycles <= C(i).t_start.cycles + c_fd_refclk_freq;
+              end if;
+              
+            when others => null;
+
+          end case;
+          
+
+          
+
+            
+
+
+        end if;
+
+      end if;
+    end process;
+  end generate gen_channels;
+  
+
+  
+end behavioral;
--- a/hdl/rtl/fd_wbgen2_pkg.vhd
+++ b/hdl/rtl/fd_wbgen2_pkg.vhd
+---------------------------------------------------------------------------------------
+-- Title          : Wishbone slave core for Fine Delay WB
+---------------------------------------------------------------------------------------
+-- File           : fd_registers_pkg.vhd
+-- Author         : auto-generated by wbgen2 from fine_delay_wb.wb
+-- Created        : Mon May 30 19:41:22 2011
+-- Standard       : VHDL'87
+---------------------------------------------------------------------------------------
+-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE fine_delay_wb.wb
+-- DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
+---------------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+use work.wbgen2_pkg.all;
+
+package fd_wbgen2_pkg is
+  type t_fd_registers is record
+    rstr_o                                   : std_logic_vector(31 downto 0);
+    rstr_wr_o                                : std_logic;
+    gcr_bypass_o                             : std_logic;
+    gcr_input_en_o                           : std_logic;
+    gcr_clr_stat_o                           : std_logic;
+    tar_data_o                               : std_logic_vector(27 downto 0);
+    tar_data_i                               : std_logic_vector(27 downto 0);
+    tar_data_load_o                          : std_logic;
+    tar_addr_o                               : std_logic_vector(3 downto 0);
+    tdcsr_write_o                            : std_logic;
+    tdcsr_read_o                             : std_logic;
+    tdcsr_err_i                              : std_logic;
+    tdcsr_int_i                              : std_logic;
+    tdcsr_load_i                             : std_logic;
+    tdcsr_empty_i                            : std_logic;
+    tdcsr_start_dis_o                        : std_logic;
+    tdcsr_start_en_o                         : std_logic;
+    tdcsr_stop_dis_o                         : std_logic;
+    tdcsr_stop_en_o                          : std_logic;
+    dcr_dly_sel_o                            : std_logic_vector(3 downto 0);
+    dcr_dly_sel_wr_o                         : std_logic;
+    dcr_dly_val_o                            : std_logic_vector(9 downto 0);
+    gpsr_cs_pll_o                            : std_logic;
+    gpsr_cs_pll_wr_o                         : std_logic;
+    gpsr_cs_gpio_o                           : std_logic;
+    gpsr_cs_gpio_wr_o                        : std_logic;
+    gpsr_sclk_o                              : std_logic;
+    gpsr_sclk_wr_o                           : std_logic;
+    gpsr_mosi_o                              : std_logic;
+    gpsr_mosi_wr_o                           : std_logic;
+    gpcr_cs_pll_o                            : std_logic;
+    gpcr_cs_pll_wr_o                         : std_logic;
+    gpcr_cs_gpio_o                           : std_logic;
+    gpcr_cs_gpio_wr_o                        : std_logic;
+    gpcr_sclk_o                              : std_logic;
+    gpcr_sclk_wr_o                           : std_logic;
+    gpcr_mosi_o                              : std_logic;
+    gpcr_mosi_wr_o                           : std_logic;
+    gprr_miso_i                              : std_logic;
+    iecraw_i                                 : std_logic_vector(31 downto 0);
+    iectag_i                                 : std_logic_vector(31 downto 0);
+    iepd_i                                   : std_logic_vector(7 downto 0);
+    pgcr_period_o                            : std_logic_vector(30 downto 0);
+    pgcr_enable_o                            : std_logic;
+    tsfifo_wr_req_i                          : std_logic;
+    tsfifo_wr_full_o                         : std_logic;
+    tsfifo_utc_i                             : std_logic_vector(31 downto 0);
+    tsfifo_coarse_i                          : std_logic_vector(27 downto 0);
+    tsfifo_frac_i                            : std_logic_vector(22 downto 0);
+    tsfifo_frac_raw_i                        : std_logic_vector(22 downto 0);
+    end record;
+  
+  constant c_fd_registers_init_value: t_fd_registers := (
+    rstr_o => (others => 'Z'),
+    rstr_wr_o => 'Z',
+    gcr_bypass_o => 'Z',
+    gcr_input_en_o => 'Z',
+    gcr_clr_stat_o => 'Z',
+    tar_data_o => (others => 'Z'),
+    tar_data_i => (others => 'Z'),
+    tar_data_load_o => 'Z',
+    tar_addr_o => (others => 'Z'),
+    tdcsr_write_o => 'Z',
+    tdcsr_read_o => 'Z',
+    tdcsr_err_i => 'Z',
+    tdcsr_int_i => 'Z',
+    tdcsr_load_i => 'Z',
+    tdcsr_empty_i => 'Z',
+    tdcsr_start_dis_o => 'Z',
+    tdcsr_start_en_o => 'Z',
+    tdcsr_stop_dis_o => 'Z',
+    tdcsr_stop_en_o => 'Z',
+    dcr_dly_sel_o => (others => 'Z'),
+    dcr_dly_sel_wr_o => 'Z',
+    dcr_dly_val_o => (others => 'Z'),
+    gpsr_cs_pll_o => 'Z',
+    gpsr_cs_pll_wr_o => 'Z',
+    gpsr_cs_gpio_o => 'Z',
+    gpsr_cs_gpio_wr_o => 'Z',
+    gpsr_sclk_o => 'Z',
+    gpsr_sclk_wr_o => 'Z',
+    gpsr_mosi_o => 'Z',
+    gpsr_mosi_wr_o => 'Z',
+    gpcr_cs_pll_o => 'Z',
+    gpcr_cs_pll_wr_o => 'Z',
+    gpcr_cs_gpio_o => 'Z',
+    gpcr_cs_gpio_wr_o => 'Z',
+    gpcr_sclk_o => 'Z',
+    gpcr_sclk_wr_o => 'Z',
+    gpcr_mosi_o => 'Z',
+    gpcr_mosi_wr_o => 'Z',
+    gprr_miso_i => 'Z',
+    iecraw_i => (others => 'Z'),
+    iectag_i => (others => 'Z'),
+    iepd_i => (others => 'Z'),
+    pgcr_period_o => (others => 'Z'),
+    pgcr_enable_o => 'Z',
+    tsfifo_wr_req_i => 'Z',
+    tsfifo_wr_full_o => 'Z',
+    tsfifo_utc_i => (others => 'Z'),
+    tsfifo_coarse_i => (others => 'Z'),
+    tsfifo_frac_i => (others => 'Z'),
+    tsfifo_frac_raw_i => (others => 'Z')
+  );
+end package;
--- a/hdl/rtl/fine_delay_core.vhd
+++ b/hdl/rtl/fine_delay_core.vhd
--- a/hdl/rtl/fine_delay_pkg.vhd
+++ b/hdl/rtl/fine_delay_pkg.vhd
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+package fine_delay_pkg is
+
+  constant c_fd_num_outputs : integer := 4;
+  constant c_fd_refclk_freq : integer := 125000000;
+  
+  
+  type t_fd_timestamp is record
+    secs   : unsigned(31 downto 0);
+    cycles : unsigned(27 downto 0);
+    fine   : unsigned(11 downto 0);
+  end record;
+
+  type t_fd_timestamp_array is array (0 to c_fd_num_outputs-1) of t_fd_timestamp;
+
+end fine_delay_pkg;
--- a/hdl/rtl/fine_delay_wb.vhd
+++ b/hdl/rtl/fine_delay_wb.vhd
--- a/hdl/rtl/fine_delay_wb.wb
+++ b/hdl/rtl/fine_delay_wb.wb
+-- -*- Mode: LUA; tab-width: 2 -*-
+
+peripheral {
+	 name = "Fine Delay WB";
+	 hdl_entity = "fine_delay_wb";
+	 prefix = "fd";
+	 
+
+	 reg {
+			name = "Reset Register";
+			prefix = "RSTR";
+
+			field {
+				 name = "Reset trigger";
+				 description = "Writing 0xDEADBEEF into this register will trigger a full reset of the \               				  fine delay core";
+				 type = PASS_THROUGH;
+				 size = 32;
+			};
+	 };
+
+	 reg {
+			name = "Global Control Register";
+			prefix = "GCR";
+			
+			field {
+				 clock = "clk_ref_i";
+
+				 name = "Bypass delay block";
+				 prefix = "BYPASS";
+				 description = "0: normal operation (fine-delay)\
+				           1: TDC and delay lines controlled from the host";
+				 type = BIT;
+				 access_bus = READ_WRITE;
+				 access_dev = READ_ONLY;
+			};
+
+			field {
+				 clock = "clk_ref_i";
+				 
+				 name = "Enabe trigger input";
+				 prefix = "INPUT_EN";
+				 description = "";
+				 type = BIT;
+				 access_bus = READ_WRITE;
+				 access_dev = READ_ONLY;
+			};
+
+			field {
+				 clock = "clk_ref_i";
+
+				 name = "Clear statistics counters";
+				 prefix = "CLR_STAT";
+				 description = "write 1: clears all statistics counters\nwrite 0: no effect";
+				 type = MONOSTABLE;
+			};
+	 };
+
+	 reg {
+			name = "TDC Address/Data Register";
+			prefix = "TAR";
+		
+			field {
+				 clock = "clk_ref_i";
+				 name = "DATA";
+				 prefix = "DATA";
+				 type = SLV;
+				 size = 28;
+				 access_bus = READ_WRITE;
+				 access_dev = READ_WRITE;
+				 load = LOAD_EXT;
+			};
+			
+			field {
+				 clock = "clk_ref_i";
+				 name = "ADDR";
+				 prefix = "ADDR";
+				 type = SLV;
+				 size = 4;
+				 access_bus = READ_WRITE;
+				 access_dev = READ_ONLY;
+			};
+	 };
+
+
+ reg {
+			name = "TDC control/status reg";
+			prefix = "TDCSR";
+
+		  field {
+				 name = "Start TDC write";
+				 prefix = "WRITE";
+				 clock = "clk_ref_i";
+				 type = MONOSTABLE;
+			};
+
+			field {
+				 name = "Start TDC read";
+				 prefix = "READ";
+				 clock = "clk_ref_i";
+				 type = MONOSTABLE;
+			};
+		
+		 
+
+			field {
+				 clock = "clk_ref_i";
+				 name = "Error flag";
+				 prefix = "ERR";
+				 type = BIT;
+				 access_bus = READ_ONLY;
+				 access_dev = WRITE_ONLY;
+			};
+
+			field {
+				 clock = "clk_ref_i";
+				 name = "Interrupt flag";
+				 prefix = "INT";
+				 type = BIT;
+				 access_bus = READ_ONLY;
+				 access_dev = WRITE_ONLY;
+			};
+
+			field {
+				 clock = "clk_ref_i";
+				 name = "Load flag";
+				 prefix = "LOAD";
+				 type = BIT;
+				 access_bus = READ_ONLY;
+				 access_dev = WRITE_ONLY;
+			};
+
+			field {
+				 clock = "clk_ref_i";
+				 name = "Empty flag";
+				 prefix = "EMPTY";
+				 type = BIT;
+				 access_bus = READ_ONLY;
+				 access_dev = WRITE_ONLY;
+			};
+
+			field {
+				 clock = "clk_ref_i";
+				 name = "Start disable";
+				 prefix = "START_DIS";
+				 type = MONOSTABLE;
+			};
+
+			field {
+				 clock = "clk_ref_i";
+				 name = "Start enable";
+				 prefix = "START_EN";
+				 type = MONOSTABLE;
+			};
+
+			field {
+				 clock = "clk_ref_i";
+				 name = "Start disable";
+				 prefix = "STOP_DIS";
+				 type = MONOSTABLE;
+			};
+
+			field {
+				 clock = "clk_ref_i";
+				 name = "Start enable";
+				 prefix = "STOP_EN";
+				 type = MONOSTABLE;
+			};
+
+	 };
+
+	 reg {
+			name = "Delay Control Register";
+			prefix = "DCR";
+
+		field {
+			 clock = "clk_ref_i";
+			 name = "Delay line select";
+			 description = "Each bit selects the delays to which the value shall be written";
+			 prefix = "DLY_SEL";
+			 size = 4;
+			 type = PASS_THROUGH;
+			};
+
+
+		field {
+			 clock = "clk_ref_i";
+			 name = "Delay value";
+			 prefix = "DLY_VAL";
+			 type = SLV;
+			 size = 10;
+			 access_bus = READ_WRITE;
+			 access_dev = READ_ONLY;
+			};
+	 };
+
+	 reg {
+			name = "GPIO set register";
+			prefix = "GPSR";
+
+			field {
+				 name = "SPI PLL chip select";
+				 prefix = "cs_pll";
+				 type = PASS_THROUGH;
+				 size = 1;
+			};
+
+			field {
+				 name = "SPI GPIO chip select";
+				 prefix = "cs_gpio";
+				 type = PASS_THROUGH;
+				 size = 1;
+			};
+			
+			field {
+				 name = "SPI SCLK";
+				 prefix = "sclk";
+				 type = PASS_THROUGH;
+				 size = 1;
+			};
+
+			field {
+				 name = "SPI MOSI";
+				 prefix = "mosi";
+				 type = PASS_THROUGH;
+				 size = 1;
+			};
+	 };
+
+	 reg {
+			name = "GPIO clear register";
+			prefix = "GPCR";
+
+			field {
+				 name = "SPI PLL chip select";
+				 prefix = "cs_pll";
+				 type = PASS_THROUGH;
+				 size = 1;
+			};
+
+			field {
+				 name = "SPI GPIO chip select";
+				 prefix = "cs_gpio";
+				 type = PASS_THROUGH;
+				 size = 1;
+			};
+			
+			field {
+				 name = "SPI SCLK";
+				 prefix = "sclk";
+				 type = PASS_THROUGH;
+				 size = 1;
+			};
+
+			field {
+				 name = "SPI MOSI";
+				 prefix = "mosi";
+				 type = PASS_THROUGH;
+				 size = 1;
+			};
+	 };
+
+	 reg {
+			name = "GPIO Readback Register";
+			prefix = "GPRR";
+
+			field {
+				 name = "SPI MISO";
+				 prefix = "miso";
+				 type = BIT;
+				 access_bus = READ_ONLY;
+				 access_dev = WRITE_ONLY;
+			};
+	 };
+
+	 reg {
+			name = "Raw Input Events Counter Register ";
+			prefix = "IECRAW";
+
+			field {
+				 name = "Number of raw events";
+				 description = "Number of all input pulses detected by the timestamper";
+				 type = SLV;
+				 size = 32;
+				 clock = "clk_ref_i";
+				 access_bus = READ_ONLY;
+				 access_dev= WRITE_ONLY;
+			};
+
+	 };
+
+	 reg {
+			name = "Tagged Input Events Counter Register ";
+			prefix = "IECTAG";
+
+			field {
+				 name = "Number of tagged events";
+				 description = "Number of all input pulses which passed the width checks and have produced valid timestamps.";
+				 type = SLV;
+				 size = 32;
+				 clock = "clk_ref_i";
+				 access_bus = READ_ONLY;
+				 access_dev= WRITE_ONLY;
+			};
+	 };
+
+	 reg {
+			name = "Input Event Processing Delay Register";
+			prefix = "IEPD";
+
+			field {
+				 name = "Processing delay";
+				 description = "Worst-case delay between the input event and the generation of its timestamp. Expressed as a number of 125 MHz clock cycles.";
+				 type = SLV;
+				 size = 8;
+				 clock = "clk_ref_i";
+				 access_bus = READ_ONLY;
+				 access_dev= WRITE_ONLY;
+			};
+	 };
+
+
+	 reg {
+			name = "Pulse Generator Control Register";
+			prefix = "PGCR";
+
+			field {
+				 name = "Pulse period";
+				 prefix = "PERIOD";
+				 type = SLV;
+				 size = 31;
+				 access_bus = READ_WRITE;
+				 access_dev= READ_ONLY;
+			};
+
+			field {
+				 name = "Enable";
+				 prefix = "ENABLE";
+				 type = BIT;
+				 access_bus = READ_WRITE;
+				 access_dev= READ_ONLY;
+			};
+	 };
+	 
+	 fifo_reg {
+			direction = CORE_TO_BUS;
+			prefix = "tsfifo";
+			name = "Timestamp FIFO";
+			
+			clock = "clk_ref_i";
+
+			flags_bus = {FIFO_FULL, FIFO_EMPTY};
+			flags_dev = {FIFO_FULL};
+			
+			size = 512;
+			
+			field {
+						name = "UTC part";
+						prefix = "utc";
+						type = SLV;
+						size = 32;
+
+			};
+
+			field {
+				 name = "Coarse part";
+				 prefix = "coarse";
+				 type = SLV;
+				 size = 28;
+			};
+
+
+			field {
+				 name = "Fractional part (from TDC)";
+				 prefix = "frac";
+				 type = SLV;
+				 size = 23;
+			};
+
+			field {
+				 name = "Raw frac part (from TDC)";
+				 prefix = "frac_raw";
+				 type = SLV;
+				 size = 23;
+			};
+	 };
+};
\ No newline at end of file