Commit 99253dd6 authored by Tomasz Wlostowski's avatar Tomasz Wlostowski

hdl: IODELAY control port in fine_delay_core

parent f6a2b0a9
......@@ -6,7 +6,7 @@
-- Author : Tomasz Wlostowski
-- Company : CERN
-- Created : 2011-08-24
-- Last update: 2014-03-24
-- Last update: 2019-03-21
-- Platform : FPGA-generic
-- Standard : VHDL'93
-------------------------------------------------------------------------------
......@@ -195,7 +195,7 @@ entity fine_delay_core is
owr_i : in std_logic;
---------------------------------------------------------------------------
-- Misc signals: I2C EEPROM, FMC presence
-- Misc signals: I2C EEPROM, FMC presence, I/O calibration
---------------------------------------------------------------------------
i2c_scl_o : out std_logic;
......@@ -207,6 +207,11 @@ entity fine_delay_core is
fmc_present_n_i : in std_logic;
idelay_inc_o : out std_logic;
idelay_cal_o : out std_logic;
idelay_ce_o : out std_logic;
idelay_rst_o : out std_logic;
---------------------------------------------------------------------------
-- Wishbone slave (classic/pipelined)
......@@ -504,6 +509,12 @@ begin -- rtl
);
idelay_rst_o <= regs_fromwb.tdcsr_idelay_rst_o;
idelay_ce_o <= regs_fromwb.tdcsr_idelay_ce_o;
idelay_inc_o <= regs_fromwb.tdcsr_idelay_inc_o and regs_fromwb.tdcsr_idelay_ce_o;
idelay_cal_o <= regs_fromwb.tdcsr_idelay_cal_o;
U_Acam_TSU : fd_acam_timestamper
generic map (
g_min_pulse_width => 3,
......
......@@ -6,7 +6,7 @@
-- Author : Tomasz Wlostowski
-- Company : CERN
-- Created : 2011-08-24
-- Last update: 2014-03-24
-- Last update: 2019-03-21
-- Platform : FPGA-generic
-- Standard : VHDL'93
-------------------------------------------------------------------------------
......@@ -237,32 +237,6 @@ package fine_delay_pkg is
regs_o : out t_fd_channel_out_registers);
end component;
component fd_main_wb_slave
port (
rst_n_i : in std_logic;
clk_sys_i : in std_logic;
wb_adr_i : in std_logic_vector(5 downto 0);
wb_dat_i : in std_logic_vector(31 downto 0);
wb_dat_o : out std_logic_vector(31 downto 0);
wb_cyc_i : in std_logic;
wb_sel_i : in std_logic_vector(3 downto 0);
wb_stb_i : in std_logic;
wb_we_i : in std_logic;
wb_ack_o : out std_logic;
wb_stall_o : out std_logic;
wb_int_o : out std_logic;
clk_ref_i : in std_logic;
tcr_rd_ack_o : out std_logic;
dmtr_in_rd_ack_o : out std_logic;
dmtr_out_rd_ack_o : out std_logic;
tsbcr_read_ack_o : out std_logic;
fid_read_ack_o : out std_logic;
irq_ts_buf_notempty_i : in std_logic;
irq_dmtd_spll_i : in std_logic;
irq_sync_status_i : in std_logic;
regs_i : in t_fd_main_in_registers;
regs_o : out t_fd_main_out_registers);
end component;
component fd_delay_line_arbiter
port (
......@@ -436,6 +410,10 @@ package fine_delay_pkg is
i2c_sda_oen_o : out std_logic;
i2c_sda_i : in std_logic;
fmc_present_n_i : in std_logic;
idelay_inc_o : out std_logic;
idelay_cal_o : out std_logic;
idelay_ce_o : out std_logic;
idelay_rst_o : out std_logic;
wb_adr_i : in std_logic_vector(c_wishbone_address_width-1 downto 0);
wb_dat_i : in std_logic_vector(c_wishbone_data_width-1 downto 0);
wb_dat_o : out std_logic_vector(c_wishbone_data_width-1 downto 0);
......
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