Commit 90db6efe authored by Tomasz Wlostowski's avatar Tomasz Wlostowski

Merge branch 'gmode'

Conflicts:
	hdl/rtl/fd_acam_timestamp_postprocessor.vhd
	hdl/rtl/fd_acam_timestamper.vhd
	hdl/testbench/svec_wr_top/main.sv
	hdl/top/spec/wr/spec_top.vhd
	hdl/top/svec/wr/svec_top.ucf
	hdl/top/svec/wr/svec_top.vhd
parents a7736c9b a989eb86
...@@ -119,11 +119,15 @@ module acam_model ...@@ -119,11 +119,15 @@ module acam_model
// //
time t_prev;
always@(posedge DStart) always@(posedge DStart)
if(PuResN && !StartDis && !start_disabled_int) begin if(PuResN && !StartDis && !start_disabled_int) begin
// if(g_verbose)$display("acam::start %d", t); // if(g_verbose)$display("acam::start %d", t);
q_start.put(t); q_start.put(t);
// $display("StartEvt %d [delta %d]\n", t, t-t_prev);
// t_prev = t;
start_disabled_int <= r_StartDisStart; start_disabled_int <= r_StartDisStart;
end end
...@@ -185,8 +189,8 @@ module acam_model ...@@ -185,8 +189,8 @@ module acam_model
else else
break; break;
end end
if(t_stop1 - t_start > 3780) if(t_stop1 - t_start > 8520)
hit = (t_stop1 - t_start) - (128ns/g_rmode_resolution) + rmode_start_offset * 3; hit = (t_stop1 - t_start) - (256ns/g_rmode_resolution) + rmode_start_offset * 3;
else else
hit = t_stop1 - t_start + rmode_start_offset * 3; hit = t_stop1 - t_start + rmode_start_offset * 3;
......
...@@ -67,6 +67,17 @@ module svec_vme_buffers ( ...@@ -67,6 +67,17 @@ module svec_vme_buffers (
pullup(slave.write_n); pullup(slave.write_n);
pulldown(slave.bbsy_n); pulldown(slave.bbsy_n);
pullup(slave.iackin_n); pullup(slave.iackin_n);
pullup(slave.iackout_n);
genvar i;
generate
for(i=0;i<6;i++)
assign slave.irq_n[i] = (VME_IRQ_n_i[i] ? 1'b0 : 1'bz);
endgenerate
assign VME_RST_n_o = slave.rst_n; assign VME_RST_n_o = slave.rst_n;
...@@ -93,6 +104,8 @@ module svec_vme_buffers ( ...@@ -93,6 +104,8 @@ module svec_vme_buffers (
assign slave.dtack_n = VME_DTACK_n_i; assign slave.dtack_n = VME_DTACK_n_i;
assign slave.berr_n = ~VME_BERR_i; assign slave.berr_n = ~VME_BERR_i;
assign slave.retry_n = VME_RETRY_n_i; assign slave.retry_n = VME_RETRY_n_i;
assign slave.iackout_n = VME_IACKOUT_n_i;
endmodule endmodule
......
...@@ -187,7 +187,7 @@ typedef enum { DONT_CARE = 'h100, ...@@ -187,7 +187,7 @@ typedef enum { DONT_CARE = 'h100,
} vme_addr_size_t; } vme_addr_size_t;
typedef enum { typedef enum {
SINGLE = 'h10, CR_CSR='h20, MBLT='h30, BLT='h40, LCK='h50, TwoeVME='h60, TwoeSST='h70 } vme_xfer_type_t; SINGLE = 'h10, CR_CSR='h20, MBLT='h30, BLT='h40, LCK='h50, TwoeVME='h60, TwoeSST='h70, IACK = 'h80 } vme_xfer_type_t;
typedef enum { D08Byte0='h1, D08Byte1='h2, D08Byte2='h3, D08Byte3='h4, D16Byte01='h5, D16Byte23='h6, D32='h7 } vme_data_type_t ; typedef enum { D08Byte0='h1, D08Byte1='h2, D08Byte2='h3, D08Byte3='h4, D16Byte01='h5, D16Byte23='h6, D32='h7 } vme_data_type_t ;
...@@ -207,17 +207,48 @@ class CBusAccessor_VME64x extends CBusAccessor; ...@@ -207,17 +207,48 @@ class CBusAccessor_VME64x extends CBusAccessor;
protected bit [4:0] m_ga; protected bit [4:0] m_ga;
virtual IVME64X.tb vme; virtual IVME64X.tb vme;
function new(virtual IVME64X.tb _vme); function new(virtual IVME64X.tb _vme);
vme = _vme; vme = _vme;
m_ga = 6'b010111; m_ga = 6'b010111;
vme.q_ga = m_ga; vme.q_ga = m_ga;
m_ba = 8'b10000000;
endfunction // new endfunction // new
protected task acknowledge_irq(int level, ref int vector);
`assert_wait(tmo_rws_bus_free, vme.dtack_n && vme.berr_n, 10us)
release_bus();
#40ns;
vme.q_addr[3:1] = level;
vme.q_iackin_n = 1'b0;
vme.q_iack_n = 1'b0;
vme.q_am = 'h29;
#100ns;
vme.q_as_n = 1'b0;
#100ns;
vme.q_ds_n[0] = 1'b0;
`assert_wait(tmo_rws_bus_idle, !vme.dtack_n || !vme.berr_n, 4us)
if(!vme.berr_n)
$error("[rw_simple_generic]: VME bus error.");
vector = vme.data;
vme.q_iackin_n = 1'b1;
vme.q_iack_n = 1'b1;
#100ns;
release_bus();
endtask
protected task set_address(uint64_t addr_in, vme_addr_size_t asize, vme_xfer_type_t xtype); protected task set_address(uint64_t addr_in, vme_addr_size_t asize, vme_xfer_type_t xtype);
bit[63:0] a = addr_in; bit[63:0] a = addr_in;
bit [31:0] a_out; bit [31:0] a_out;
const bit [5:0] am_map [int] = const bit [5:0] am_map [int] =
'{ '{
A32 | CR_CSR : 6'b101111, A32 | CR_CSR : 6'b101111,
...@@ -248,11 +279,11 @@ class CBusAccessor_VME64x extends CBusAccessor; ...@@ -248,11 +279,11 @@ class CBusAccessor_VME64x extends CBusAccessor;
a_out = {8'h0, ~m_ga[4:0], a[18:0]}; a_out = {8'h0, ~m_ga[4:0], a[18:0]};
else case(asize) else case(asize)
A16: A16:
a_out = {16'h0, m_ba[7:3], a[10:2], 2'b00}; a_out = {16'h0, a[15:2], 2'b00};
A24: A24:
a_out = {8'h0, m_ba[7:3], a[18:2], 2'b00}; a_out = {8'h0, a[23:2], 2'b00};
A32: A32:
a_out = {m_ba[7:3], a[26:2], 2'b00}; a_out = { a[31:2], 2'b00};
endcase // case (xtype) endcase // case (xtype)
vme.q_addr[31:2] = a_out[31:2]; vme.q_addr[31:2] = a_out[31:2];
...@@ -399,7 +430,30 @@ class CBusAccessor_VME64x extends CBusAccessor; ...@@ -399,7 +430,30 @@ class CBusAccessor_VME64x extends CBusAccessor;
writem(aa, da, size, result); writem(aa, da, size, result);
endtask endtask
task handle_irqs(ref int done);
done = 0;
if(vme.irq_n != 7'h7f)
begin
int i,level, vector;
for(i=6;i>=0;i--)
if(!vme.irq_n[i])
begin
level = i+1;
break;
end
$display("vme64x_bfm: got irq level %d", level);
acknowledge_irq(level, vector);
$display("vme64x_bfm: vector %x", vector);
done = 1;
end
endtask // handle_irqs
endclass // CBusAccessor_VME64x endclass // CBusAccessor_VME64x
......
...@@ -6,7 +6,7 @@ ...@@ -6,7 +6,7 @@
-- Author : Tomasz Wlostowski -- Author : Tomasz Wlostowski
-- Company : CERN -- Company : CERN
-- Created : 2011-08-29 -- Created : 2011-08-29
-- Last update: 2013-02-21 -- Last update: 2013-02-06
-- Platform : FPGA-generic -- Platform : FPGA-generic
-- Standard : VHDL'93 -- Standard : VHDL'93
------------------------------------------------------------------------------- -------------------------------------------------------------------------------
...@@ -62,20 +62,20 @@ entity fd_acam_timestamp_postprocessor is ...@@ -62,20 +62,20 @@ entity fd_acam_timestamp_postprocessor is
raw_utc_i : in std_logic_vector(c_TIMESTAMP_UTC_BITS-1 downto 0); raw_utc_i : in std_logic_vector(c_TIMESTAMP_UTC_BITS-1 downto 0);
-- "start number" (value of coarse counter, counting at every start pulse of the -- "start number" (value of coarse counter, counting at every start pulse of the
-- TDC, i.e. 125 MHz / 16 = 7.8215 MHz) -- TDC, i.e. 125 MHz / 32 = 3.90625 MHz)
raw_coarse_i : in std_logic_vector(c_TIMESTAMP_COARSE_BITS-4-1 downto 0); raw_coarse_i : in std_logic_vector(c_TIMESTAMP_COARSE_BITS-5-1 downto 0);
-- raw fractional timestamp generated by ACAM -- raw fractional timestamp generated by ACAM
raw_frac_i : in std_logic_vector(22 downto 0); raw_frac_i : in std_logic_vector(22 downto 0);
-- coarse offset (in 125 MHz clock cycles) from the last ACAM's start pulse to the -- coarse offset (in 125 MHz clock cycles) from the last ACAM's start pulse to the
-- input pulse (0..15) -- input pulse (0..15)
raw_start_offset_i : in std_logic_vector(3 downto 0); raw_start_offset_i : in std_logic_vector(4 downto 0);
-- Offset between the actual timescale and the ACAM fixed start signal generated -- Offset between the actual timescale and the ACAM fixed start signal generated
-- by the AD9516 PLL. Used to align the timestamps to the externally -- by the AD9516 PLL. Used to align the timestamps to the externally
-- provided time base (e.g. by White Rabbit). -- provided time base (e.g. by White Rabbit).
acam_subcycle_offset_i : in std_logic_vector(4 downto 0); acam_subcycle_offset_i : in std_logic_vector(5 downto 0);
--------------------------------------------------------------------------- ---------------------------------------------------------------------------
-- Post-processed timestamp. WARNING! DE-NORMALIZED! -- Post-processed timestamp. WARNING! DE-NORMALIZED!
...@@ -148,7 +148,7 @@ begin -- behavioral ...@@ -148,7 +148,7 @@ begin -- behavioral
pp_pipe(0) <= raw_valid_i; pp_pipe(0) <= raw_valid_i;
post_frac_start_adj <= signed(raw_frac_i) - signed(regs_i.asor_offset_o); post_frac_start_adj <= signed(raw_frac_i) - signed(regs_i.asor_offset_o);
post_tag_coarse(3 downto 0) <= (others => '0'); post_tag_coarse(4 downto 0) <= (others => '0');
post_tag_utc <= unsigned(raw_utc_i); post_tag_utc <= unsigned(raw_utc_i);
-- pipeline stage 2: -- pipeline stage 2:
...@@ -162,9 +162,9 @@ begin -- behavioral ...@@ -162,9 +162,9 @@ begin -- behavioral
pp_pipe(1) <= pp_pipe(0); pp_pipe(1) <= pp_pipe(0);
if (unsigned(raw_start_offset_i) <= unsigned(regs_i.atmcr_c_thr_o)) and (post_frac_start_adj > signed(regs_i.atmcr_f_thr_o)) then if (unsigned(raw_start_offset_i) <= unsigned(regs_i.atmcr_c_thr_o)) and (post_frac_start_adj > signed(regs_i.atmcr_f_thr_o)) then
post_tag_coarse(post_tag_coarse'left downto 4) <= unsigned(raw_coarse_i) - 1; post_tag_coarse(post_tag_coarse'left downto 5) <= unsigned(raw_coarse_i) - 1;
else else
post_tag_coarse(post_tag_coarse'left downto 4) <= unsigned(raw_coarse_i); post_tag_coarse(post_tag_coarse'left downto 5) <= unsigned(raw_coarse_i);
end if; end if;
-- Pipeline stage 3: -- Pipeline stage 3:
...@@ -212,18 +212,19 @@ begin -- behavioral ...@@ -212,18 +212,19 @@ begin -- behavioral
-- extra coarse counts from ACAM's frac part after rescaling -- extra coarse counts from ACAM's frac part after rescaling
tag_frac_o <= std_logic_vector(post_frac_multiplied_d0(c_SCALER_SHIFT + g_frac_bits-1 downto c_SCALER_SHIFT)); tag_frac_o <= std_logic_vector(post_frac_multiplied_d0(c_SCALER_SHIFT + g_frac_bits-1 downto c_SCALER_SHIFT));
tag_valid_o <= pp_pipe(4); tag_valid_o <= pp_pipe(4);
elsif(raw_valid_i = '1') then elsif(raw_valid_i = '1') then
tag_utc_o <= raw_utc_i; tag_utc_o <= raw_utc_i;
tag_coarse_o <= raw_coarse_i & raw_start_offset_i; tag_coarse_o <= raw_coarse_i & raw_start_offset_i;
tag_frac_o <= raw_frac_i(11 downto 0); tag_frac_o <= raw_frac_i(11 downto 0);
tag_dbg_raw_o(10 downto 0) <= raw_frac_i(22 downto 12); tag_dbg_raw_o(10 downto 0) <= raw_frac_i(22 downto 12);
tag_dbg_raw_o(15 downto 11) <= acam_subcycle_offset_i; tag_dbg_raw_o(15 downto 11) <= acam_subcycle_offset_i(4 downto 0);
tag_dbg_raw_o(23 downto 16) <= raw_coarse_i(7 downto 0); tag_dbg_raw_o(23 downto 16) <= raw_coarse_i(7 downto 0);
tag_dbg_raw_o(31 downto 24) <= raw_utc_i(7 downto 0); tag_dbg_raw_o(30 downto 24) <= raw_utc_i(6 downto 0);
tag_dbg_raw_o(31) <= acam_subcycle_offset_i(5);
tag_valid_o <= '1'; tag_valid_o <= '1';
else else
......
...@@ -6,7 +6,7 @@ ...@@ -6,7 +6,7 @@
-- Author : Tomasz Wlostowski -- Author : Tomasz Wlostowski
-- Company : CERN -- Company : CERN
-- Created : 2011-08-24 -- Created : 2011-08-24
-- Last update: 2013-02-21 -- Last update: 2013-02-12
-- Platform : FPGA-generic -- Platform : FPGA-generic
-- Standard : VHDL'93 -- Standard : VHDL'93
------------------------------------------------------------------------------- -------------------------------------------------------------------------------
...@@ -165,10 +165,10 @@ architecture behavioral of fd_acam_timestamper is ...@@ -165,10 +165,10 @@ architecture behavioral of fd_acam_timestamper is
rst_n_i : in std_logic; rst_n_i : in std_logic;
raw_valid_i : in std_logic; raw_valid_i : in std_logic;
raw_utc_i : in std_logic_vector(c_TIMESTAMP_UTC_BITS-1 downto 0); raw_utc_i : in std_logic_vector(c_TIMESTAMP_UTC_BITS-1 downto 0);
raw_coarse_i : in std_logic_vector(c_TIMESTAMP_COARSE_BITS-4-1 downto 0); raw_coarse_i : in std_logic_vector(c_TIMESTAMP_COARSE_BITS-5-1 downto 0);
raw_frac_i : in std_logic_vector(22 downto 0); raw_frac_i : in std_logic_vector(22 downto 0);
raw_start_offset_i : in std_logic_vector(3 downto 0); raw_start_offset_i : in std_logic_vector(4 downto 0);
acam_subcycle_offset_i : in std_logic_vector(4 downto 0); acam_subcycle_offset_i : in std_logic_vector(5 downto 0);
tag_valid_o : out std_logic; tag_valid_o : out std_logic;
tag_utc_o : out std_logic_vector(c_TIMESTAMP_UTC_BITS-1 downto 0); tag_utc_o : out std_logic_vector(c_TIMESTAMP_UTC_BITS-1 downto 0);
tag_coarse_o : out std_logic_vector(c_TIMESTAMP_COARSE_BITS-1 downto 0); tag_coarse_o : out std_logic_vector(c_TIMESTAMP_COARSE_BITS-1 downto 0);
...@@ -222,18 +222,18 @@ architecture behavioral of fd_acam_timestamper is ...@@ -222,18 +222,18 @@ architecture behavioral of fd_acam_timestamper is
signal trig_pulse : std_logic; signal trig_pulse : std_logic;
-- counters (internal time base) -- counters (internal time base)
signal start_count : unsigned(3 downto 0); signal start_count : unsigned(4 downto 0);
signal coarse_count : unsigned(c_TIMESTAMP_COARSE_BITS-4-1 downto 0); signal coarse_count : unsigned(c_TIMESTAMP_COARSE_BITS-5-1 downto 0);
signal utc_count : unsigned(c_TIMESTAMP_UTC_BITS-1 downto 0); signal utc_count : unsigned(c_TIMESTAMP_UTC_BITS-1 downto 0);
signal subcycle_offset : signed(4 downto 0); signal subcycle_offset : signed(5 downto 0);
signal gcr_input_en_d0 : std_logic; signal gcr_input_en_d0 : std_logic;
-- raw (unprocessed) time tag -- raw (unprocessed) time tag
signal raw_tag_valid : std_logic; signal raw_tag_valid : std_logic;
signal raw_tag_coarse : unsigned(c_TIMESTAMP_COARSE_BITS-4-1 downto 0); signal raw_tag_coarse : unsigned(c_TIMESTAMP_COARSE_BITS-5-1 downto 0);
signal raw_tag_frac : signed(22 downto 0); signal raw_tag_frac : signed(22 downto 0);
signal raw_tag_start_offset : unsigned(3 downto 0); signal raw_tag_start_offset : unsigned(4 downto 0);
signal raw_tag_utc : unsigned(c_TIMESTAMP_UTC_BITS-1 downto 0); signal raw_tag_utc : unsigned(c_TIMESTAMP_UTC_BITS-1 downto 0);
signal width_check_sreg : std_logic_vector(g_min_pulse_width-2 downto 0); signal width_check_sreg : std_logic_vector(g_min_pulse_width-2 downto 0);
...@@ -401,11 +401,14 @@ begin -- behave ...@@ -401,11 +401,14 @@ begin -- behave
else else
-- Enable the start input at proper moment to ensure that the 7.125 MHz -- Enable the start input at proper moment to ensure that the 7.125 MHz
-- "start clock" cycle is not cut. -- "start clock" cycle is not cut.
if(start_count = x"e") then if(start_count = x"8") then
-- advance the start OK shift register with another one. -- advance the start OK shift register with another one.
start_ok_sreg <= start_ok_sreg(start_ok_sreg'left-1 downto 0) & '1'; start_ok_sreg <= start_ok_sreg(start_ok_sreg'left-1 downto 0) & '1';
acam_start_dis_o <= '1';
elsif (start_count = x"18") then
acam_start_dis_o <= '0'; acam_start_dis_o <= '0';
end if; end if;
end if; end if;
end if; end if;
end if; end if;
...@@ -440,6 +443,8 @@ begin -- behave ...@@ -440,6 +443,8 @@ begin -- behave
end if; end if;
end process; end process;
-- Process: p_sync_acam_ef -- Process: p_sync_acam_ef
-- Input: acam_ef_i -- Input: acam_ef_i
-- Output: acam_ef_d1 -- Output: acam_ef_d1
...@@ -457,6 +462,17 @@ begin -- behave ...@@ -457,6 +462,17 @@ begin -- behave
-- Time Base Counters -- Time Base Counters
------------------------------------------------------------------------------- -------------------------------------------------------------------------------
p_gen_start_mask : process(clk_ref_i)
begin
if rising_edge(clk_ref_i) then
if rst_n_i = '0' then
start_mask <= '0';
elsif(tdc_start_d(1) = '1' and tdc_start_d(2) = '0') then
start_mask <= not start_mask;
end if;
end if;
end process;
-- Start counter: counts the number of clk_ref_i cycles from the last TDC start -- Start counter: counts the number of clk_ref_i cycles from the last TDC start
-- event. -- event.
...@@ -476,18 +492,18 @@ begin -- behave ...@@ -476,18 +492,18 @@ begin -- behave
-- between the current start count and the LSBs of the new time value -- between the current start count and the LSBs of the new time value
-- and correct the timestamps later on. -- and correct the timestamps later on.
if(csync_p1_i = '1') then if(csync_p1_i = '1') then
subcycle_offset <= signed('0' & csync_coarse_i(3 downto 0)) - signed('0' & start_count) - 1; subcycle_offset <= signed('0' & csync_coarse_i(4 downto 0)) - signed('0' & start_count) - 1;
end if; end if;
-- Rising edge on TDC_START? Resynchronize the counter, to go to zero -- Rising edge on TDC_START? Resynchronize the counter, to go to zero
-- right after the edge. -- right after the edge.
if(tdc_start_d(1) = '1' and tdc_start_d(2) = '0') then if(tdc_start_d(1) = '1' and tdc_start_d(2) = '0' and start_mask = '0') then
start_count <= x"2"; start_count <= to_unsigned(2, 5);
advance_coarse <= '0'; advance_coarse <= '0';
else else
-- Start cycle expired - advance the 128 ns x counter. We do that one -- Start cycle expired - advance the 128 ns x counter. We do that one
-- cycle in advance using a register to relax the P&R timing. -- cycle in advance using a register to relax the P&R timing.
if(start_count = x"e") then if(start_count = x"1e") then
advance_coarse <= '1'; advance_coarse <= '1';
else else
advance_coarse <= '0'; advance_coarse <= '0';
...@@ -511,13 +527,13 @@ begin -- behave ...@@ -511,13 +527,13 @@ begin -- behave
-- overflow of start_count. -- overflow of start_count.
if(csync_p1_i = '1') then if(csync_p1_i = '1') then
if(advance_coarse = '1') then if(advance_coarse = '1') then
coarse_count <= unsigned(csync_coarse_i(27 downto 4)) + 1; coarse_count <= unsigned(csync_coarse_i(27 downto 5)) + 1;
else else
coarse_count <= unsigned(csync_coarse_i(27 downto 4)); coarse_count <= unsigned(csync_coarse_i(27 downto 5));
end if; end if;
elsif(advance_coarse = '1') then elsif(advance_coarse = '1') then
-- well, just boringly count up -- well, just boringly count up
if(coarse_count = (g_clk_ref_freq / 16) - 1) then if(coarse_count = (g_clk_ref_freq / 32) - 1) then
coarse_count <= (others => '0'); coarse_count <= (others => '0');
else else
coarse_count <= coarse_count + 1; coarse_count <= coarse_count + 1;
...@@ -537,14 +553,14 @@ begin -- behave ...@@ -537,14 +553,14 @@ begin -- behave
utc_count <= (others => '0'); utc_count <= (others => '0');
else else
if(csync_p1_i = '1') then if(csync_p1_i = '1') then
if(advance_coarse = '1' and coarse_count = (g_clk_ref_freq / 16) -1) then if(advance_coarse = '1' and coarse_count = (g_clk_ref_freq / 32) -1) then
-- I hate special cases! -- I hate special cases!
utc_count <= unsigned(csync_utc_i) + 1; utc_count <= unsigned(csync_utc_i) + 1;
else else
utc_count <= unsigned(csync_utc_i); utc_count <= unsigned(csync_utc_i);
end if; end if;
elsif(advance_coarse = '1' and coarse_count = (g_clk_ref_freq / 16) - 1) then elsif(advance_coarse = '1' and coarse_count = (g_clk_ref_freq / 32) - 1) then
utc_count <= utc_count + 1; utc_count <= utc_count + 1;
end if; end if;
...@@ -721,7 +737,8 @@ begin -- behave ...@@ -721,7 +737,8 @@ begin -- behave
when RMODE_READ => when RMODE_READ =>
-- store the fine tag -- store the fine tag
raw_tag_frac <= signed(acam_d_i(raw_tag_frac'left downto 0)); raw_tag_frac(21 downto 0) <= signed(acam_d_i(21 downto 0));
raw_tag_frac(22) <= '0';
-- check if the FIFO has become empty after the readout. If it didn't, the TDC -- check if the FIFO has become empty after the readout. If it didn't, the TDC
......
...@@ -3,7 +3,7 @@ ...@@ -3,7 +3,7 @@
--------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------
-- File : fd_channel_wbgen2_pkg.vhd -- File : fd_channel_wbgen2_pkg.vhd
-- Author : auto-generated by wbgen2 from fd_channel_wishbone_slave.wb -- Author : auto-generated by wbgen2 from fd_channel_wishbone_slave.wb
-- Created : Mon Jun 4 13:42:20 2012 -- Created : Fri Feb 15 12:07:17 2013
-- Standard : VHDL'87 -- Standard : VHDL'87
--------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE fd_channel_wishbone_slave.wb -- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE fd_channel_wishbone_slave.wb
......
...@@ -3,7 +3,7 @@ ...@@ -3,7 +3,7 @@
--------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------
-- File : fd_channel_wishbone_slave.vhd -- File : fd_channel_wishbone_slave.vhd
-- Author : auto-generated by wbgen2 from fd_channel_wishbone_slave.wb -- Author : auto-generated by wbgen2 from fd_channel_wishbone_slave.wb
-- Created : Mon Jun 4 13:42:20 2012 -- Created : Fri Feb 15 12:07:17 2013
-- Standard : VHDL'87 -- Standard : VHDL'87
--------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE fd_channel_wishbone_slave.wb -- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE fd_channel_wishbone_slave.wb
...@@ -161,11 +161,11 @@ begin ...@@ -161,11 +161,11 @@ begin
end if; end if;
rddata_reg(0) <= fd_channel_dcr_enable_int; rddata_reg(0) <= fd_channel_dcr_enable_int;
rddata_reg(1) <= fd_channel_dcr_mode_int; rddata_reg(1) <= fd_channel_dcr_mode_int;
rddata_reg(2) <= 'X'; rddata_reg(2) <= '0';
rddata_reg(3) <= fd_channel_dcr_pg_trig_sync1; rddata_reg(3) <= fd_channel_dcr_pg_trig_sync1;
rddata_reg(4) <= 'X'; rddata_reg(4) <= '0';
rddata_reg(5) <= fd_channel_dcr_upd_done_sync1; rddata_reg(5) <= fd_channel_dcr_upd_done_sync1;
rddata_reg(6) <= 'X'; rddata_reg(6) <= '0';
rddata_reg(7) <= fd_channel_dcr_no_fine_int; rddata_reg(7) <= fd_channel_dcr_no_fine_int;
rddata_reg(8) <= fd_channel_dcr_force_hi_int; rddata_reg(8) <= fd_channel_dcr_force_hi_int;
rddata_reg(9) <= 'X'; rddata_reg(9) <= 'X';
......
...@@ -3,7 +3,7 @@ ...@@ -3,7 +3,7 @@
--------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------
-- File : fd_main_wbgen2_pkg.vhd -- File : fd_main_wbgen2_pkg.vhd
-- Author : auto-generated by wbgen2 from fd_main_wishbone_slave.wb -- Author : auto-generated by wbgen2 from fd_main_wishbone_slave.wb
-- Created : Fri Dec 14 11:28:02 2012 -- Created : Fri Feb 15 12:07:16 2013
-- Standard : VHDL'87 -- Standard : VHDL'87
--------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE fd_main_wishbone_slave.wb -- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE fd_main_wishbone_slave.wb
...@@ -130,7 +130,7 @@ package fd_main_wbgen2_pkg is ...@@ -130,7 +130,7 @@ package fd_main_wbgen2_pkg is
calr_cal_dmtd_o : std_logic; calr_cal_dmtd_o : std_logic;
calr_psel_o : std_logic_vector(3 downto 0); calr_psel_o : std_logic_vector(3 downto 0);
adsfr_o : std_logic_vector(17 downto 0); adsfr_o : std_logic_vector(17 downto 0);
atmcr_c_thr_o : std_logic_vector(3 downto 0); atmcr_c_thr_o : std_logic_vector(7 downto 0);
atmcr_f_thr_o : std_logic_vector(22 downto 0); atmcr_f_thr_o : std_logic_vector(22 downto 0);
asor_offset_o : std_logic_vector(22 downto 0); asor_offset_o : std_logic_vector(22 downto 0);
iepd_rst_stat_o : std_logic; iepd_rst_stat_o : std_logic;
......
...@@ -3,7 +3,7 @@ ...@@ -3,7 +3,7 @@
--------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------
-- File : fd_main_wishbone_slave.vhd -- File : fd_main_wishbone_slave.vhd
-- Author : auto-generated by wbgen2 from fd_main_wishbone_slave.wb -- Author : auto-generated by wbgen2 from fd_main_wishbone_slave.wb
-- Created : Fri Dec 14 11:28:02 2012 -- Created : Fri Feb 15 12:07:16 2013
-- Standard : VHDL'87 -- Standard : VHDL'87
--------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE fd_main_wishbone_slave.wb -- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE fd_main_wishbone_slave.wb
...@@ -159,7 +159,7 @@ signal fd_main_adsfr_swb_delay : std_logic ; ...@@ -159,7 +159,7 @@ signal fd_main_adsfr_swb_delay : std_logic ;
signal fd_main_adsfr_swb_s0 : std_logic ; signal fd_main_adsfr_swb_s0 : std_logic ;
signal fd_main_adsfr_swb_s1 : std_logic ; signal fd_main_adsfr_swb_s1 : std_logic ;
signal fd_main_adsfr_swb_s2 : std_logic ; signal fd_main_adsfr_swb_s2 : std_logic ;
signal fd_main_atmcr_c_thr_int : std_logic_vector(3 downto 0); signal fd_main_atmcr_c_thr_int : std_logic_vector(7 downto 0);
signal fd_main_atmcr_c_thr_swb : std_logic ; signal fd_main_atmcr_c_thr_swb : std_logic ;
signal fd_main_atmcr_c_thr_swb_delay : std_logic ; signal fd_main_atmcr_c_thr_swb_delay : std_logic ;
signal fd_main_atmcr_c_thr_swb_s0 : std_logic ; signal fd_main_atmcr_c_thr_swb_s0 : std_logic ;
...@@ -332,7 +332,7 @@ begin ...@@ -332,7 +332,7 @@ begin
fd_main_adsfr_int <= "000000000000000000"; fd_main_adsfr_int <= "000000000000000000";
fd_main_adsfr_swb <= '0'; fd_main_adsfr_swb <= '0';
fd_main_adsfr_swb_delay <= '0'; fd_main_adsfr_swb_delay <= '0';
fd_main_atmcr_c_thr_int <= "0000"; fd_main_atmcr_c_thr_int <= "00000000";
fd_main_atmcr_c_thr_swb <= '0'; fd_main_atmcr_c_thr_swb <= '0';
fd_main_atmcr_c_thr_swb_delay <= '0'; fd_main_atmcr_c_thr_swb_delay <= '0';
fd_main_atmcr_f_thr_int <= "00000000000000000000000"; fd_main_atmcr_f_thr_int <= "00000000000000000000000";
...@@ -373,8 +373,8 @@ begin ...@@ -373,8 +373,8 @@ begin
fd_main_tsbir_timeout_int <= "0000000000"; fd_main_tsbir_timeout_int <= "0000000000";
fd_main_tsbir_threshold_int <= "000000000000"; fd_main_tsbir_threshold_int <= "000000000000";
fid_read_ack_o <= '0'; fid_read_ack_o <= '0';
fd_main_i2cr_scl_out_int <= '0'; fd_main_i2cr_scl_out_int <= '1';
fd_main_i2cr_sda_out_int <= '0'; fd_main_i2cr_sda_out_int <= '1';
fd_main_tder2_pelt_drive_int <= "00000000000000000000000000000000"; fd_main_tder2_pelt_drive_int <= "00000000000000000000000000000000";
fd_main_tsbr_advance_adv_int <= '0'; fd_main_tsbr_advance_adv_int <= '0';
eic_idr_write_int <= '0'; eic_idr_write_int <= '0';
...@@ -595,8 +595,8 @@ begin ...@@ -595,8 +595,8 @@ begin
rddata_reg(3) <= regs_i.tcr_wr_present_i; rddata_reg(3) <= regs_i.tcr_wr_present_i;
rddata_reg(4) <= regs_i.tcr_wr_ready_i; rddata_reg(4) <= regs_i.tcr_wr_ready_i;
rddata_reg(5) <= regs_i.tcr_wr_link_i; rddata_reg(5) <= regs_i.tcr_wr_link_i;
rddata_reg(6) <= 'X'; rddata_reg(6) <= '0';
rddata_reg(7) <= 'X'; rddata_reg(7) <= '0';
rddata_reg(8) <= 'X'; rddata_reg(8) <= 'X';
rddata_reg(9) <= 'X'; rddata_reg(9) <= 'X';
rddata_reg(10) <= 'X'; rddata_reg(10) <= 'X';
...@@ -736,14 +736,14 @@ begin ...@@ -736,14 +736,14 @@ begin
fd_main_tdcsr_alutrig_int <= wrdata_reg(7); fd_main_tdcsr_alutrig_int <= wrdata_reg(7);
fd_main_tdcsr_alutrig_int_delay <= wrdata_reg(7); fd_main_tdcsr_alutrig_int_delay <= wrdata_reg(7);
end if; end if;
rddata_reg(0) <= 'X'; rddata_reg(0) <= '0';
rddata_reg(1) <= 'X'; rddata_reg(1) <= '0';
rddata_reg(2) <= fd_main_tdcsr_empty_sync1; rddata_reg(2) <= fd_main_tdcsr_empty_sync1;
rddata_reg(3) <= 'X'; rddata_reg(3) <= '0';
rddata_reg(4) <= 'X'; rddata_reg(4) <= '0';
rddata_reg(5) <= 'X'; rddata_reg(5) <= '0';
rddata_reg(6) <= 'X'; rddata_reg(6) <= '0';
rddata_reg(7) <= 'X'; rddata_reg(7) <= '0';
rddata_reg(8) <= 'X'; rddata_reg(8) <= 'X';
rddata_reg(9) <= 'X'; rddata_reg(9) <= 'X';
rddata_reg(10) <= 'X'; rddata_reg(10) <= 'X';
...@@ -780,7 +780,7 @@ begin ...@@ -780,7 +780,7 @@ begin
fd_main_calr_psel_swb <= '1'; fd_main_calr_psel_swb <= '1';
fd_main_calr_psel_swb_delay <= '1'; fd_main_calr_psel_swb_delay <= '1';
end if; end if;
rddata_reg(0) <= 'X'; rddata_reg(0) <= '0';
rddata_reg(1) <= fd_main_calr_cal_pps_int; rddata_reg(1) <= fd_main_calr_cal_pps_int;
rddata_reg(2) <= fd_main_calr_cal_dmtd_int; rddata_reg(2) <= fd_main_calr_cal_dmtd_int;
rddata_reg(6 downto 3) <= fd_main_calr_psel_int; rddata_reg(6 downto 3) <= fd_main_calr_psel_int;
...@@ -852,19 +852,15 @@ begin ...@@ -852,19 +852,15 @@ begin
ack_in_progress <= '1'; ack_in_progress <= '1';
when "001101" => when "001101" =>
if (wb_we_i = '1') then if (wb_we_i = '1') then
fd_main_atmcr_c_thr_int <= wrdata_reg(3 downto 0); fd_main_atmcr_c_thr_int <= wrdata_reg(7 downto 0);
fd_main_atmcr_c_thr_swb <= '1'; fd_main_atmcr_c_thr_swb <= '1';
fd_main_atmcr_c_thr_swb_delay <= '1'; fd_main_atmcr_c_thr_swb_delay <= '1';
fd_main_atmcr_f_thr_int <= wrdata_reg(26 downto 4); fd_main_atmcr_f_thr_int <= wrdata_reg(30 downto 8);
fd_main_atmcr_f_thr_swb <= '1'; fd_main_atmcr_f_thr_swb <= '1';
fd_main_atmcr_f_thr_swb_delay <= '1'; fd_main_atmcr_f_thr_swb_delay <= '1';
end if; end if;
rddata_reg(3 downto 0) <= fd_main_atmcr_c_thr_int; rddata_reg(7 downto 0) <= fd_main_atmcr_c_thr_int;
rddata_reg(26 downto 4) <= fd_main_atmcr_f_thr_int; rddata_reg(30 downto 8) <= fd_main_atmcr_f_thr_int;
rddata_reg(27) <= 'X';
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X'; rddata_reg(31) <= 'X';
ack_sreg(3) <= '1'; ack_sreg(3) <= '1';
ack_in_progress <= '1'; ack_in_progress <= '1';
...@@ -911,7 +907,7 @@ begin ...@@ -911,7 +907,7 @@ begin
fd_main_iepd_rst_stat_int <= wrdata_reg(0); fd_main_iepd_rst_stat_int <= wrdata_reg(0);
fd_main_iepd_rst_stat_int_delay <= wrdata_reg(0); fd_main_iepd_rst_stat_int_delay <= wrdata_reg(0);
end if; end if;
rddata_reg(0) <= 'X'; rddata_reg(0) <= '0';
if (wb_we_i = '0') then if (wb_we_i = '0') then
fd_main_iepd_pdelay_lwb <= '1'; fd_main_iepd_pdelay_lwb <= '1';
fd_main_iepd_pdelay_lwb_delay <= '1'; fd_main_iepd_pdelay_lwb_delay <= '1';
...@@ -957,7 +953,7 @@ begin ...@@ -957,7 +953,7 @@ begin
rddata_reg(26) <= fd_main_scr_sel_gpio_int; rddata_reg(26) <= fd_main_scr_sel_gpio_int;
rddata_reg(27) <= regs_i.scr_ready_i; rddata_reg(27) <= regs_i.scr_ready_i;
rddata_reg(28) <= fd_main_scr_cpol_int; rddata_reg(28) <= fd_main_scr_cpol_int;
rddata_reg(29) <= 'X'; rddata_reg(29) <= '0';
rddata_reg(30) <= 'X'; rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X'; rddata_reg(31) <= 'X';
ack_sreg(2) <= '1'; ack_sreg(2) <= '1';
...@@ -985,8 +981,8 @@ begin ...@@ -985,8 +981,8 @@ begin
end if; end if;
rddata_reg(4 downto 0) <= fd_main_tsbcr_chan_mask_int; rddata_reg(4 downto 0) <= fd_main_tsbcr_chan_mask_int;
rddata_reg(5) <= fd_main_tsbcr_enable_int; rddata_reg(5) <= fd_main_tsbcr_enable_int;
rddata_reg(6) <= 'X'; rddata_reg(6) <= '0';
rddata_reg(7) <= 'X'; rddata_reg(7) <= '0';
rddata_reg(8) <= regs_i.tsbcr_full_i; rddata_reg(8) <= regs_i.tsbcr_full_i;
rddata_reg(9) <= regs_i.tsbcr_empty_i; rddata_reg(9) <= regs_i.tsbcr_empty_i;
tsbcr_read_ack_o <= '1'; tsbcr_read_ack_o <= '1';
...@@ -1139,7 +1135,7 @@ begin ...@@ -1139,7 +1135,7 @@ begin
if (wb_we_i = '1') then if (wb_we_i = '1') then
fd_main_tsbr_advance_adv_int <= wrdata_reg(0); fd_main_tsbr_advance_adv_int <= wrdata_reg(0);
end if; end if;
rddata_reg(0) <= 'X'; rddata_reg(0) <= '0';
rddata_reg(0) <= 'X'; rddata_reg(0) <= 'X';
rddata_reg(1) <= 'X'; rddata_reg(1) <= 'X';
rddata_reg(2) <= 'X'; rddata_reg(2) <= 'X';
...@@ -1376,7 +1372,7 @@ begin ...@@ -1376,7 +1372,7 @@ begin
-- PLL Locked -- PLL Locked
-- Mezzanice Present -- Mezzanine Present
-- DMTD Clock Status -- DMTD Clock Status
-- WR Timing Enable -- WR Timing Enable
regs_o.tcr_wr_enable_o <= fd_main_tcr_wr_enable_int; regs_o.tcr_wr_enable_o <= fd_main_tcr_wr_enable_int;
...@@ -1478,8 +1474,8 @@ begin ...@@ -1478,8 +1474,8 @@ begin
end process; end process;
-- Reference clock cycles -- Reference clock cycles (0...124999999)
-- asynchronous std_logic_vector register : Reference clock cycles (type RW/WO, clk_ref_i <-> clk_sys_i) -- asynchronous std_logic_vector register : Reference clock cycles (0...124999999) (type RW/WO, clk_ref_i <-> clk_sys_i)
process (clk_ref_i, rst_n_i) process (clk_ref_i, rst_n_i)
begin begin
if (rst_n_i = '0') then if (rst_n_i = '0') then
...@@ -1538,7 +1534,7 @@ begin ...@@ -1538,7 +1534,7 @@ begin
end process; end process;
-- Start TDC write -- Write to TDC
process (clk_ref_i, rst_n_i) process (clk_ref_i, rst_n_i)
begin begin
if (rst_n_i = '0') then if (rst_n_i = '0') then
...@@ -1555,7 +1551,7 @@ begin ...@@ -1555,7 +1551,7 @@ begin
end process; end process;
-- Start TDC read -- Read from TDC
process (clk_ref_i, rst_n_i) process (clk_ref_i, rst_n_i)
begin begin
if (rst_n_i = '0') then if (rst_n_i = '0') then
...@@ -1586,7 +1582,7 @@ begin ...@@ -1586,7 +1582,7 @@ begin
end process; end process;
-- Start enable -- Stop enable
process (clk_ref_i, rst_n_i) process (clk_ref_i, rst_n_i)
begin begin
if (rst_n_i = '0') then if (rst_n_i = '0') then
...@@ -1620,7 +1616,7 @@ begin ...@@ -1620,7 +1616,7 @@ begin
end process; end process;
-- Stop enable -- Start enable
process (clk_ref_i, rst_n_i) process (clk_ref_i, rst_n_i)
begin begin
if (rst_n_i = '0') then if (rst_n_i = '0') then
...@@ -1654,7 +1650,7 @@ begin ...@@ -1654,7 +1650,7 @@ begin
end process; end process;
-- write 1: Pulse the Alutrigger line -- Pulse <code>Alutrigger</code> line
process (clk_ref_i, rst_n_i) process (clk_ref_i, rst_n_i)
begin begin
if (rst_n_i = '0') then if (rst_n_i = '0') then
...@@ -1671,7 +1667,7 @@ begin ...@@ -1671,7 +1667,7 @@ begin
end process; end process;
-- Triggers calibration pulses -- Generate calibration pulses (type 1 calibration)
process (clk_ref_i, rst_n_i) process (clk_ref_i, rst_n_i)
begin begin
if (rst_n_i = '0') then if (rst_n_i = '0') then
...@@ -1704,10 +1700,10 @@ begin ...@@ -1704,10 +1700,10 @@ begin
end process; end process;
-- Produce DDMTD calibration pattern -- Produce DDMTD calibration pattern (type 2 calibration)
regs_o.calr_cal_dmtd_o <= fd_main_calr_cal_dmtd_int; regs_o.calr_cal_dmtd_o <= fd_main_calr_cal_dmtd_int;
-- Enable pulse generation -- Calibration pulse output select/mask
-- asynchronous std_logic_vector register : Enable pulse generation (type RW/RO, clk_ref_i <-> clk_sys_i) -- asynchronous std_logic_vector register : Calibration pulse output select/mask (type RW/RO, clk_ref_i <-> clk_sys_i)
process (clk_ref_i, rst_n_i) process (clk_ref_i, rst_n_i)
begin begin
if (rst_n_i = '0') then if (rst_n_i = '0') then
...@@ -1758,7 +1754,7 @@ begin ...@@ -1758,7 +1754,7 @@ begin
fd_main_atmcr_c_thr_swb_s0 <= '0'; fd_main_atmcr_c_thr_swb_s0 <= '0';
fd_main_atmcr_c_thr_swb_s1 <= '0'; fd_main_atmcr_c_thr_swb_s1 <= '0';
fd_main_atmcr_c_thr_swb_s2 <= '0'; fd_main_atmcr_c_thr_swb_s2 <= '0';
regs_o.atmcr_c_thr_o <= "0000"; regs_o.atmcr_c_thr_o <= "00000000";
elsif rising_edge(clk_ref_i) then elsif rising_edge(clk_ref_i) then
fd_main_atmcr_c_thr_swb_s0 <= fd_main_atmcr_c_thr_swb; fd_main_atmcr_c_thr_swb_s0 <= fd_main_atmcr_c_thr_swb;
fd_main_atmcr_c_thr_swb_s1 <= fd_main_atmcr_c_thr_swb_s0; fd_main_atmcr_c_thr_swb_s1 <= fd_main_atmcr_c_thr_swb_s0;
......
...@@ -515,7 +515,7 @@ peripheral { ...@@ -515,7 +515,7 @@ peripheral {
field { field {
name = "Wraparound Coarse Threshold"; name = "Wraparound Coarse Threshold";
prefix = "C_THR"; prefix = "C_THR";
size = 4; size = 8;
type = SLV; type = SLV;
clock = "clk_ref_i"; clock = "clk_ref_i";
access_bus = READ_WRITE; access_bus = READ_WRITE;
......
...@@ -6,7 +6,7 @@ ...@@ -6,7 +6,7 @@
-- Author : Tomasz Wlostowski -- Author : Tomasz Wlostowski
-- Company : CERN -- Company : CERN
-- Created : 2011-08-24 -- Created : 2011-08-24
-- Last update: 2012-11-22 -- Last update: 2013-04-30
-- Platform : FPGA-generic -- Platform : FPGA-generic
-- Standard : VHDL'93 -- Standard : VHDL'93
------------------------------------------------------------------------------- -------------------------------------------------------------------------------
...@@ -76,7 +76,7 @@ package fine_delay_pkg is ...@@ -76,7 +76,7 @@ package fine_delay_pkg is
constant c_FD_DMTD_CALIBRATION_PERIOD : integer := 144; constant c_FD_DMTD_CALIBRATION_PERIOD : integer := 144;
-- Calibration pulse width -- Calibration pulse width
constant c_FD_DMTD_CALIBRATION_PWIDTH : integer := 10; constant c_FD_DMTD_CALIBRATION_PWIDTH : integer := 32;
constant c_FD_SDB_DEVICE : t_sdb_device := ( constant c_FD_SDB_DEVICE : t_sdb_device := (
abi_class => x"0000", -- undocumented device abi_class => x"0000", -- undocumented device
...@@ -90,7 +90,7 @@ package fine_delay_pkg is ...@@ -90,7 +90,7 @@ package fine_delay_pkg is
product => ( product => (
vendor_id => x"000000000000CE42", -- CERN vendor_id => x"000000000000CE42", -- CERN
device_id => x"f19ede1a", device_id => x"f19ede1a",
version => x"00000001", version => x"00000003",
date => x"20120809", date => x"20120809",
name => "Fine-Delay-Core "))); name => "Fine-Delay-Core ")));
......
...@@ -9,5 +9,5 @@ syn_package = "fgg900" ...@@ -9,5 +9,5 @@ syn_package = "fgg900"
syn_top = "svec_top" syn_top = "svec_top"
syn_project = "svec_fine_delay.xise" syn_project = "svec_fine_delay.xise"
files = [ "wrc.ram" ] files = [ "wrc-release.ram" ]
modules = { "local" : [ "../../../top/svec/wr", "../../../platform" ] } modules = { "local" : [ "../../../top/svec/wr", "../../../platform" ] }
This source diff could not be displayed because it is too large. You can view the blob instead.
...@@ -197,21 +197,28 @@ module fdelay_board ( ...@@ -197,21 +197,28 @@ module fdelay_board (
); );
genvar gg; genvar gg;
function bit[9:0] reverse_bits (bit [9:0] x);
reg [9:0] tmp;
int i;
for(i=0;i<10;i++)
tmp[9-i]=x[i];
return tmp;
endfunction // reverse_bits
generate
for(gg=0;gg<4;gg++)
begin
// assign out_o[gg] = fmc.delay_pulse[gg];
mc100ep195 mc100ep195
U_delay_line( U_delay_line0(
.len(fmc.delay_len[gg]), .len(fmc.delay_len[0]),
.i(fmc.delay_pulse[gg]), .i(fmc.delay_pulse[0]),
.delay(fmc.delay_val), .delay(reverse_bits(fmc.delay_val)),
.o(out_o[gg]) .o(out_o[0]));
);
end
endgenerate
endmodule // main endmodule // main
......
...@@ -3,7 +3,6 @@ ...@@ -3,7 +3,6 @@
`include "fdelay_board.svh" `include "fdelay_board.svh"
`include "simdrv_fine_delay.svh" `include "simdrv_fine_delay.svh"
`include "ideal_timestamper.svh"
module delay_meas(input enable, input a, input b); module delay_meas(input enable, input a, input b);
...@@ -26,7 +25,6 @@ module delay_meas(input enable, input a, input b); ...@@ -26,7 +25,6 @@ module delay_meas(input enable, input a, input b);
end end
initial forever begin initial forever begin
wait(tag_a.num() > 0 && tag_b.num() > 0); wait(tag_a.num() > 0 && tag_b.num() > 0);
...@@ -45,6 +43,43 @@ module delay_meas(input enable, input a, input b); ...@@ -45,6 +43,43 @@ module delay_meas(input enable, input a, input b);
end end
endmodule // delay_meas endmodule // delay_meas
module period_meas(input enable, input a);
mailbox tag_a, tag_b;
event q_notempty;
initial begin
tag_a = new(1024);
end
time prev_a = 0;
always@(posedge a) begin
if(prev_a > 0)begin
if(enable) tag_a.put($time - prev_a);
end else
prev_a=$time;
end
initial forever begin
wait(tag_a.num() > 0);
while(tag_a.num() > 0)
begin
time delta;
tag_a.get(delta);
$display("Delay: %.3f ns", real'(delta) / real'(1ns) );
end
end
endmodule // delay_meas
module main; module main;
...@@ -87,14 +122,11 @@ module main; ...@@ -87,14 +122,11 @@ module main;
wire [3:0] out0, out1; wire [3:0] out0, out1;
reg pulse_enable = 0; reg pulse_enable = 0;
random_pulse_gen random_pulse_gen
#( #(
.g_pulse_width (100ns), .g_pulse_width (50ns),
.g_min_spacing (1001ns), .g_min_spacing (1001ns),
.g_max_spacing (1001.1ns), .g_max_spacing (1001.1ns))
.g_repetition(1),
.g_burst_spacing(3ns))
U_Gen0 U_Gen0
( (
.enable_i(pulse_enable), .enable_i(pulse_enable),
...@@ -108,15 +140,12 @@ module main; ...@@ -108,15 +140,12 @@ module main;
.fmc(I_fmc0.board) .fmc(I_fmc0.board)
); );
delay_meas U_DMeas0 (pulse_enable, trig0, out0[0]); reg out0_delayed=0;
ideal_timestamper tsu_in( always@(out0[0]) out0_delayed <= #10ps out0[0];
.clk_ref_i(I_fmc0.clk_ref_p),
.rst_n_i(rst_n),
.enable_i(1'b1),
.trig_a_i(trig0),
.csync_p1_i(1'b0));
period_meas U_DMeas0 (pulse_enable, out0[0]);
task automatic init_vme64x_core(ref CBusAccessor_VME64x acc); task automatic init_vme64x_core(ref CBusAccessor_VME64x acc);
/* map func0 to 0x80000000, A32 */ /* map func0 to 0x80000000, A32 */
...@@ -132,7 +161,7 @@ module main; ...@@ -132,7 +161,7 @@ module main;
initial begin initial begin
CBusAccessor_VME64x acc = new(VME.master); CBusAccessor_VME64x acc = new(VME.master);
CBusAccessor acc_casted = CBusAccessor'(acc); CBusAccessor acc_casted = CBusAccessor'(acc);
Timestamp dly; Timestamp dly, t_start;
CSimDrv_FineDelay drv0; CSimDrv_FineDelay drv0;
uint64_t d; uint64_t d;
...@@ -141,70 +170,52 @@ module main; ...@@ -141,70 +170,52 @@ module main;
init_vme64x_core(acc); init_vme64x_core(acc);
acc_casted.set_default_xfer_size(A32|SINGLE|D32); acc_casted.set_default_xfer_size(A32|SINGLE|D32);
// acc.read('h20000, d, D32|A32|SINGLE);
// $display("Vector 1 = %x", d);
acc.read('h80030080, d, D32|A32|SINGLE);
$display("Vector 0 = %x", d);
acc.read('h80030084, d, D32|A32|SINGLE);
$display("Vector 1 = %x", d);
acc.read('h80030088, d, D32|A32|SINGLE);
$display("Vector 2 = %x", d);
$stop;
drv0 = new(acc, 'h10000);
drv0 = new(acc, 'h80010000);
drv0.init(); drv0.init();
dly=new; t_start=new;
dly.from_ps(800000); drv0.get_time(t_start);
drv0.config_output(0, CSimDrv_FineDelay::DELAY, 1, dly, 250000); t_start.coarse += 2000;
drv0.config_output(0, CSimDrv_FineDelay::PULSE_GEN, 1, t_start, 200000, 1001000, -1);
$display("Init done"); $display("Init done");
pulse_enable = 1; pulse_enable = 1;
/* -----\/----- EXCLUDED -----\/-----
forever begin forever begin
// drv0.rbuf_update(); drv0.rbuf_update();
// if(drv0.poll())
Timestamp ts, ts_ref;
// ts = drv0.get();
while(ts_q_fd0.size() == 0) if(drv0.poll())
#1ns;
ts = ts_q_fd0.pop_front();
$display("TS: %.3f", ts.flatten());
while(tsu_in.poll())
begin begin
ts_ref = tsu_in.get(); Timestamp ts;
ts = drv0.get();
// $display("TS: %.3f", ts.flatten());
end end
#1us;
$display("TS: %.3f, ref: %.3f, delta: %.3f", ts.flatten(), ts_ref.flatten(), ts_ref.flatten() - ts.flatten());
end end
-----/\----- EXCLUDED -----/\----- */
end // initial begin end // initial begin
Timestamp ts_q_fd0[$];
always@(posedge DUT.dcm0_clk_ref_0)
begin
if(DUT.U_FineDelay_Core0.tag_valid)
begin
Timestamp tr;
tr = new;
$display("Got a tag");
tr.coarse = DUT.U_FineDelay_Core0.tag_coarse;
tr.utc = 0;
tr.frac = DUT.U_FineDelay_Core0.tag_frac;
ts_q_fd0.push_back(tr);
end
end
endmodule // main endmodule // main
...@@ -177,7 +177,7 @@ class CSimDrv_FineDelay; ...@@ -177,7 +177,7 @@ class CSimDrv_FineDelay;
base = 'h100 + 'h100 * channel; base = 'h100 + 'h100 * channel;
writel(base + `ADDR_FD_FRR, 800); writel(base + `ADDR_FD_FRR, 865);
writel(base + `ADDR_FD_U_STARTH, t_start.utc >> 32); writel(base + `ADDR_FD_U_STARTH, t_start.utc >> 32);
writel(base + `ADDR_FD_U_STARTL, t_start.utc & 'hffffffff); writel(base + `ADDR_FD_U_STARTL, t_start.utc & 'hffffffff);
writel(base + `ADDR_FD_C_START, t_start.coarse); writel(base + `ADDR_FD_C_START, t_start.coarse);
......
onerror {resume} onerror {resume}
quietly WaveActivateNextPane {} 0 quietly WaveActivateNextPane {} 0
add wave -noupdate /main/DUT/g_with_wr_phy
add wave -noupdate /main/DUT/g_simulation
add wave -noupdate /main/DUT/clk_20m_vcxo_i
add wave -noupdate /main/DUT/clk_125m_pllref_p_i
add wave -noupdate /main/DUT/clk_125m_pllref_n_i
add wave -noupdate /main/DUT/clk_125m_gtp_p_i
add wave -noupdate /main/DUT/clk_125m_gtp_n_i
add wave -noupdate /main/DUT/rst_n_i
add wave -noupdate /main/DUT/VME_AS_n_i
add wave -noupdate /main/DUT/VME_RST_n_i
add wave -noupdate /main/DUT/VME_WRITE_n_i
add wave -noupdate /main/DUT/VME_AM_i
add wave -noupdate /main/DUT/VME_DS_n_i
add wave -noupdate /main/DUT/VME_GA_i
add wave -noupdate /main/DUT/VME_BERR_o
add wave -noupdate /main/DUT/VME_DTACK_n_o
add wave -noupdate /main/DUT/VME_RETRY_n_o
add wave -noupdate /main/DUT/VME_RETRY_OE_o
add wave -noupdate /main/DUT/VME_LWORD_n_b
add wave -noupdate /main/DUT/VME_ADDR_b
add wave -noupdate /main/DUT/VME_DATA_b
add wave -noupdate /main/DUT/VME_BBSY_n_i
add wave -noupdate /main/DUT/VME_IRQ_n_o
add wave -noupdate /main/DUT/VME_IACK_n_i
add wave -noupdate /main/DUT/VME_IACKIN_n_i
add wave -noupdate /main/DUT/VME_IACKOUT_n_o
add wave -noupdate /main/DUT/VME_DTACK_OE_o
add wave -noupdate /main/DUT/VME_DATA_DIR_o
add wave -noupdate /main/DUT/VME_DATA_OE_N_o
add wave -noupdate /main/DUT/VME_ADDR_DIR_o
add wave -noupdate /main/DUT/VME_ADDR_OE_N_o
add wave -noupdate /main/DUT/sfp_txp_o
add wave -noupdate /main/DUT/sfp_txn_o
add wave -noupdate /main/DUT/sfp_rxp_i
add wave -noupdate /main/DUT/sfp_rxn_i
add wave -noupdate /main/DUT/sfp_mod_def0_b
add wave -noupdate /main/DUT/sfp_mod_def1_b
add wave -noupdate /main/DUT/sfp_mod_def2_b
add wave -noupdate /main/DUT/sfp_rate_select_b
add wave -noupdate /main/DUT/sfp_tx_fault_i
add wave -noupdate /main/DUT/sfp_tx_disable_o
add wave -noupdate /main/DUT/sfp_los_i
add wave -noupdate /main/DUT/fmc0_prsntm2c_n_i
add wave -noupdate /main/DUT/fmc1_prsntm2c_n_i
add wave -noupdate /main/DUT/fmc0_scl_b
add wave -noupdate /main/DUT/fmc0_sda_b
add wave -noupdate /main/DUT/fmc1_scl_b
add wave -noupdate /main/DUT/fmc1_sda_b
add wave -noupdate /main/DUT/pll20dac_din_o
add wave -noupdate /main/DUT/pll20dac_sclk_o
add wave -noupdate /main/DUT/pll20dac_sync_n_o
add wave -noupdate /main/DUT/pll25dac_din_o
add wave -noupdate /main/DUT/pll25dac_sclk_o
add wave -noupdate /main/DUT/pll25dac_sync_n_o
add wave -noupdate /main/DUT/tempid_dq_b
add wave -noupdate /main/DUT/fp_ledn_o
add wave -noupdate /main/DUT/fd0_tdc_start_p_i
add wave -noupdate /main/DUT/fd0_tdc_start_n_i
add wave -noupdate /main/DUT/fd0_clk_ref_p_i
add wave -noupdate /main/DUT/fd0_clk_ref_n_i
add wave -noupdate /main/DUT/fd0_trig_a_i
add wave -noupdate /main/DUT/fd0_tdc_cal_pulse_o
add wave -noupdate /main/DUT/fd0_tdc_d_b
add wave -noupdate /main/DUT/fd0_tdc_emptyf_i
add wave -noupdate /main/DUT/fd0_tdc_alutrigger_o
add wave -noupdate /main/DUT/fd0_tdc_wr_n_o
add wave -noupdate /main/DUT/fd0_tdc_rd_n_o
add wave -noupdate /main/DUT/fd0_tdc_oe_n_o
add wave -noupdate /main/DUT/fd0_led_trig_o
add wave -noupdate /main/DUT/fd0_tdc_start_dis_o
add wave -noupdate /main/DUT/fd0_tdc_stop_dis_o
add wave -noupdate /main/DUT/fd0_spi_cs_dac_n_o
add wave -noupdate /main/DUT/fd0_spi_cs_pll_n_o
add wave -noupdate /main/DUT/fd0_spi_cs_gpio_n_o
add wave -noupdate /main/DUT/fd0_spi_sclk_o
add wave -noupdate /main/DUT/fd0_spi_mosi_o
add wave -noupdate /main/DUT/fd0_spi_miso_i
add wave -noupdate /main/DUT/fd0_delay_len_o
add wave -noupdate /main/DUT/fd0_delay_val_o
add wave -noupdate /main/DUT/fd0_delay_pulse_o
add wave -noupdate /main/DUT/fd0_dmtd_clk_o
add wave -noupdate /main/DUT/fd0_dmtd_fb_in_i
add wave -noupdate /main/DUT/fd0_dmtd_fb_out_i
add wave -noupdate /main/DUT/fd0_pll_status_i
add wave -noupdate /main/DUT/fd0_ext_rst_n_o
add wave -noupdate /main/DUT/fd0_onewire_b
add wave -noupdate /main/DUT/fd1_tdc_start_p_i
add wave -noupdate /main/DUT/fd1_tdc_start_n_i
add wave -noupdate /main/DUT/fd1_clk_ref_p_i
add wave -noupdate /main/DUT/fd1_clk_ref_n_i
add wave -noupdate /main/DUT/fd1_trig_a_i
add wave -noupdate /main/DUT/fd1_tdc_cal_pulse_o
add wave -noupdate /main/DUT/fd1_tdc_d_b
add wave -noupdate /main/DUT/fd1_tdc_emptyf_i
add wave -noupdate /main/DUT/fd1_tdc_alutrigger_o
add wave -noupdate /main/DUT/fd1_tdc_wr_n_o
add wave -noupdate /main/DUT/fd1_tdc_rd_n_o
add wave -noupdate /main/DUT/fd1_tdc_oe_n_o
add wave -noupdate /main/DUT/fd1_led_trig_o
add wave -noupdate /main/DUT/fd1_tdc_start_dis_o
add wave -noupdate /main/DUT/fd1_tdc_stop_dis_o
add wave -noupdate /main/DUT/fd1_spi_cs_dac_n_o
add wave -noupdate /main/DUT/fd1_spi_cs_pll_n_o
add wave -noupdate /main/DUT/fd1_spi_cs_gpio_n_o
add wave -noupdate /main/DUT/fd1_spi_sclk_o
add wave -noupdate /main/DUT/fd1_spi_mosi_o
add wave -noupdate /main/DUT/fd1_spi_miso_i
add wave -noupdate /main/DUT/fd1_delay_len_o
add wave -noupdate /main/DUT/fd1_delay_val_o
add wave -noupdate /main/DUT/fd1_delay_pulse_o
add wave -noupdate /main/DUT/fd1_dmtd_clk_o
add wave -noupdate /main/DUT/fd1_dmtd_fb_in_i
add wave -noupdate /main/DUT/fd1_dmtd_fb_out_i
add wave -noupdate /main/DUT/fd1_pll_status_i
add wave -noupdate /main/DUT/fd1_ext_rst_n_o
add wave -noupdate /main/DUT/fd1_onewire_b
add wave -noupdate /main/DUT/uart_rxd_i
add wave -noupdate /main/DUT/uart_txd_o
add wave -noupdate /main/DUT/VME_DATA_b_out
add wave -noupdate /main/DUT/VME_ADDR_b_out
add wave -noupdate /main/DUT/VME_LWORD_n_b_out
add wave -noupdate /main/DUT/VME_DATA_DIR_int
add wave -noupdate /main/DUT/VME_ADDR_DIR_int
add wave -noupdate /main/DUT/dac_hpll_load_p1
add wave -noupdate /main/DUT/dac_dpll_load_p1
add wave -noupdate /main/DUT/dac_hpll_data
add wave -noupdate /main/DUT/dac_dpll_data
add wave -noupdate /main/DUT/phy_tx_data
add wave -noupdate /main/DUT/phy_tx_k
add wave -noupdate /main/DUT/phy_tx_disparity
add wave -noupdate /main/DUT/phy_tx_enc_err
add wave -noupdate /main/DUT/phy_rx_data
add wave -noupdate /main/DUT/phy_rx_rbclk
add wave -noupdate /main/DUT/phy_rx_k
add wave -noupdate /main/DUT/phy_rx_enc_err
add wave -noupdate /main/DUT/phy_rx_bitslide
add wave -noupdate /main/DUT/phy_rst
add wave -noupdate /main/DUT/phy_loopen
add wave -noupdate /main/DUT/cnx_master_out add wave -noupdate /main/DUT/cnx_master_out
add wave -noupdate /main/DUT/cnx_master_in add wave -noupdate /main/DUT/cnx_master_in
add wave -noupdate /main/DUT/cnx_slave_out add wave -noupdate /main/DUT/cnx_slave_out
add wave -noupdate /main/DUT/cnx_slave_in add wave -noupdate /main/DUT/cnx_slave_in
add wave -noupdate /main/DUT/dcm0_clk_ref_0
add wave -noupdate /main/DUT/dcm0_clk_ref_180
add wave -noupdate /main/DUT/fd0_tdc_start
add wave -noupdate /main/DUT/tdc0_data_out
add wave -noupdate /main/DUT/tdc0_data_in
add wave -noupdate /main/DUT/tdc0_data_oe
add wave -noupdate /main/DUT/dcm1_clk_ref_0
add wave -noupdate /main/DUT/dcm1_clk_ref_180
add wave -noupdate /main/DUT/fd1_tdc_start
add wave -noupdate /main/DUT/tdc1_data_out
add wave -noupdate /main/DUT/tdc1_data_in
add wave -noupdate /main/DUT/tdc1_data_oe
add wave -noupdate /main/DUT/tm_link_up
add wave -noupdate /main/DUT/tm_utc
add wave -noupdate /main/DUT/tm_cycles
add wave -noupdate /main/DUT/tm_time_valid
add wave -noupdate /main/DUT/tm0_clk_aux_lock_en
add wave -noupdate /main/DUT/tm0_clk_aux_locked
add wave -noupdate /main/DUT/tm1_clk_aux_lock_en
add wave -noupdate /main/DUT/tm1_clk_aux_locked
add wave -noupdate /main/DUT/tm_dac_value
add wave -noupdate /main/DUT/tm0_dac_wr
add wave -noupdate /main/DUT/tm1_dac_wr
add wave -noupdate /main/DUT/ddr0_pll_reset
add wave -noupdate /main/DUT/ddr0_pll_locked
add wave -noupdate /main/DUT/fd0_pll_status
add wave -noupdate /main/DUT/ddr1_pll_reset
add wave -noupdate /main/DUT/ddr1_pll_locked
add wave -noupdate /main/DUT/fd1_pll_status
add wave -noupdate /main/DUT/wrc_scl_out
add wave -noupdate /main/DUT/wrc_scl_in
add wave -noupdate /main/DUT/wrc_sda_out
add wave -noupdate /main/DUT/wrc_sda_in
add wave -noupdate /main/DUT/fd0_scl_out
add wave -noupdate /main/DUT/fd0_scl_in
add wave -noupdate /main/DUT/fd0_sda_out
add wave -noupdate /main/DUT/fd0_sda_in
add wave -noupdate /main/DUT/fd1_scl_out
add wave -noupdate /main/DUT/fd1_scl_in
add wave -noupdate /main/DUT/fd1_sda_out
add wave -noupdate /main/DUT/fd1_sda_in
add wave -noupdate /main/DUT/sfp_scl_out
add wave -noupdate /main/DUT/sfp_scl_in
add wave -noupdate /main/DUT/sfp_sda_out
add wave -noupdate /main/DUT/sfp_sda_in
add wave -noupdate /main/DUT/wrc_owr_en
add wave -noupdate /main/DUT/wrc_owr_in
add wave -noupdate /main/DUT/fd0_owr_en
add wave -noupdate /main/DUT/fd0_owr_in
add wave -noupdate /main/DUT/fd1_owr_en
add wave -noupdate /main/DUT/fd1_owr_in
add wave -noupdate /main/DUT/fd0_irq
add wave -noupdate /main/DUT/fd1_irq
add wave -noupdate /main/DUT/pllout_clk_sys
add wave -noupdate /main/DUT/pllout_clk_dmtd
add wave -noupdate /main/DUT/pllout_clk_fb_pllref
add wave -noupdate /main/DUT/pllout_clk_fb_dmtd
add wave -noupdate /main/DUT/clk_20m_vcxo_buf
add wave -noupdate /main/DUT/clk_125m_pllref
add wave -noupdate /main/DUT/clk_125m_gtp
add wave -noupdate /main/DUT/clk_sys
add wave -noupdate /main/DUT/clk_dmtd
add wave -noupdate /main/DUT/local_reset_n
add wave -noupdate /main/DUT/vme_master_out
add wave -noupdate /main/DUT/vme_master_in
add wave -noupdate /main/DUT/pins
add wave -noupdate /main/DUT/rst_n_a
add wave -noupdate /main/DUT/pps
add wave -noupdate /main/DUT/led_divider
add wave -noupdate /main/DUT/leds
add wave -noupdate /main/DUT/etherbone_rst_n
add wave -noupdate /main/DUT/etherbone_src_out
add wave -noupdate /main/DUT/etherbone_src_in
add wave -noupdate /main/DUT/etherbone_snk_out
add wave -noupdate /main/DUT/etherbone_snk_in
add wave -noupdate /main/DUT/etherbone_cfg_in
add wave -noupdate /main/DUT/etherbone_cfg_out
TreeUpdate [SetDefaultTree] TreeUpdate [SetDefaultTree]
WaveRestoreCursors {{Cursor 1} {23693000000 fs} 0} WaveRestoreCursors {{Cursor 1} {53004000000 fs} 0}
configure wave -namecolwidth 183 configure wave -namecolwidth 183
configure wave -valuecolwidth 100 configure wave -valuecolwidth 100
configure wave -justifyvalue left configure wave -justifyvalue left
...@@ -235,4 +20,4 @@ configure wave -griddelta 40 ...@@ -235,4 +20,4 @@ configure wave -griddelta 40
configure wave -timeline 0 configure wave -timeline 0
configure wave -timelineunits ns configure wave -timelineunits ns
update update
WaveRestoreZoom {2400011620 fs} {12618218340 fs} WaveRestoreZoom {0 fs} {226247193600 fs}
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files = ["spec_top.vhd", "spec_top.ucf", "spec_serial_dac.vhd", "spec_serial_dac_arb.vhd", "spec_reset_gen.vhd"] files = ["synthesis_descriptor.vhd", "spec_top.vhd", "spec_top.ucf", "spec_serial_dac.vhd", "spec_serial_dac_arb.vhd", "spec_reset_gen.vhd"]
fetchto = "../../../ip_cores" fetchto = "../../../ip_cores"
......
...@@ -171,6 +171,15 @@ NET "fmc_scl_b" IOSTANDARD =LVCMOS25; ...@@ -171,6 +171,15 @@ NET "fmc_scl_b" IOSTANDARD =LVCMOS25;
NET "fmc_sda_b" LOC = F8 ; NET "fmc_sda_b" LOC = F8 ;
NET "fmc_sda_b" IOSTANDARD =LVCMOS25; NET "fmc_sda_b" IOSTANDARD =LVCMOS25;
#net "led_n_o[0]" loc=c20;
#net "led_n_o[0]" IOSTANDARD=LVCMOS18;
#net "led_n_o[1]" loc=F18;
#net "led_n_o[1]" IOSTANDARD=LVCMOS18;
#net "led_n_o[2]" loc=f20;
#net "led_n_o[2]" IOSTANDARD=LVCMOS18;
#net "led_n_o[3]" loc=G19;
#net "led_n_o[3]" IOSTANDARD=LVCMOS18;
NET "carrier_onewire_b" LOC = D4; NET "carrier_onewire_b" LOC = D4;
NET "carrier_onewire_b" IOSTANDARD = "LVCMOS25"; NET "carrier_onewire_b" IOSTANDARD = "LVCMOS25";
......
...@@ -6,7 +6,7 @@ ...@@ -6,7 +6,7 @@
-- Author : Tomasz Wlostowski -- Author : Tomasz Wlostowski
-- Company : CERN -- Company : CERN
-- Created : 2011-08-24 -- Created : 2011-08-24
-- Last update: 2013-02-22 -- Last update: 2013-04-17
-- Platform : FPGA-generic -- Platform : FPGA-generic
-- Standard : VHDL'93 -- Standard : VHDL'93
------------------------------------------------------------------------------- -------------------------------------------------------------------------------
...@@ -50,6 +50,8 @@ use work.fine_delay_pkg.all; ...@@ -50,6 +50,8 @@ use work.fine_delay_pkg.all;
use work.etherbone_pkg.all; use work.etherbone_pkg.all;
use work.wr_xilinx_pkg.all; use work.wr_xilinx_pkg.all;
use work.synthesis_descriptor.all;
library UNISIM; library UNISIM;
use UNISIM.vcomponents.all; use UNISIM.vcomponents.all;
...@@ -264,35 +266,26 @@ architecture rtl of spec_top is ...@@ -264,35 +266,26 @@ architecture rtl of spec_top is
constant c_MASTER_GENNUM : integer := 0; constant c_MASTER_GENNUM : integer := 0;
constant c_MASTER_ETHERBONE : integer := 1; constant c_MASTER_ETHERBONE : integer := 1;
constant c_SLAVE_FD : integer := 0; constant c_SLAVE_FD : integer := 0;
constant c_SLAVE_WRCORE : integer := 1; constant c_SLAVE_WRCORE : integer := 1;
constant c_SLAVE_VIC : integer := 2; constant c_SLAVE_VIC : integer := 2;
constant c_DESC_SYNTHESIS : integer := 3;
constant c_DESC_REPO_URL : integer := 4;
constant c_WRCORE_BRIDGE_SDB : t_sdb_bridge := f_xwb_bridge_manual_sdb(x"0003ffff", x"00030000"); constant c_WRCORE_BRIDGE_SDB : t_sdb_bridge := f_xwb_bridge_manual_sdb(x"0003ffff", x"00030000");
constant c_xwb_vic_sdb : t_sdb_device := ( constant c_INTERCONNECT_LAYOUT : t_sdb_record_array(c_NUM_WB_MASTERS+1 downto 0) :=
abi_class => x"0000", -- undocumented device (c_SLAVE_WRCORE => f_sdb_embed_bridge(c_WRCORE_BRIDGE_SDB, x"000c0000"),
abi_ver_major => x"01", c_SLAVE_FD => f_sdb_embed_device(c_FD_SDB_DEVICE, x"00080000"),
abi_ver_minor => x"01", c_SLAVE_VIC => f_sdb_embed_device(c_xwb_vic_sdb, x"00090000"),
wbd_endian => c_sdb_endian_big, c_DESC_SYNTHESIS => f_sdb_embed_synthesis(c_sdb_synthesis_info),
wbd_width => x"7", -- 8/16/32-bit port granularity c_DESC_REPO_URL => f_sdb_embed_repo_url(c_sdb_repo_url));
sdb_component => (
addr_first => x"0000000000000000",
addr_last => x"00000000000000ff",
product => (
vendor_id => x"000000000000CE42", -- CERN
device_id => x"00000013",
version => x"00000001",
date => x"20120113",
name => "WB-VIC-Int.Control ")));
constant c_INTERCONNECT_LAYOUT : t_sdb_record_array(c_NUM_WB_MASTERS-1 downto 0) :=
(c_SLAVE_WRCORE => f_sdb_embed_bridge(c_WRCORE_BRIDGE_SDB, x"000c0000"),
c_SLAVE_FD => f_sdb_embed_device(c_FD_SDB_DEVICE, x"00080000"),
c_SLAVE_VIC => f_sdb_embed_device(c_xwb_vic_sdb, x"00090000"));
constant c_SDB_ADDRESS : t_wishbone_address := x"00000000"; constant c_SDB_ADDRESS : t_wishbone_address := x"00000000";
constant c_VIC_VECTOR_TABLE : t_wishbone_address_array(0 to 0) :=
(0 => x"00080000");
signal pllout_clk_sys : std_logic; signal pllout_clk_sys : std_logic;
signal pllout_clk_dmtd : std_logic; signal pllout_clk_dmtd : std_logic;
signal pllout_clk_fb_pllref : std_logic; signal pllout_clk_fb_pllref : std_logic;
...@@ -567,7 +560,7 @@ begin ...@@ -567,7 +560,7 @@ begin
------------------------------------------------------------------------------- -------------------------------------------------------------------------------
-- Top level interconnect and interrupt controller -- Top level interconnect and interrupt controller
------------------------------------------------------------------------------- -------------------------------------------------------------------------------
U_Intercon : xwb_sdb_crossbar U_Intercon : xwb_sdb_crossbar
generic map ( generic map (
g_num_masters => c_NUM_WB_SLAVES, g_num_masters => c_NUM_WB_SLAVES,
...@@ -588,7 +581,8 @@ begin ...@@ -588,7 +581,8 @@ begin
generic map ( generic map (
g_interface_mode => PIPELINED, g_interface_mode => PIPELINED,
g_address_granularity => BYTE, g_address_granularity => BYTE,
g_num_interrupts => 1) g_num_interrupts => 1,
g_init_vectors => c_VIC_VECTOR_TABLE)
port map ( port map (
clk_sys_i => clk_sys, clk_sys_i => clk_sys,
rst_n_i => local_reset_n, rst_n_i => local_reset_n,
...@@ -626,10 +620,11 @@ begin ...@@ -626,10 +620,11 @@ begin
g_with_external_clock_input => false, g_with_external_clock_input => false,
g_aux_clks => 1, g_aux_clks => 1,
g_ep_rxbuf_size => 1024, g_ep_rxbuf_size => 1024,
g_dpram_initf => "wrc.ram", g_dpram_initf => "none",
g_dpram_size => 90112/4, g_dpram_size => 90112/4,
g_interface_mode => PIPELINED, g_interface_mode => PIPELINED,
g_address_granularity => BYTE) g_address_granularity => BYTE,
g_softpll_enable_debugger => false)
port map ( port map (
clk_sys_i => clk_sys, clk_sys_i => clk_sys,
clk_dmtd_i => clk_dmtd, clk_dmtd_i => clk_dmtd,
...@@ -655,7 +650,7 @@ begin ...@@ -655,7 +650,7 @@ begin
phy_rst_o => phy_rst, phy_rst_o => phy_rst,
phy_loopen_o => phy_loopen, phy_loopen_o => phy_loopen,
led_act_o => LED_RED, led_act_o => LED_RED,
led_link_o => LED_GREEN, led_link_o => LED_GREEN,
scl_o => wrc_scl_out, scl_o => wrc_scl_out,
...@@ -687,9 +682,9 @@ begin ...@@ -687,9 +682,9 @@ begin
tm_link_up_o => tm_link_up, tm_link_up_o => tm_link_up,
tm_dac_value_o => tm_dac_value, tm_dac_value_o => tm_dac_value,
tm_dac_wr_o => tm_dac_wr, tm_dac_wr_o(0) => tm_dac_wr,
tm_clk_aux_lock_en_i => tm_clk_aux_lock_en, tm_clk_aux_lock_en_i(0) => tm_clk_aux_lock_en,
tm_clk_aux_locked_o => tm_clk_aux_locked, tm_clk_aux_locked_o(0) => tm_clk_aux_locked,
tm_time_valid_o => tm_time_valid, tm_time_valid_o => tm_time_valid,
tm_tai_o => tm_utc, tm_tai_o => tm_utc,
tm_cycles_o => tm_cycles, tm_cycles_o => tm_cycles,
......
-------------------------------------------------------------------------------
-- Title : Fine Delay FMC SPEC (Simple PCIe FMC Carrier) SDB descriptor
-- Project : Fine Delay FMC (fmc-delay-1ns-4cha)
-------------------------------------------------------------------------------
-- File : synthesis_descriptor.vhd
-- Author : Tomasz Wlostowski
-- Company : CERN
-- Created : 2013-04-16
-- Last update: 2013-04-16
-- Platform : FPGA-generic
-- Standard : VHDL'93
-------------------------------------------------------------------------------
-- Description: SDB descriptor for the top level of the FD on a SPEC carrier.
-- Contains synthesis & source repository information.
-- Warning: this file is modified whenever a synthesis is executed.
-------------------------------------------------------------------------------
--
-- Copyright (c) 2013 CERN / BE-CO-HT
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
-- Public License as published by the Free Software Foundation;
-- either version 2.1 of the License, or (at your option) any
-- later version.
--
-- This source is distributed in the hope that it will be
-- useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
-- PURPOSE. See the GNU Lesser General Public License for more
-- details.
--
-- You should have received a copy of the GNU Lesser General
-- Public License along with this source; if not, download it
-- from http://www.gnu.org/licenses/lgpl-2.1.html
--
-------------------------------------------------------------------------------
library ieee;
use ieee.STD_LOGIC_1164.all;
use work.wishbone_pkg.all;
package synthesis_descriptor is
constant c_sdb_synthesis_info : t_sdb_synthesis :=
(
syn_module_name => "fine-delay-spec ",
syn_commit_id => "00000000000000000000000000000000",
syn_tool_name => "ISE ",
syn_tool_version => x"00000133",
syn_date => x"00000000",
syn_username => "twlostow ");
constant c_sdb_repo_url : t_sdb_repo_url :=
(
repo_url => "git://ohwr.org/fmc-projects/fmc-delay-1ns-8cha.git "
);
end package synthesis_descriptor;
files = [ "svec_top.vhd", "svec_top.ucf", "xvme64x_core.vhd" ] files = [ "synthesis_descriptor.vhd", "svec_top.vhd", "svec_top.ucf", "xvme64x_core.vhd" ]
fetchto = "../../../ip_cores" fetchto = "../../../ip_cores"
......
This diff is collapsed.
...@@ -6,7 +6,7 @@ ...@@ -6,7 +6,7 @@
-- Author : Tomasz Wlostowski -- Author : Tomasz Wlostowski
-- Company : CERN -- Company : CERN
-- Created : 2011-08-24 -- Created : 2011-08-24
-- Last update: 2013-02-21 -- Last update: 2013-05-17
-- Platform : FPGA-generic -- Platform : FPGA-generic
-- Standard : VHDL'93 -- Standard : VHDL'93
------------------------------------------------------------------------------- -------------------------------------------------------------------------------
...@@ -51,6 +51,8 @@ use work.fine_delay_pkg.all; ...@@ -51,6 +51,8 @@ use work.fine_delay_pkg.all;
use work.etherbone_pkg.all; use work.etherbone_pkg.all;
use work.wr_xilinx_pkg.all; use work.wr_xilinx_pkg.all;
use work.synthesis_descriptor.all;
library UNISIM; library UNISIM;
use UNISIM.vcomponents.all; use UNISIM.vcomponents.all;
...@@ -142,8 +144,6 @@ entity svec_top is ...@@ -142,8 +144,6 @@ entity svec_top is
tempid_dq_b : inout std_logic; tempid_dq_b : inout std_logic;
fp_ledn_o : out std_logic_vector(7 downto 0);
------------------------------------------------------------------------- -------------------------------------------------------------------------
-- Fine Delay Pins -- Fine Delay Pins
------------------------------------------------------------------------- -------------------------------------------------------------------------
...@@ -237,7 +237,6 @@ architecture rtl of svec_top is ...@@ -237,7 +237,6 @@ architecture rtl of svec_top is
port ( port (
clk_i : in std_logic; clk_i : in std_logic;
rst_n_i : in std_logic; rst_n_i : in std_logic;
rst_n_o : out std_logic;
VME_AS_n_i : in std_logic; VME_AS_n_i : in std_logic;
VME_RST_n_i : in std_logic; VME_RST_n_i : in std_logic;
VME_WRITE_n_i : in std_logic; VME_WRITE_n_i : in std_logic;
...@@ -302,8 +301,6 @@ architecture rtl of svec_top is ...@@ -302,8 +301,6 @@ architecture rtl of svec_top is
signal VME_ADDR_b_out : std_logic_vector(31 downto 1); signal VME_ADDR_b_out : std_logic_vector(31 downto 1);
signal VME_LWORD_n_b_out, VME_DATA_DIR_int, VME_ADDR_DIR_int : std_logic; signal VME_LWORD_n_b_out, VME_DATA_DIR_int, VME_ADDR_DIR_int : std_logic;
signal dac_hpll_load_p1 : std_logic; signal dac_hpll_load_p1 : std_logic;
signal dac_dpll_load_p1 : std_logic; signal dac_dpll_load_p1 : std_logic;
signal dac_hpll_data : std_logic_vector(15 downto 0); signal dac_hpll_data : std_logic_vector(15 downto 0);
...@@ -328,38 +325,31 @@ architecture rtl of svec_top is ...@@ -328,38 +325,31 @@ architecture rtl of svec_top is
constant c_MASTER_VME : integer := 0; constant c_MASTER_VME : integer := 0;
constant c_MASTER_ETHERBONE : integer := 1; constant c_MASTER_ETHERBONE : integer := 1;
constant c_SLAVE_FD1 : integer := 0; constant c_SLAVE_FD1 : integer := 1;
constant c_SLAVE_FD0 : integer := 1; constant c_SLAVE_FD0 : integer := 0;
constant c_SLAVE_WRCORE : integer := 2; constant c_SLAVE_WRCORE : integer := 3;
constant c_SLAVE_VIC : integer := 3; constant c_SLAVE_VIC : integer := 2;
constant c_DESC_SYNTHESIS : integer := 4;
constant c_WRCORE_BRIDGE_SDB : t_sdb_bridge := f_xwb_bridge_manual_sdb(x"0003ffff", x"00040000"); constant c_DESC_REPO_URL : integer := 5;
constant c_xwb_vic_sdb : t_sdb_device := ( constant c_WRCORE_BRIDGE_SDB : t_sdb_bridge := f_xwb_bridge_manual_sdb(x"0003ffff", x"00070000");
abi_class => x"0000", -- undocumented device
abi_ver_major => x"01", constant c_INTERCONNECT_LAYOUT : t_sdb_record_array(c_NUM_WB_MASTERS + 1 downto 0) :=
abi_ver_minor => x"01", (
wbd_endian => c_sdb_endian_big, c_SLAVE_FD0 => f_sdb_embed_device(c_FD_SDB_DEVICE, x"00010000"),
wbd_width => x"7", -- 8/16/32-bit port granularity c_SLAVE_FD1 => f_sdb_embed_device(c_FD_SDB_DEVICE, x"00020000"),
sdb_component => ( c_SLAVE_VIC => f_sdb_embed_device(c_xwb_vic_sdb, x"00030000"),
addr_first => x"0000000000000000", c_SLAVE_WRCORE => f_sdb_embed_bridge(c_WRCORE_BRIDGE_SDB, x"00040000"),
addr_last => x"00000000000000ff", c_DESC_SYNTHESIS => f_sdb_embed_synthesis(c_sdb_synthesis_info),
product => ( c_DESC_REPO_URL => f_sdb_embed_repo_url(c_sdb_repo_url)
vendor_id => x"000000000000CE42", -- CERN
device_id => x"00000013",
version => x"00000001",
date => x"20120113",
name => "WB-VIC-Int.Control ")));
constant c_INTERCONNECT_LAYOUT : t_sdb_record_array(c_NUM_WB_MASTERS-1 downto 0) :=
(c_SLAVE_WRCORE => f_sdb_embed_bridge(c_WRCORE_BRIDGE_SDB, x"00040000"),
c_SLAVE_FD0 => f_sdb_embed_device(c_FD_SDB_DEVICE, x"00010000"),
c_SLAVE_FD1 => f_sdb_embed_device(c_FD_SDB_DEVICE, x"00020000"),
c_SLAVE_VIC => f_sdb_embed_device(c_xwb_vic_sdb, x"00030000")
); );
constant c_SDB_ADDRESS : t_wishbone_address := x"00000000"; constant c_SDB_ADDRESS : t_wishbone_address := x"00000000";
constant c_VIC_VECTOR_TABLE : t_wishbone_address_array(0 to 1) :=
(0 => x"00010000",
1 => x"00020000");
signal cnx_master_out : t_wishbone_master_out_array(c_NUM_WB_MASTERS-1 downto 0); signal cnx_master_out : t_wishbone_master_out_array(c_NUM_WB_MASTERS-1 downto 0);
signal cnx_master_in : t_wishbone_master_in_array(c_NUM_WB_MASTERS-1 downto 0); signal cnx_master_in : t_wishbone_master_in_array(c_NUM_WB_MASTERS-1 downto 0);
...@@ -376,17 +366,14 @@ architecture rtl of svec_top is ...@@ -376,17 +366,14 @@ architecture rtl of svec_top is
signal tdc1_data_out, tdc1_data_in : std_logic_vector(27 downto 0); signal tdc1_data_out, tdc1_data_in : std_logic_vector(27 downto 0);
signal tdc1_data_oe : std_logic; signal tdc1_data_oe : std_logic;
signal tm_link_up : std_logic; signal tm_link_up : std_logic;
signal tm_utc : std_logic_vector(39 downto 0); signal tm_utc : std_logic_vector(39 downto 0);
signal tm_cycles : std_logic_vector(27 downto 0); signal tm_cycles : std_logic_vector(27 downto 0);
signal tm_time_valid : std_logic; signal tm_time_valid : std_logic;
signal tm0_clk_aux_lock_en : std_logic; signal tm_clk_aux_lock_en : std_logic_vector(1 downto 0);
signal tm0_clk_aux_locked : std_logic; signal tm_clk_aux_locked : std_logic_vector(1 downto 0);
signal tm1_clk_aux_lock_en : std_logic; signal tm_dac_value : std_logic_vector(23 downto 0);
signal tm1_clk_aux_locked : std_logic; signal tm_dac_wr : std_logic_vector(1 downto 0);
signal tm_dac_value : std_logic_vector(23 downto 0);
signal tm0_dac_wr : std_logic;
signal tm1_dac_wr : std_logic;
signal ddr0_pll_reset : std_logic; signal ddr0_pll_reset : std_logic;
signal ddr0_pll_locked, fd0_pll_status : std_logic; signal ddr0_pll_locked, fd0_pll_status : std_logic;
...@@ -419,11 +406,8 @@ architecture rtl of svec_top is ...@@ -419,11 +406,8 @@ architecture rtl of svec_top is
signal vme_master_out : t_wishbone_master_out; signal vme_master_out : t_wishbone_master_out;
signal vme_master_in : t_wishbone_master_in; signal vme_master_in : t_wishbone_master_in;
signal pins : std_logic_vector(31 downto 0); signal pins : std_logic_vector(31 downto 0);
signal pps : std_logic; signal pps : std_logic;
signal led_divider : unsigned(22 downto 0);
signal leds : std_logic_vector(7 downto 0);
signal vic_master_irq : std_logic; signal vic_master_irq : std_logic;
...@@ -674,17 +658,17 @@ begin ...@@ -674,17 +658,17 @@ begin
g_phys_uart => true, g_phys_uart => true,
g_virtual_uart => true, g_virtual_uart => true,
g_with_external_clock_input => false, g_with_external_clock_input => false,
g_aux_clks => 1, g_aux_clks => 2,
g_ep_rxbuf_size => 1024,
g_dpram_initf => "wrc.ram",
g_dpram_size => 90112/4, --16384,
g_interface_mode => PIPELINED, g_interface_mode => PIPELINED,
g_address_granularity => BYTE) g_address_granularity => BYTE,
-- g_softpll_enable_debugger => true,
g_dpram_initf => "none")
port map ( port map (
clk_sys_i => clk_sys, clk_sys_i => clk_sys,
clk_dmtd_i => clk_dmtd, clk_dmtd_i => clk_dmtd,
clk_ref_i => clk_125m_pllref, clk_ref_i => clk_125m_pllref,
clk_aux_i(0) => dcm0_clk_ref_0, clk_aux_i(0) => dcm0_clk_ref_0,
clk_aux_i(1) => dcm1_clk_ref_0,
rst_n_i => local_reset_n, rst_n_i => local_reset_n,
dac_hpll_load_p1_o => dac_hpll_load_p1, dac_hpll_load_p1_o => dac_hpll_load_p1,
...@@ -705,8 +689,8 @@ begin ...@@ -705,8 +689,8 @@ begin
phy_rst_o => phy_rst, phy_rst_o => phy_rst,
phy_loopen_o => phy_loopen, phy_loopen_o => phy_loopen,
led_link_o => open, led_link_o => open,
led_act_o => open, led_act_o => open,
scl_o => wrc_scl_out, scl_o => wrc_scl_out,
scl_i => wrc_scl_in, scl_i => wrc_scl_in,
...@@ -740,9 +724,9 @@ begin ...@@ -740,9 +724,9 @@ begin
tm_link_up_o => tm_link_up, tm_link_up_o => tm_link_up,
tm_dac_value_o => tm_dac_value, tm_dac_value_o => tm_dac_value,
tm_dac_wr_o => tm0_dac_wr, tm_dac_wr_o => tm_dac_wr(0),
tm_clk_aux_lock_en_i => tm0_clk_aux_lock_en, tm_clk_aux_lock_en_i => tm_clk_aux_lock_en(0),
tm_clk_aux_locked_o => tm0_clk_aux_locked, tm_clk_aux_locked_o => tm_clk_aux_locked(0),
tm_time_valid_o => tm_time_valid, tm_time_valid_o => tm_time_valid,
tm_tai_o => tm_utc, tm_tai_o => tm_utc,
tm_cycles_o => tm_cycles, tm_cycles_o => tm_cycles,
...@@ -821,7 +805,8 @@ begin ...@@ -821,7 +805,8 @@ begin
generic map ( generic map (
g_interface_mode => PIPELINED, g_interface_mode => PIPELINED,
g_address_granularity => BYTE, g_address_granularity => BYTE,
g_num_interrupts => 2) g_num_interrupts => 2,
g_init_vectors => c_VIC_VECTOR_TABLE)
port map ( port map (
clk_sys_i => clk_sys, clk_sys_i => clk_sys,
rst_n_i => local_reset_n, rst_n_i => local_reset_n,
...@@ -951,12 +936,11 @@ begin ...@@ -951,12 +936,11 @@ begin
tm_time_valid_i => tm_time_valid, tm_time_valid_i => tm_time_valid,
tm_cycles_i => tm_cycles, tm_cycles_i => tm_cycles,
tm_utc_i => tm_utc, tm_utc_i => tm_utc,
tm_clk_aux_lock_en_o => tm0_clk_aux_lock_en, tm_clk_aux_lock_en_o => tm_clk_aux_lock_en(0),
tm_clk_aux_locked_i => tm0_clk_aux_locked, tm_clk_aux_locked_i => tm_clk_aux_locked(0),
tm_clk_dmtd_locked_i => '1', -- FIXME: fan out real signal from the tm_clk_dmtd_locked_i => '1',
-- WRCore
tm_dac_value_i => tm_dac_value, tm_dac_value_i => tm_dac_value,
tm_dac_wr_i => tm0_dac_wr, tm_dac_wr_i => tm_dac_wr(0),
owr_en_o => fd0_owr_en, owr_en_o => fd0_owr_en,
owr_i => fd0_owr_in, owr_i => fd0_owr_in,
...@@ -1065,12 +1049,12 @@ begin ...@@ -1065,12 +1049,12 @@ begin
tm_time_valid_i => tm_time_valid, tm_time_valid_i => tm_time_valid,
tm_cycles_i => tm_cycles, tm_cycles_i => tm_cycles,
tm_utc_i => tm_utc, tm_utc_i => tm_utc,
tm_clk_aux_lock_en_o => tm1_clk_aux_lock_en, tm_clk_aux_lock_en_o => tm_clk_aux_lock_en(1),
tm_clk_aux_locked_i => tm1_clk_aux_locked, tm_clk_aux_locked_i => tm_clk_aux_locked(1),
tm_clk_dmtd_locked_i => '1', -- FIXME: fan out real signal from the tm_clk_dmtd_locked_i => '1', -- FIXME: fan out real signal from the
-- -- WRCore -- -- WRCore
tm_dac_value_i => tm_dac_value, tm_dac_value_i => tm_dac_value,
tm_dac_wr_i => tm1_dac_wr, tm_dac_wr_i => '0',
owr_en_o => fd1_owr_en, owr_en_o => fd1_owr_en,
owr_i => fd1_owr_in, owr_i => fd1_owr_in,
...@@ -1104,26 +1088,6 @@ begin ...@@ -1104,26 +1088,6 @@ begin
sfp_tx_disable_o <= '0'; sfp_tx_disable_o <= '0';
p_drive_leds : process(clk_sys)
begin
if rising_edge(clk_sys) then
if(local_reset_n = '0') then
leds <= "01111111";
led_divider <= (others => '0');
else
led_divider <= led_divider+ 1;
if(led_divider = 0) then
leds <= leds(6 downto 0) & leds(7);
end if;
end if;
end if;
end process;
fp_ledn_o <= leds;
end rtl; end rtl;
-------------------------------------------------------------------------------
-- Title : Fine Delay FMC SVEC (Simple VME FMC Carrier) SDB descriptor
-- Project : Fine Delay FMC (fmc-delay-1ns-4cha)
-------------------------------------------------------------------------------
-- File : synthesis_descriptor.vhd
-- Author : Tomasz Wlostowski
-- Company : CERN
-- Created : 2013-04-16
-- Last update: 2013-04-16
-- Platform : FPGA-generic
-- Standard : VHDL'93
-------------------------------------------------------------------------------
-- Description: SDB descriptor for the top level of the FD on a SVEC carrier.
-- Contains synthesis & source repository information.
-- Warning: this file is modified whenever a synthesis is executed.
-------------------------------------------------------------------------------
--
-- Copyright (c) 2013 CERN / BE-CO-HT
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
-- Public License as published by the Free Software Foundation;
-- either version 2.1 of the License, or (at your option) any
-- later version.
--
-- This source is distributed in the hope that it will be
-- useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
-- PURPOSE. See the GNU Lesser General Public License for more
-- details.
--
-- You should have received a copy of the GNU Lesser General
-- Public License along with this source; if not, download it
-- from http://www.gnu.org/licenses/lgpl-2.1.html
--
-------------------------------------------------------------------------------
library ieee;
use ieee.STD_LOGIC_1164.all;
use work.wishbone_pkg.all;
package synthesis_descriptor is
constant c_sdb_synthesis_info : t_sdb_synthesis :=
(
syn_module_name => "fine-delay-svec ",
syn_commit_id => "00000000000000000000000000000000",
syn_tool_name => "ISE ",
syn_tool_version => x"00000133",
syn_date => x"00000000",
syn_username => "twlostow ");
constant c_sdb_repo_url : t_sdb_repo_url :=
(
repo_url => "git://ohwr.org/fmc-projects/fmc-delay-1ns-8cha.git "
);
end package synthesis_descriptor;
...@@ -9,8 +9,6 @@ entity xvme64x_core is ...@@ -9,8 +9,6 @@ entity xvme64x_core is
clk_i : in std_logic; clk_i : in std_logic;
rst_n_i : in std_logic; rst_n_i : in std_logic;
rst_n_o : out std_logic;
VME_AS_n_i : in std_logic; VME_AS_n_i : in std_logic;
VME_RST_n_i : in std_logic; VME_RST_n_i : in std_logic;
VME_WRITE_n_i : in std_logic; VME_WRITE_n_i : in std_logic;
...@@ -51,12 +49,12 @@ architecture wrapper of xvme64x_core is ...@@ -51,12 +49,12 @@ architecture wrapper of xvme64x_core is
component VME64xCore_Top component VME64xCore_Top
generic ( generic (
g_wb_data_width : integer := 32; g_wb_data_width : integer := 32;
g_wb_addr_width : integer := 64; g_wb_addr_width : integer := 64;
g_CRAM_SIZE : integer := 1024); g_CRAM_SIZE : integer := 1024);
port ( port (
clk_i : in std_logic; clk_i : in std_logic;
reset_o : out std_logic; rst_n_i : in std_logic;
VME_AS_n_i : in std_logic; VME_AS_n_i : in std_logic;
VME_RST_n_i : in std_logic; VME_RST_n_i : in std_logic;
VME_WRITE_n_i : in std_logic; VME_WRITE_n_i : in std_logic;
...@@ -98,19 +96,16 @@ architecture wrapper of xvme64x_core is ...@@ -98,19 +96,16 @@ architecture wrapper of xvme64x_core is
debug : out std_logic_vector(7 downto 0)); debug : out std_logic_vector(7 downto 0));
end component; end component;
signal rst_in, rst_out : std_logic; signal rst_in, rst_out : std_logic;
signal dat_out, dat_in : std_logic_vector(31 downto 0); signal dat_out, dat_in : std_logic_vector(31 downto 0);
signal adr_out : std_logic_vector(63 downto 0); signal adr_out : std_logic_vector(63 downto 0);
begin -- wrapper begin -- wrapper
rst_in <= not rst_n_i;
rst_n_o <= rst_n_i and (not rst_out);
U_Wrapped_VME : VME64xCore_Top U_Wrapped_VME : VME64xCore_Top
port map ( port map (
clk_i => clk_i, clk_i => clk_i,
reset_o => rst_out, rst_n_i => rst_n_i,
VME_AS_n_i => VME_AS_n_i, VME_AS_n_i => VME_AS_n_i,
VME_RST_n_i => VME_RST_n_i, VME_RST_n_i => VME_RST_n_i,
VME_WRITE_n_i => VME_WRITE_n_i, VME_WRITE_n_i => VME_WRITE_n_i,
...@@ -121,13 +116,13 @@ begin -- wrapper ...@@ -121,13 +116,13 @@ begin -- wrapper
VME_DTACK_n_o => VME_DTACK_n_o, VME_DTACK_n_o => VME_DTACK_n_o,
VME_RETRY_n_o => VME_RETRY_n_o, VME_RETRY_n_o => VME_RETRY_n_o,
VME_RETRY_OE_o => VME_RETRY_OE_o, VME_RETRY_OE_o => VME_RETRY_OE_o,
VME_LWORD_n_i => VME_LWORD_n_b_i, VME_LWORD_n_i => VME_LWORD_n_b_i,
VME_LWORD_n_o => VME_LWORD_n_b_o, VME_LWORD_n_o => VME_LWORD_n_b_o,
VME_ADDR_i => VME_ADDR_b_i, VME_ADDR_i => VME_ADDR_b_i,
VME_ADDR_o => VME_ADDR_b_o, VME_ADDR_o => VME_ADDR_b_o,
VME_DATA_i => VME_DATA_b_i, VME_DATA_i => VME_DATA_b_i,
VME_DATA_o => VME_DATA_b_o, VME_DATA_o => VME_DATA_b_o,
VME_IRQ_o => VME_IRQ_n_o, VME_IRQ_o => VME_IRQ_n_o,
VME_IACKIN_n_i => VME_IACKIN_n_i, VME_IACKIN_n_i => VME_IACKIN_n_i,
VME_IACK_n_i => VME_IACK_n_i, VME_IACK_n_i => VME_IACK_n_i,
VME_IACKOUT_n_o => VME_IACKOUT_n_o, VME_IACKOUT_n_o => VME_IACKOUT_n_o,
...@@ -137,18 +132,18 @@ begin -- wrapper ...@@ -137,18 +132,18 @@ begin -- wrapper
VME_ADDR_DIR_o => VME_ADDR_DIR_o, VME_ADDR_DIR_o => VME_ADDR_DIR_o,
VME_ADDR_OE_N_o => VME_ADDR_OE_N_o, VME_ADDR_OE_N_o => VME_ADDR_OE_N_o,
DAT_i => dat_in, DAT_i => dat_in,
DAT_o => dat_out, DAT_o => dat_out,
ADR_o => adr_out, ADR_o => adr_out,
CYC_o => master_o.cyc, CYC_o => master_o.cyc,
ERR_i => master_i.err, ERR_i => master_i.err,
RTY_i => master_i.rty, RTY_i => master_i.rty,
SEL_o => open, SEL_o => open,
STB_o => master_o.stb, STB_o => master_o.stb,
ACK_i => master_i.ack, ACK_i => master_i.ack,
WE_o => master_o.we, WE_o => master_o.we,
STALL_i => master_i.stall, STALL_i => master_i.stall,
IRQ_i => irq_i, IRQ_i => irq_i,
INT_ack_o => irq_ack_o INT_ack_o => irq_ack_o
); );
......
...@@ -20,7 +20,15 @@ ...@@ -20,7 +20,15 @@
#define AR2_Disable(chan) (1<<(3+chan)) #define AR2_Disable(chan) (1<<(3+chan))
#define AR2_Adj(chan, value) (((value)&0xf)<<(12+4*(chan-7))) #define AR2_Adj(chan, value) (((value)&0xf)<<(12+4*(chan-7)))
#define AR3_RaSpeed(num,val) (val << (num*2 + 21)) #define AR2_DelRise1(value) (((value)&0x3)<<(20))
#define AR2_DelFall1(value) (((value)&0x3)<<(22))
#define AR2_DelRise2(value) (((value)&0x3)<<(24))
#define AR2_DelFall2(value) (((value)&0x3)<<(26))
#define AR3_DelTx(chan, value) (((value)&0x3)<<(5 + (chan -1 ) * 2))
#define AR3_RaSpeed(chan, value) (((value)&0x3)<<(21 + (chan ) * 2))
#define AR4_RaSpeed(chan, value) (((value)&0x3)<<(10 + (chan-3) * 2))
#define AR3_Zero (0) // nothing interesting for the Fine Delay #define AR3_Zero (0) // nothing interesting for the Fine Delay
......
...@@ -3,7 +3,7 @@ ...@@ -3,7 +3,7 @@
* File : fd_channel_regs.h * File : fd_channel_regs.h
* Author : auto-generated by wbgen2 from fd_channel_wishbone_slave.wb * Author : auto-generated by wbgen2 from fd_channel_wishbone_slave.wb
* Created : Wed Apr 11 11:05:22 2012 * Created : Fri Feb 15 12:07:17 2013
* Standard : ANSI C * Standard : ANSI C
THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE fd_channel_wishbone_slave.wb THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE fd_channel_wishbone_slave.wb
...@@ -57,8 +57,8 @@ ...@@ -57,8 +57,8 @@
/* definitions for field: Disable Fine Part update in reg: Delay Control Register */ /* definitions for field: Disable Fine Part update in reg: Delay Control Register */
#define FD_DCR_NO_FINE WBGEN2_GEN_MASK(7, 1) #define FD_DCR_NO_FINE WBGEN2_GEN_MASK(7, 1)
/* definitions for field: Disable Fine Part update in reg: Delay Control Register */ /* definitions for field: Force Output High in reg: Delay Control Register */
#define FD_DCR_FORCE_HI WBGEN2_GEN_MASK(8, 1) #define FD_DCR_FORCE_HI WBGEN2_GEN_MASK(8, 1)
/* definitions for register: Fine Range Register */ /* definitions for register: Fine Range Register */
......
...@@ -3,7 +3,7 @@ ...@@ -3,7 +3,7 @@
* File : fd_main_regs.h * File : fd_main_regs.h
* Author : auto-generated by wbgen2 from fd_main_wishbone_slave.wb * Author : auto-generated by wbgen2 from fd_main_wishbone_slave.wb
* Created : Mon Jun 4 13:42:20 2012 * Created : Fri Feb 15 12:07:16 2013
* Standard : ANSI C * Standard : ANSI C
THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE fd_main_wishbone_slave.wb THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE fd_main_wishbone_slave.wb
...@@ -64,7 +64,7 @@ ...@@ -64,7 +64,7 @@
/* definitions for field: PLL Locked in reg: Global Control Register */ /* definitions for field: PLL Locked in reg: Global Control Register */
#define FD_GCR_DDR_LOCKED WBGEN2_GEN_MASK(2, 1) #define FD_GCR_DDR_LOCKED WBGEN2_GEN_MASK(2, 1)
/* definitions for field: Mezzanice Present in reg: Global Control Register */ /* definitions for field: Mezzanine Present in reg: Global Control Register */
#define FD_GCR_FMC_PRESENT WBGEN2_GEN_MASK(3, 1) #define FD_GCR_FMC_PRESENT WBGEN2_GEN_MASK(3, 1)
/* definitions for register: Timing Control Register */ /* definitions for register: Timing Control Register */
...@@ -99,46 +99,46 @@ ...@@ -99,46 +99,46 @@
/* definitions for register: Time Register - sub-second 125 MHz clock cycles */ /* definitions for register: Time Register - sub-second 125 MHz clock cycles */
/* definitions for register: TDC Data Register */ /* definitions for register: Host-driven TDC Data Register */
/* definitions for register: TDC control/status reg */ /* definitions for register: Host-driven TDC Control/Status */
/* definitions for field: Start TDC write in reg: TDC control/status reg */ /* definitions for field: Write to TDC in reg: Host-driven TDC Control/Status */
#define FD_TDCSR_WRITE WBGEN2_GEN_MASK(0, 1) #define FD_TDCSR_WRITE WBGEN2_GEN_MASK(0, 1)
/* definitions for field: Start TDC read in reg: TDC control/status reg */ /* definitions for field: Read from TDC in reg: Host-driven TDC Control/Status */
#define FD_TDCSR_READ WBGEN2_GEN_MASK(1, 1) #define FD_TDCSR_READ WBGEN2_GEN_MASK(1, 1)
/* definitions for field: Empty flag in reg: TDC control/status reg */ /* definitions for field: Empty flag in reg: Host-driven TDC Control/Status */
#define FD_TDCSR_EMPTY WBGEN2_GEN_MASK(2, 1) #define FD_TDCSR_EMPTY WBGEN2_GEN_MASK(2, 1)
/* definitions for field: Start enable in reg: TDC control/status reg */ /* definitions for field: Stop enable in reg: Host-driven TDC Control/Status */
#define FD_TDCSR_STOP_EN WBGEN2_GEN_MASK(3, 1) #define FD_TDCSR_STOP_EN WBGEN2_GEN_MASK(3, 1)
/* definitions for field: Start disable in reg: TDC control/status reg */ /* definitions for field: Start disable in reg: Host-driven TDC Control/Status */
#define FD_TDCSR_START_DIS WBGEN2_GEN_MASK(4, 1) #define FD_TDCSR_START_DIS WBGEN2_GEN_MASK(4, 1)
/* definitions for field: Stop enable in reg: TDC control/status reg */ /* definitions for field: Start enable in reg: Host-driven TDC Control/Status */
#define FD_TDCSR_START_EN WBGEN2_GEN_MASK(5, 1) #define FD_TDCSR_START_EN WBGEN2_GEN_MASK(5, 1)
/* definitions for field: Stop disable in reg: TDC control/status reg */ /* definitions for field: Stop disable in reg: Host-driven TDC Control/Status */
#define FD_TDCSR_STOP_DIS WBGEN2_GEN_MASK(6, 1) #define FD_TDCSR_STOP_DIS WBGEN2_GEN_MASK(6, 1)
/* definitions for field: write 1: Pulse the Alutrigger line in reg: TDC control/status reg */ /* definitions for field: Pulse <code>Alutrigger</code> line in reg: Host-driven TDC Control/Status */
#define FD_TDCSR_ALUTRIG WBGEN2_GEN_MASK(7, 1) #define FD_TDCSR_ALUTRIG WBGEN2_GEN_MASK(7, 1)
/* definitions for register: Calibration register */ /* definitions for register: Calibration register */
/* definitions for field: Triggers calibration pulses in reg: Calibration register */ /* definitions for field: Generate calibration pulses (type 1 calibration) in reg: Calibration register */
#define FD_CALR_CAL_PULSE WBGEN2_GEN_MASK(0, 1) #define FD_CALR_CAL_PULSE WBGEN2_GEN_MASK(0, 1)
/* definitions for field: PPS Calibration output enable in reg: Calibration register */ /* definitions for field: PPS Calibration output enable in reg: Calibration register */
#define FD_CALR_CAL_PPS WBGEN2_GEN_MASK(1, 1) #define FD_CALR_CAL_PPS WBGEN2_GEN_MASK(1, 1)
/* definitions for field: Produce DDMTD calibration pattern in reg: Calibration register */ /* definitions for field: Produce DDMTD calibration pattern (type 2 calibration) in reg: Calibration register */
#define FD_CALR_CAL_DMTD WBGEN2_GEN_MASK(2, 1) #define FD_CALR_CAL_DMTD WBGEN2_GEN_MASK(2, 1)
/* definitions for field: Enable pulse generation in reg: Calibration register */ /* definitions for field: Calibration pulse output select/mask in reg: Calibration register */
#define FD_CALR_PSEL_MASK WBGEN2_GEN_MASK(3, 4) #define FD_CALR_PSEL_MASK WBGEN2_GEN_MASK(3, 4)
#define FD_CALR_PSEL_SHIFT 3 #define FD_CALR_PSEL_SHIFT 3
#define FD_CALR_PSEL_W(value) WBGEN2_GEN_WRITE(value, 3, 4) #define FD_CALR_PSEL_W(value) WBGEN2_GEN_WRITE(value, 3, 4)
...@@ -171,16 +171,16 @@ ...@@ -171,16 +171,16 @@
/* definitions for register: Acam Timestamp Merging Control Register */ /* definitions for register: Acam Timestamp Merging Control Register */
/* definitions for field: Wraparound Coarse Threshold in reg: Acam Timestamp Merging Control Register */ /* definitions for field: Wraparound Coarse Threshold in reg: Acam Timestamp Merging Control Register */
#define FD_ATMCR_C_THR_MASK WBGEN2_GEN_MASK(0, 4) #define FD_ATMCR_C_THR_MASK WBGEN2_GEN_MASK(0, 8)
#define FD_ATMCR_C_THR_SHIFT 0 #define FD_ATMCR_C_THR_SHIFT 0
#define FD_ATMCR_C_THR_W(value) WBGEN2_GEN_WRITE(value, 0, 4) #define FD_ATMCR_C_THR_W(value) WBGEN2_GEN_WRITE(value, 0, 8)
#define FD_ATMCR_C_THR_R(reg) WBGEN2_GEN_READ(reg, 0, 4) #define FD_ATMCR_C_THR_R(reg) WBGEN2_GEN_READ(reg, 0, 8)
/* definitions for field: Wraparound Fine Threshold in reg: Acam Timestamp Merging Control Register */ /* definitions for field: Wraparound Fine Threshold in reg: Acam Timestamp Merging Control Register */
#define FD_ATMCR_F_THR_MASK WBGEN2_GEN_MASK(4, 23) #define FD_ATMCR_F_THR_MASK WBGEN2_GEN_MASK(8, 23)
#define FD_ATMCR_F_THR_SHIFT 4 #define FD_ATMCR_F_THR_SHIFT 8
#define FD_ATMCR_F_THR_W(value) WBGEN2_GEN_WRITE(value, 4, 23) #define FD_ATMCR_F_THR_W(value) WBGEN2_GEN_WRITE(value, 8, 23)
#define FD_ATMCR_F_THR_R(reg) WBGEN2_GEN_READ(reg, 4, 23) #define FD_ATMCR_F_THR_R(reg) WBGEN2_GEN_READ(reg, 8, 23)
/* definitions for register: Acam Start Offset Register */ /* definitions for register: Acam Start Offset Register */
...@@ -399,9 +399,9 @@ ...@@ -399,9 +399,9 @@
#define FD_REG_TM_SECL 0x00000014 #define FD_REG_TM_SECL 0x00000014
/* [0x18]: REG Time Register - sub-second 125 MHz clock cycles */ /* [0x18]: REG Time Register - sub-second 125 MHz clock cycles */
#define FD_REG_TM_CYCLES 0x00000018 #define FD_REG_TM_CYCLES 0x00000018
/* [0x1c]: REG TDC Data Register */ /* [0x1c]: REG Host-driven TDC Data Register */
#define FD_REG_TDR 0x0000001c #define FD_REG_TDR 0x0000001c
/* [0x20]: REG TDC control/status reg */ /* [0x20]: REG Host-driven TDC Control/Status */
#define FD_REG_TDCSR 0x00000020 #define FD_REG_TDCSR 0x00000020
/* [0x24]: REG Calibration register */ /* [0x24]: REG Calibration register */
#define FD_REG_CALR 0x00000024 #define FD_REG_CALR 0x00000024
......
...@@ -66,6 +66,7 @@ PUBLIC API ...@@ -66,6 +66,7 @@ PUBLIC API
*/ */
fdelay_device_t *fdelay_create();
/* Creates a local instance of Fine Delay Core at address base_addr on the SPEC at bus/devfn. Returns 0 on success, negative on error. */ /* Creates a local instance of Fine Delay Core at address base_addr on the SPEC at bus/devfn. Returns 0 on success, negative on error. */
int spec_fdelay_create_bd(fdelay_device_t *dev, int bus, int dev_fn, uint32_t base); int spec_fdelay_create_bd(fdelay_device_t *dev, int bus, int dev_fn, uint32_t base);
...@@ -117,6 +118,7 @@ int fdelay_configure_capture (fdelay_device_t *dev, int enable, int channel_mask ...@@ -117,6 +118,7 @@ int fdelay_configure_capture (fdelay_device_t *dev, int enable, int channel_mask
int fdelay_read (fdelay_device_t *dev, fdelay_time_t *timestamps, int how_many); int fdelay_read (fdelay_device_t *dev, fdelay_time_t *timestamps, int how_many);
int fdelay_configure_output(fdelay_device_t *dev, int channel, int enable, int64_t delay_ps, int64_t width_ps, int64_t delta_ps, int rep_count) ;
/* (delay mode only) Configures output(s) selected in channel_mask to work in delay mode. Delta_ps = spacing between /* (delay mode only) Configures output(s) selected in channel_mask to work in delay mode. Delta_ps = spacing between
the rising edges of subsequent pulses. */ the rising edges of subsequent pulses. */
int fdelay_configure_delay (fdelay_device_t *dev, int channel_mask, int enable, int64_t delay_ps, int64_t width_ps, int64_t delta_ps, int repeat_count); int fdelay_configure_delay (fdelay_device_t *dev, int channel_mask, int enable, int64_t delay_ps, int64_t width_ps, int64_t delta_ps, int repeat_count);
...@@ -134,5 +136,6 @@ int fdelay_get_time(fdelay_device_t *dev, fdelay_time_t *t); ...@@ -134,5 +136,6 @@ int fdelay_get_time(fdelay_device_t *dev, fdelay_time_t *t);
int fdelay_set_time(fdelay_device_t *dev, const fdelay_time_t t); int fdelay_set_time(fdelay_device_t *dev, const fdelay_time_t t);
int fdelay_dmtd_calibration(fdelay_device_t *dev, double *offsets); int fdelay_dmtd_calibration(fdelay_device_t *dev, double *offsets);
float fdelay_get_board_temperature(fdelay_device_t *dev);
#endif #endif
...@@ -31,6 +31,7 @@ ...@@ -31,6 +31,7 @@
/* ACAM TDC operation modes */ /* ACAM TDC operation modes */
#define ACAM_RMODE 0 #define ACAM_RMODE 0
#define ACAM_IMODE 1 #define ACAM_IMODE 1
#define ACAM_GMODE 2
/* MCP23S17 register addresses (only ones which are used by the lib) */ /* MCP23S17 register addresses (only ones which are used by the lib) */
#define MCP_IODIR 0x0 #define MCP_IODIR 0x0
......
SPEC_SW ?= $(shell readlink -f ~/wr-repos/spec-sw) SPEC_SW ?= $(shell readlink -f ~/wr-repos/spec-sw)
ETHERBONE ?= $(shell readlink -f ~/wr-repos/etherbone-core/api) ETHERBONE ?= $(shell readlink -f ~/wr-repos/etherbone-core/api)
OBJS = fdelay_lib.o i2c_master.o onewire.o fdelay_bus.o spec/tools/speclib.o spec/kernel/loader-ll.o fdelay_dmtd_calibration.o simple-eb.o OBJS = fdelay_lib.o i2c_master.o onewire.o fdelay_bus.o fdelay_dmtd_calibration.o sveclib/sveclib.o sveclib/libvmebus.o speclib/speclib.o
CFLAGS = -I../include -g -Imini_bone -Ispec/tools -Ietherbone CFLAGS = -I../include -g -Imini_bone -Ispec/tools -Isveclib -I.
ifeq ($(SPEC_SW),) #ifeq ($(SPEC_SW),)
throw_error: #throw_error:
@echo "SPEC software package location environment variable is not set. Can't compile :(" # @echo "SPEC software package location environment variable is not set. Can't compile :("
endif #endif
all: spec lib all: lib
spec: #spec:
ln -s $(SPEC_SW) spec # ln -s $(SPEC_SW) spec
ln -s $(ETHERBONE) etherbone # ln -s $(ETHERBONE) etherbone
lib: $(OBJS) lib: $(OBJS)
gcc -shared -o libfinedelay.so $(OBJS) -letherbone gcc -shared -o libfinedelay.so $(OBJS)
ar rc libfinedelay.a $(OBJS) ar rc libfinedelay.a $(OBJS)
clean: clean:
......
...@@ -4,13 +4,24 @@ ...@@ -4,13 +4,24 @@
#include <getopt.h> #include <getopt.h>
#include "fdelay_lib.h" #include "fdelay_lib.h"
#include "simple-eb.h"
#include "spec/tools/speclib.h" #include "sveclib/sveclib.h"
#include "speclib/speclib.h"
#include "fdelay_lib.h" #include "fdelay_lib.h"
void printk() {}; void printk() {};
static void fd_svec_writel(void *priv, uint32_t data, uint32_t addr)
{
svec_writel(priv, data, addr);
}
static uint32_t fd_svec_readl(void *priv, uint32_t addr)
{
return svec_readl(priv, addr);
}
static void fd_spec_writel(void *priv, uint32_t data, uint32_t addr) static void fd_spec_writel(void *priv, uint32_t data, uint32_t addr)
{ {
spec_writel(priv, data, addr); spec_writel(priv, data, addr);
...@@ -22,94 +33,79 @@ static uint32_t fd_spec_readl(void *priv, uint32_t addr) ...@@ -22,94 +33,79 @@ static uint32_t fd_spec_readl(void *priv, uint32_t addr)
} }
#if 0 #if 0
static int spec_fdelay_create(fdelay_device_t *dev, int bus, int dev_fn) #endif
{
uint32_t base;
dev->priv_io = spec_open(bus, dev_fn);
if(!dev->priv_io)
#define VENDOR_CERN 0xce42
#define DEVICE_FD_CORE 0xf19ede1a
#define DEVICE_VUART 0xe2d13d04
static int probe_svec(fdelay_device_t *dev, const char *location)
{
uint32_t map_base;
int slot;
void *card;
uint32_t core_base;
if (!strncmp(location, "svec:"), 5) {
sscanf(location+5, "%d,%x,%x", &slot, &map_base, &core_base);
} else
return -1;
card = svec_open(slot);
svec_set_map_base(card, map_base);
if(!card)
{ {
fprintf(stderr,"Can't map the SPEC @ %x:%x\n", bus, dev_fn); fprintf(stderr,"SVEC probe failed.\n");
return -1; return -1;
} }
dev->writel = fd_spec_writel; dev->priv_io = card;
dev->readl = fd_spec_readl; dev->writel = fd_svec_writel;
dev->base_addr = base; dev->readl = fd_svec_readl;
dev->base_addr = core_base;
//spec_vuart_init(dev->priv_io, 0xe0500); /* for communication with WRCore during DMTD calibration */ dbg("svec: using slot %d, A32/D32 base: 0x%x, core base 0x%x\n", slot, map_base, core_base);
return 0;
return 0;
} }
#endif
static void fd_eb_writel(void *priv, uint32_t data, uint32_t addr) void loader_low_level() {};
{
ebs_write((eb_device_t) priv, addr, data);
}
static uint32_t fd_eb_readl(void *priv, uint32_t addr) static int probe_spec(fdelay_device_t *dev, const char *location)
{ {
return ebs_read((eb_device_t) priv, addr); uint32_t core_base;
} int slot;
if (!strncmp(location, "spec:"), 5) {
sscanf(location+5, "%d,%x", &slot, &core_base);
} else
return -1;
dev->priv_io = spec_open(slot, -1);
#define VENDOR_CERN 0xce42 if(!dev->priv_io)
#define DEVICE_FD_CORE 0xf19ede1a {
#define DEVICE_VUART 0xe2d13d04 fprintf(stderr,"Can't map the SPEC @ slot %d\n", slot);
return -1;
}
dev->writel = fd_spec_writel;
dev->readl = fd_spec_readl;
dev->base_addr = core_base;
dbg("spec: using slot %d, core base 0x%x\n", slot, core_base);
return 0;
}
int fdelay_probe(fdelay_device_t *dev, const char *location) int fdelay_probe(fdelay_device_t *dev, const char *location)
{ {
int bus = -1, dev_fn = -1; if(!probe_svec(dev, location))
char ip_addr[128]; return 0;
int use_eb = 0; if(!probe_spec(dev, location))
uint32_t base_core; return 0;
if(!strncmp(location, "eb:", 3))
{
snprintf(ip_addr, sizeof(ip_addr), "udp/%s", location+3);
use_eb = 1;
} else if (!strncmp(location, "spec:"), 5) {
sscanf(location+5, "%d,%d", &bus, &dev_fn);
}
if(use_eb)
{
dbg("Probing with Etherbone [%s]\n", ip_addr);
if( ebs_init() != EB_OK)
{
fprintf(stderr,"Can't initialize Etherbone library.\n");
return -1;
}
if(ebs_open((eb_device_t*) &dev->priv_io, ip_addr) != EB_OK)
{
fprintf(stderr,"Can't connect to Etherbone device %s.\n", location);
return -1;
}
if(!ebs_sdb_find_device((eb_device_t ) dev->priv_io, VENDOR_CERN, DEVICE_FD_CORE, 0, &base_core))
{
fprintf(stderr,"Can't detect the FD core. Is the bitstream loaded?\n", location);
return -1;
}
dev->writel = fd_eb_writel;
dev->readl = fd_eb_readl;
dev->base_addr = base_core;
dbg("Found FD core @ 0x%x\n", base_core);
} else {
dbg("Sorry, SPEC temporarily unsupported\n.");
return -1;
}
} }
fdelay_device_t *fdelay_create() fdelay_device_t *fdelay_create()
......
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...@@ -172,6 +172,7 @@ int ds18x_init(fdelay_device_t *dev) ...@@ -172,6 +172,7 @@ int ds18x_init(fdelay_device_t *dev)
{ {
ow_init(dev); ow_init(dev);
if(ds18x_read_serial(dev, ds18x_id) < 0) if(ds18x_read_serial(dev, ds18x_id) < 0)
return -1; return -1;
...@@ -179,5 +180,7 @@ int ds18x_init(fdelay_device_t *dev) ...@@ -179,5 +180,7 @@ int ds18x_init(fdelay_device_t *dev)
ds18x_id[0], ds18x_id[1], ds18x_id[2], ds18x_id[3], ds18x_id[0], ds18x_id[1], ds18x_id[2], ds18x_id[3],
ds18x_id[4], ds18x_id[5], ds18x_id[6], ds18x_id[7]); ds18x_id[4], ds18x_id[5], ds18x_id[6], ds18x_id[7]);
return ds18x_read_temp(dev, NULL); ds18x_read_temp(dev, NULL);
sleep(1);
return 0;
} }
TESTS = gs_logger # dmtd_calibration gs_logger random_pulse_test sweep_test temperature_calibration TESTS = gs_logger simple_delay random_pulse_gen
CFLAGS = -I../include CFLAGS = -I../include
LDFLAGS = -L../lib ../lib/libfinedelay.a -lm -letherbone LDFLAGS = -L../lib ../lib/libfinedelay.a -lm
CC=gcc CC=gcc
.PHONY: all .PHONY: all
......
#define _GNU_SOURCE
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <errno.h>
#include <fcntl.h>
#include <stdint.h>
#include <unistd.h>
#include <signal.h>
#include <sys/select.h>
#define FDELAY_INTERNAL // for sysfs_get/set
#include "fdelay_lib.h"
/* Add two timestamps */
static fdelay_time_t ts_add(fdelay_time_t a, fdelay_time_t b)
{
a.frac += b.frac;
if(a.frac >= 4096)
{
a.frac -= 4096;
a.coarse++;
}
a.coarse += b.coarse;
if(a.coarse >= 125000000)
{
a.coarse -= 125000000;
a.utc ++;
}
a.utc += b.utc;
return a;
}
fdelay_time_t ts_sub(fdelay_time_t a, fdelay_time_t b)
{
a.frac -= b.frac;
if(a.frac < 0)
{
a.frac += 4096;
a.coarse--;
}
a.coarse -= b.coarse;
if(a.coarse < 0)
{
a.coarse += 125000000;
a.utc --;
}
a.utc-=b.utc;
return a;
}
int64_t rrand64(int64_t min, int64_t max)
{
int i;
uint64_t tmp = 0;
for(i=0;i<32;i++)
tmp ^= ((uint64_t)random()) << i;
tmp %= (max-min+1);
return min+tmp;
}
int armed = 0;
static int64_t min_gap, max_gap;
static fdelay_time_t t;
void produce_pulses(fdelay_device_t *b)
{
int64_t delta;
fdelay_time_t td;
if(armed && !fdelay_channel_triggered(b, 1))
return ;
delta = rrand64(min_gap, max_gap);
fdelay_get_time(b, &t);
td = fdelay_from_picos(delta);
t = ts_add(t, td);
fdelay_configure_pulse_gen(b, 1, 1, t, min_gap/3, 0, 1);
armed = 1;
}
int main(int argc, char *argv[])
{
if(argc < 4)
{
fprintf(stderr, "usage: %s card_location min_period[us] max_period[us] count\n", argv[0]);
return 0;
}
fdelay_device_t *b = fdelay_create();
if(fdelay_probe(b, argv[1]) < 0)
{
fprintf(stderr, "Probing failed\n");
return 0;
}
fdelay_init(b, 0);
fdelay_configure_trigger(b, 0, 0);
int count = atoi(argv[4]);
min_gap =(int64_t) (atof(argv[2]) * 1000000.0);
max_gap =(int64_t) (atof(argv[3]) * 1000000.0);
int i = 0;
while(count < 0 || (i < count))
{
produce_pulses(b);
i++;
}
printf("generated %d pulses\n", i);
return 0;
}
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