Merge branch 'gmode'

Conflicts: hdl/rtl/fd_acam_timestamp_postprocessor.vhd hdl/rtl/fd_acam_timestamper.vhd hdl/testbench/svec_wr_top/main.sv hdl/top/spec/wr/spec_top.vhd hdl/top/svec/wr/svec_top.ucf hdl/top/svec/wr/svec_top.vhd

Merge branch 'gmode'
Conflicts: hdl/rtl/fd_acam_timestamp_postprocessor.vhd hdl/rtl/fd_acam_timestamper.vhd hdl/testbench/svec_wr_top/main.sv hdl/top/spec/wr/spec_top.vhd hdl/top/svec/wr/svec_top.ucf hdl/top/svec/wr/svec_top.vhd
90db6efe · Tomasz Wlostowski · a7736c9b · a989eb86 · 90db6efe · 90db6efe
Commit 90db6efe authored May 17, 2013 by Tomasz Wlostowski
39 changed files
--- a/hdl/include/acam_model.svh
+++ b/hdl/include/acam_model.svh
@@ -119,11 +119,15 @@ module acam_model
   
 //    
   
-
+   time t_prev;
+   
   always@(posedge DStart) 
     if(PuResN && !StartDis && !start_disabled_int) begin
 //	if(g_verbose)$display("acam::start %d", t);
 	q_start.put(t);
+//        $display("StartEvt %d [delta %d]\n", t, t-t_prev);
+//        t_prev = t;
+        
 	start_disabled_int <= r_StartDisStart;
 	
     end
@@ -185,8 +189,8 @@ module acam_model
 	        else 
 	          break;
 	     end
-	     if(t_stop1 - t_start > 3780)
-	       hit  =  (t_stop1 - t_start) - (128ns/g_rmode_resolution) + rmode_start_offset * 3;
+	     if(t_stop1 - t_start > 8520)
+	       hit  =  (t_stop1 - t_start) - (256ns/g_rmode_resolution) + rmode_start_offset * 3;
 	     else
 	       hit  = t_stop1 - t_start + rmode_start_offset * 3;


--- a/hdl/include/vme64x_bfm/svec_vme_buffers.svh
+++ b/hdl/include/vme64x_bfm/svec_vme_buffers.svh
@@ -67,6 +67,17 @@ module svec_vme_buffers (
   pullup(slave.write_n);
   pulldown(slave.bbsy_n);
   pullup(slave.iackin_n);
+   pullup(slave.iackout_n);
+
+   
+   genvar        i;
+   generate
+      for(i=0;i<6;i++)
+        assign slave.irq_n[i] = (VME_IRQ_n_i[i] ? 1'b0 : 1'bz);
+   endgenerate
+   
+   
+          
   
   assign VME_RST_n_o = slave.rst_n;
   
@@ -93,6 +104,8 @@ module svec_vme_buffers (
   assign slave.dtack_n = VME_DTACK_n_i;
   assign slave.berr_n = ~VME_BERR_i;
   assign slave.retry_n = VME_RETRY_n_i;
+   assign slave.iackout_n = VME_IACKOUT_n_i;
+   
 endmodule



--- a/hdl/include/vme64x_bfm/vme64x_bfm.svh
+++ b/hdl/include/vme64x_bfm/vme64x_bfm.svh
@@ -187,7 +187,7 @@ typedef enum { DONT_CARE = 'h100,
               } vme_addr_size_t;

 typedef enum { 
-               SINGLE = 'h10, CR_CSR='h20, MBLT='h30, BLT='h40, LCK='h50, TwoeVME='h60, TwoeSST='h70 } vme_xfer_type_t;
+               SINGLE = 'h10, CR_CSR='h20, MBLT='h30, BLT='h40, LCK='h50, TwoeVME='h60, TwoeSST='h70, IACK = 'h80 } vme_xfer_type_t;

 typedef enum { D08Byte0='h1, D08Byte1='h2, D08Byte2='h3, D08Byte3='h4, D16Byte01='h5, D16Byte23='h6, D32='h7 } vme_data_type_t ;
   
@@ -207,17 +207,48 @@ class CBusAccessor_VME64x extends CBusAccessor;
   protected bit [4:0] m_ga;
   virtual             IVME64X.tb vme;

+
+   
   function new(virtual IVME64X.tb _vme);
      vme = _vme;
      m_ga = 6'b010111;
      vme.q_ga = m_ga;
-      m_ba = 8'b10000000;
   endfunction // new

+
+
+   protected task acknowledge_irq(int level, ref int vector);
+      `assert_wait(tmo_rws_bus_free, vme.dtack_n && vme.berr_n, 10us)
+      release_bus();
+      #40ns;
+
+      vme.q_addr[3:1] = level;
+      vme.q_iackin_n = 1'b0;
+      vme.q_iack_n = 1'b0;
+      vme.q_am = 'h29;
+      #100ns;
+      
+      vme.q_as_n = 1'b0;
+      #100ns;
+      vme.q_ds_n[0] = 1'b0;
+      
+      `assert_wait(tmo_rws_bus_idle, !vme.dtack_n || !vme.berr_n, 4us)
+      if(!vme.berr_n)
+        $error("[rw_simple_generic]: VME bus error.");
+
+      vector = vme.data;
+      
+      vme.q_iackin_n = 1'b1;
+      vme.q_iack_n = 1'b1;
+      #100ns;
+      release_bus();
+   endtask
+   
+
   protected task set_address(uint64_t addr_in, vme_addr_size_t asize, vme_xfer_type_t xtype);
      bit[63:0] a = addr_in;
      bit [31:0] a_out;
-      
+
     const bit [5:0] am_map [int] = 
                      '{
                        A32 | CR_CSR : 6'b101111,
@@ -248,11 +279,11 @@ class CBusAccessor_VME64x extends CBusAccessor;
        a_out = {8'h0, ~m_ga[4:0], a[18:0]};
      else case(asize)
        A16: 
-          a_out = {16'h0, m_ba[7:3], a[10:2], 2'b00};
+                   a_out = {16'h0, a[15:2], 2'b00};
        A24: 
-          a_out = {8'h0, m_ba[7:3], a[18:2], 2'b00};
+          a_out = {8'h0, a[23:2], 2'b00};
        A32:
-          a_out = {m_ba[7:3], a[26:2], 2'b00};
+          a_out = { a[31:2], 2'b00};
      endcase // case (xtype)

      vme.q_addr[31:2] = a_out[31:2];
@@ -399,7 +430,30 @@ class CBusAccessor_VME64x extends CBusAccessor;
      writem(aa, da, size, result);
   endtask

+   task handle_irqs(ref int done);
+      done = 0;
+      
+      if(vme.irq_n != 7'h7f) 
+        begin
+           int i,level, vector;
+           for(i=6;i>=0;i--)
+             if(!vme.irq_n[i])
+               begin
+                  level = i+1;
+                  break;
+               end
+           $display("vme64x_bfm: got irq level %d", level);
+           
+           acknowledge_irq(level, vector);
+           $display("vme64x_bfm: vector %x", vector);
+           done = 1;
+           
+        end
+   endtask // handle_irqs
   
+
+      
+  
 endclass // CBusAccessor_VME64x

  

--- a/hdl/rtl/fd_acam_timestamp_postprocessor.vhd
+++ b/hdl/rtl/fd_acam_timestamp_postprocessor.vhd
@@ -6,7 +6,7 @@
 -- Author     : Tomasz Wlostowski
 -- Company    : CERN
 -- Created    : 2011-08-29
-- Last update: 2013-02-21
+-- Last update: 2013-02-06
 -- Platform   : FPGA-generic
 -- Standard   : VHDL'93
 -------------------------------------------------------------------------------
@@ -62,20 +62,20 @@ entity fd_acam_timestamp_postprocessor is
    raw_utc_i   : in std_logic_vector(c_TIMESTAMP_UTC_BITS-1 downto 0);

    -- "start number" (value of coarse counter, counting at every start pulse of the
-    -- TDC, i.e. 125 MHz / 16 = 7.8215 MHz)
-    raw_coarse_i : in std_logic_vector(c_TIMESTAMP_COARSE_BITS-4-1 downto 0);
+    -- TDC, i.e. 125 MHz / 32 = 3.90625 MHz)
+    raw_coarse_i : in std_logic_vector(c_TIMESTAMP_COARSE_BITS-5-1 downto 0);

    -- raw fractional timestamp generated by ACAM
    raw_frac_i : in std_logic_vector(22 downto 0);

    -- coarse offset (in 125 MHz clock cycles) from the last ACAM's start pulse to the
    -- input pulse (0..15)
-    raw_start_offset_i : in std_logic_vector(3 downto 0);
+    raw_start_offset_i : in std_logic_vector(4 downto 0);

    -- Offset between the actual timescale and the ACAM fixed start signal generated
    -- by the AD9516 PLL. Used to align the timestamps to the externally
    -- provided time base (e.g. by White Rabbit).
-    acam_subcycle_offset_i : in std_logic_vector(4 downto 0);
+    acam_subcycle_offset_i : in std_logic_vector(5 downto 0);

    ---------------------------------------------------------------------------
    -- Post-processed timestamp. WARNING! DE-NORMALIZED!
@@ -148,7 +148,7 @@ begin  -- behavioral
        pp_pipe(0) <= raw_valid_i;

        post_frac_start_adj         <= signed(raw_frac_i) - signed(regs_i.asor_offset_o);
-        post_tag_coarse(3 downto 0) <= (others => '0');
+        post_tag_coarse(4 downto 0) <= (others => '0');
        post_tag_utc                <= unsigned(raw_utc_i);

        -- pipeline stage 2:
@@ -162,9 +162,9 @@ begin  -- behavioral
        pp_pipe(1) <= pp_pipe(0);

        if (unsigned(raw_start_offset_i) <= unsigned(regs_i.atmcr_c_thr_o)) and (post_frac_start_adj > signed(regs_i.atmcr_f_thr_o)) then
-          post_tag_coarse(post_tag_coarse'left downto 4) <= unsigned(raw_coarse_i) - 1;
+          post_tag_coarse(post_tag_coarse'left downto 5) <= unsigned(raw_coarse_i) - 1;
        else
-          post_tag_coarse(post_tag_coarse'left downto 4) <= unsigned(raw_coarse_i);
+          post_tag_coarse(post_tag_coarse'left downto 5) <= unsigned(raw_coarse_i);
        end if;

        -- Pipeline stage 3:
@@ -212,18 +212,19 @@ begin  -- behavioral
          -- extra coarse counts from ACAM's frac part after rescaling


-          tag_frac_o <= std_logic_vector(post_frac_multiplied_d0(c_SCALER_SHIFT + g_frac_bits-1 downto c_SCALER_SHIFT));
+          tag_frac_o  <= std_logic_vector(post_frac_multiplied_d0(c_SCALER_SHIFT + g_frac_bits-1 downto c_SCALER_SHIFT));
          tag_valid_o <= pp_pipe(4);

        elsif(raw_valid_i = '1') then
          
-          tag_utc_o <= raw_utc_i;
-          tag_coarse_o <= raw_coarse_i & raw_start_offset_i;
-          tag_frac_o <= raw_frac_i(11 downto 0);
-          tag_dbg_raw_o(10 downto 0) <= raw_frac_i(22 downto 12);
-          tag_dbg_raw_o(15 downto 11) <= acam_subcycle_offset_i;
+          tag_utc_o                   <= raw_utc_i;
+          tag_coarse_o                <= raw_coarse_i & raw_start_offset_i;
+          tag_frac_o                  <= raw_frac_i(11 downto 0);
+          tag_dbg_raw_o(10 downto 0)  <= raw_frac_i(22 downto 12);
+          tag_dbg_raw_o(15 downto 11) <= acam_subcycle_offset_i(4 downto 0);
          tag_dbg_raw_o(23 downto 16) <= raw_coarse_i(7 downto 0);
-          tag_dbg_raw_o(31 downto 24) <= raw_utc_i(7 downto 0);
+          tag_dbg_raw_o(30 downto 24) <= raw_utc_i(6 downto 0);
+          tag_dbg_raw_o(31)           <= acam_subcycle_offset_i(5);

          tag_valid_o <= '1';
        else

--- a/hdl/rtl/fd_acam_timestamper.vhd
+++ b/hdl/rtl/fd_acam_timestamper.vhd
@@ -6,7 +6,7 @@
 -- Author     : Tomasz Wlostowski
 -- Company    : CERN
 -- Created    : 2011-08-24
-- Last update: 2013-02-21
+-- Last update: 2013-02-12
 -- Platform   : FPGA-generic
 -- Standard   : VHDL'93
 -------------------------------------------------------------------------------
@@ -165,10 +165,10 @@ architecture behavioral of fd_acam_timestamper is
      rst_n_i                : in  std_logic;
      raw_valid_i            : in  std_logic;
      raw_utc_i              : in  std_logic_vector(c_TIMESTAMP_UTC_BITS-1 downto 0);
-      raw_coarse_i           : in  std_logic_vector(c_TIMESTAMP_COARSE_BITS-4-1 downto 0);
+      raw_coarse_i           : in  std_logic_vector(c_TIMESTAMP_COARSE_BITS-5-1 downto 0);
      raw_frac_i             : in  std_logic_vector(22 downto 0);
-      raw_start_offset_i     : in  std_logic_vector(3 downto 0);
-      acam_subcycle_offset_i : in  std_logic_vector(4 downto 0);
+      raw_start_offset_i     : in  std_logic_vector(4 downto 0);
+      acam_subcycle_offset_i : in  std_logic_vector(5 downto 0);
      tag_valid_o            : out std_logic;
      tag_utc_o              : out std_logic_vector(c_TIMESTAMP_UTC_BITS-1 downto 0);
      tag_coarse_o           : out std_logic_vector(c_TIMESTAMP_COARSE_BITS-1 downto 0);
@@ -222,18 +222,18 @@ architecture behavioral of fd_acam_timestamper is
  signal trig_pulse : std_logic;

  -- counters (internal time base)
-  signal start_count     : unsigned(3 downto 0);
-  signal coarse_count    : unsigned(c_TIMESTAMP_COARSE_BITS-4-1 downto 0);
+  signal start_count     : unsigned(4 downto 0);
+  signal coarse_count    : unsigned(c_TIMESTAMP_COARSE_BITS-5-1 downto 0);
  signal utc_count       : unsigned(c_TIMESTAMP_UTC_BITS-1 downto 0);
-  signal subcycle_offset : signed(4 downto 0);
+  signal subcycle_offset : signed(5 downto 0);

  signal gcr_input_en_d0 : std_logic;

  -- raw (unprocessed) time tag
  signal raw_tag_valid        : std_logic;
-  signal raw_tag_coarse       : unsigned(c_TIMESTAMP_COARSE_BITS-4-1 downto 0);
+  signal raw_tag_coarse       : unsigned(c_TIMESTAMP_COARSE_BITS-5-1 downto 0);
  signal raw_tag_frac         : signed(22 downto 0);
-  signal raw_tag_start_offset : unsigned(3 downto 0);
+  signal raw_tag_start_offset : unsigned(4 downto 0);
  signal raw_tag_utc          : unsigned(c_TIMESTAMP_UTC_BITS-1 downto 0);

  signal width_check_sreg : std_logic_vector(g_min_pulse_width-2 downto 0);
@@ -401,11 +401,14 @@ begin  -- behave
        else
          -- Enable the start input at proper moment to ensure that the 7.125 MHz
          -- "start clock" cycle is not cut.
-          if(start_count = x"e") then
+          if(start_count = x"8") then
            -- advance the start OK shift register with another one.
            start_ok_sreg    <= start_ok_sreg(start_ok_sreg'left-1 downto 0) & '1';
+            acam_start_dis_o <= '1';
+          elsif (start_count = x"18") then
            acam_start_dis_o <= '0';
          end if;
+          
        end if;
      end if;
    end if;
@@ -440,6 +443,8 @@ begin  -- behave
    end if;
  end process;

+
+
  -- Process: p_sync_acam_ef
  -- Input: acam_ef_i
  -- Output: acam_ef_d1
@@ -457,6 +462,17 @@ begin  -- behave
 -- Time Base Counters
 -------------------------------------------------------------------------------  

+  p_gen_start_mask : process(clk_ref_i)
+  begin
+    if rising_edge(clk_ref_i) then
+      if rst_n_i = '0' then
+        start_mask <= '0';
+      elsif(tdc_start_d(1) = '1' and tdc_start_d(2) = '0') then
+        start_mask <= not start_mask;
+      end if;
+    end if;
+  end process;
+
 -- Start counter: counts the number of clk_ref_i cycles from the last TDC start
 -- event.

@@ -476,18 +492,18 @@ begin  -- behave
        -- between the current start count and the LSBs of the new time value
        -- and correct the timestamps later on.
        if(csync_p1_i = '1') then
-          subcycle_offset <= signed('0' & csync_coarse_i(3 downto 0)) - signed('0' & start_count) - 1;
+          subcycle_offset <= signed('0' & csync_coarse_i(4 downto 0)) - signed('0' & start_count) - 1;
        end if;

        -- Rising edge on TDC_START? Resynchronize the counter, to go to zero
        -- right after the edge.
-        if(tdc_start_d(1) = '1' and tdc_start_d(2) = '0') then
-          start_count    <= x"2";
+        if(tdc_start_d(1) = '1' and tdc_start_d(2) = '0' and start_mask = '0') then
+          start_count    <= to_unsigned(2, 5);
          advance_coarse <= '0';
        else
          -- Start cycle expired - advance the 128 ns x counter. We do that one
          -- cycle in advance using a register to relax the P&R timing.
-          if(start_count = x"e") then
+          if(start_count = x"1e") then
            advance_coarse <= '1';
          else
            advance_coarse <= '0';
@@ -511,13 +527,13 @@ begin  -- behave
        -- overflow of start_count.
        if(csync_p1_i = '1') then
          if(advance_coarse = '1') then
-            coarse_count <= unsigned(csync_coarse_i(27 downto 4)) + 1;
+            coarse_count <= unsigned(csync_coarse_i(27 downto 5)) + 1;
          else
-            coarse_count <= unsigned(csync_coarse_i(27 downto 4));
+            coarse_count <= unsigned(csync_coarse_i(27 downto 5));
          end if;
        elsif(advance_coarse = '1') then
          -- well, just boringly count up
-          if(coarse_count = (g_clk_ref_freq / 16) - 1) then
+          if(coarse_count = (g_clk_ref_freq / 32) - 1) then
            coarse_count <= (others => '0');
          else
            coarse_count <= coarse_count + 1;
@@ -537,14 +553,14 @@ begin  -- behave
        utc_count <= (others => '0');
      else
        if(csync_p1_i = '1') then
-          if(advance_coarse = '1' and coarse_count = (g_clk_ref_freq / 16) -1) then
+          if(advance_coarse = '1' and coarse_count = (g_clk_ref_freq / 32) -1) then
            -- I hate special cases!
            utc_count <= unsigned(csync_utc_i) + 1;
          else
            utc_count <= unsigned(csync_utc_i);
          end if;
          
-        elsif(advance_coarse = '1' and coarse_count = (g_clk_ref_freq / 16) - 1) then
+        elsif(advance_coarse = '1' and coarse_count = (g_clk_ref_freq / 32) - 1) then
          utc_count <= utc_count + 1;
        end if;

@@ -721,7 +737,8 @@ begin  -- behave
          when RMODE_READ =>

 -- store the fine tag
-            raw_tag_frac <= signed(acam_d_i(raw_tag_frac'left downto 0));
+            raw_tag_frac(21 downto 0) <= signed(acam_d_i(21 downto 0));
+            raw_tag_frac(22) <= '0';


            -- check if the FIFO has become empty after the readout. If it didn't, the TDC

--- a/hdl/rtl/fd_channel_wbgen2_pkg.vhd
+++ b/hdl/rtl/fd_channel_wbgen2_pkg.vhd
@@ -3,7 +3,7 @@
 ---------------------------------------------------------------------------------------
 -- File           : fd_channel_wbgen2_pkg.vhd
 -- Author         : auto-generated by wbgen2 from fd_channel_wishbone_slave.wb
-- Created        : Mon Jun  4 13:42:20 2012
+-- Created        : Fri Feb 15 12:07:17 2013
 -- Standard       : VHDL'87
 ---------------------------------------------------------------------------------------
 -- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE fd_channel_wishbone_slave.wb

--- a/hdl/rtl/fd_channel_wishbone_slave.vhd
+++ b/hdl/rtl/fd_channel_wishbone_slave.vhd
@@ -3,7 +3,7 @@
 ---------------------------------------------------------------------------------------
 -- File           : fd_channel_wishbone_slave.vhd
 -- Author         : auto-generated by wbgen2 from fd_channel_wishbone_slave.wb
-- Created        : Mon Jun  4 13:42:20 2012
+-- Created        : Fri Feb 15 12:07:17 2013
 -- Standard       : VHDL'87
 ---------------------------------------------------------------------------------------
 -- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE fd_channel_wishbone_slave.wb
@@ -161,11 +161,11 @@ begin
            end if;
            rddata_reg(0) <= fd_channel_dcr_enable_int;
            rddata_reg(1) <= fd_channel_dcr_mode_int;
-            rddata_reg(2) <= 'X';
+            rddata_reg(2) <= '0';
            rddata_reg(3) <= fd_channel_dcr_pg_trig_sync1;
-            rddata_reg(4) <= 'X';
+            rddata_reg(4) <= '0';
            rddata_reg(5) <= fd_channel_dcr_upd_done_sync1;
-            rddata_reg(6) <= 'X';
+            rddata_reg(6) <= '0';
            rddata_reg(7) <= fd_channel_dcr_no_fine_int;
            rddata_reg(8) <= fd_channel_dcr_force_hi_int;
            rddata_reg(9) <= 'X';

--- a/hdl/rtl/fd_main_wbgen2_pkg.vhd
+++ b/hdl/rtl/fd_main_wbgen2_pkg.vhd
@@ -3,7 +3,7 @@
 ---------------------------------------------------------------------------------------
 -- File           : fd_main_wbgen2_pkg.vhd
 -- Author         : auto-generated by wbgen2 from fd_main_wishbone_slave.wb
-- Created        : Fri Dec 14 11:28:02 2012
+-- Created        : Fri Feb 15 12:07:16 2013
 -- Standard       : VHDL'87
 ---------------------------------------------------------------------------------------
 -- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE fd_main_wishbone_slave.wb
@@ -130,7 +130,7 @@ package fd_main_wbgen2_pkg is
      calr_cal_dmtd_o                          : std_logic;
      calr_psel_o                              : std_logic_vector(3 downto 0);
      adsfr_o                                  : std_logic_vector(17 downto 0);
-      atmcr_c_thr_o                            : std_logic_vector(3 downto 0);
+      atmcr_c_thr_o                            : std_logic_vector(7 downto 0);
      atmcr_f_thr_o                            : std_logic_vector(22 downto 0);
      asor_offset_o                            : std_logic_vector(22 downto 0);
      iepd_rst_stat_o                          : std_logic;

--- a/hdl/rtl/fd_main_wishbone_slave.vhd
+++ b/hdl/rtl/fd_main_wishbone_slave.vhd
@@ -3,7 +3,7 @@
 ---------------------------------------------------------------------------------------
 -- File           : fd_main_wishbone_slave.vhd
 -- Author         : auto-generated by wbgen2 from fd_main_wishbone_slave.wb
-- Created        : Fri Dec 14 11:28:02 2012
+-- Created        : Fri Feb 15 12:07:16 2013
 -- Standard       : VHDL'87
 ---------------------------------------------------------------------------------------
 -- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE fd_main_wishbone_slave.wb
@@ -159,7 +159,7 @@ signal fd_main_adsfr_swb_delay                  : std_logic      ;
 signal fd_main_adsfr_swb_s0                     : std_logic      ;
 signal fd_main_adsfr_swb_s1                     : std_logic      ;
 signal fd_main_adsfr_swb_s2                     : std_logic      ;
-signal fd_main_atmcr_c_thr_int                  : std_logic_vector(3 downto 0);
+signal fd_main_atmcr_c_thr_int                  : std_logic_vector(7 downto 0);
 signal fd_main_atmcr_c_thr_swb                  : std_logic      ;
 signal fd_main_atmcr_c_thr_swb_delay            : std_logic      ;
 signal fd_main_atmcr_c_thr_swb_s0               : std_logic      ;
@@ -332,7 +332,7 @@ begin
      fd_main_adsfr_int <= "000000000000000000";
      fd_main_adsfr_swb <= '0';
      fd_main_adsfr_swb_delay <= '0';
-      fd_main_atmcr_c_thr_int <= "0000";
+      fd_main_atmcr_c_thr_int <= "00000000";
      fd_main_atmcr_c_thr_swb <= '0';
      fd_main_atmcr_c_thr_swb_delay <= '0';
      fd_main_atmcr_f_thr_int <= "00000000000000000000000";
@@ -373,8 +373,8 @@ begin
      fd_main_tsbir_timeout_int <= "0000000000";
      fd_main_tsbir_threshold_int <= "000000000000";
      fid_read_ack_o <= '0';
-      fd_main_i2cr_scl_out_int <= '0';
-      fd_main_i2cr_sda_out_int <= '0';
+      fd_main_i2cr_scl_out_int <= '1';
+      fd_main_i2cr_sda_out_int <= '1';
      fd_main_tder2_pelt_drive_int <= "00000000000000000000000000000000";
      fd_main_tsbr_advance_adv_int <= '0';
      eic_idr_write_int <= '0';
@@ -595,8 +595,8 @@ begin
            rddata_reg(3) <= regs_i.tcr_wr_present_i;
            rddata_reg(4) <= regs_i.tcr_wr_ready_i;
            rddata_reg(5) <= regs_i.tcr_wr_link_i;
-            rddata_reg(6) <= 'X';
-            rddata_reg(7) <= 'X';
+            rddata_reg(6) <= '0';
+            rddata_reg(7) <= '0';
            rddata_reg(8) <= 'X';
            rddata_reg(9) <= 'X';
            rddata_reg(10) <= 'X';
@@ -736,14 +736,14 @@ begin
              fd_main_tdcsr_alutrig_int <= wrdata_reg(7);
              fd_main_tdcsr_alutrig_int_delay <= wrdata_reg(7);
            end if;
-            rddata_reg(0) <= 'X';
-            rddata_reg(1) <= 'X';
+            rddata_reg(0) <= '0';
+            rddata_reg(1) <= '0';
            rddata_reg(2) <= fd_main_tdcsr_empty_sync1;
-            rddata_reg(3) <= 'X';
-            rddata_reg(4) <= 'X';
-            rddata_reg(5) <= 'X';
-            rddata_reg(6) <= 'X';
-            rddata_reg(7) <= 'X';
+            rddata_reg(3) <= '0';
+            rddata_reg(4) <= '0';
+            rddata_reg(5) <= '0';
+            rddata_reg(6) <= '0';
+            rddata_reg(7) <= '0';
            rddata_reg(8) <= 'X';
            rddata_reg(9) <= 'X';
            rddata_reg(10) <= 'X';
@@ -780,7 +780,7 @@ begin
              fd_main_calr_psel_swb <= '1';
              fd_main_calr_psel_swb_delay <= '1';
            end if;
-            rddata_reg(0) <= 'X';
+            rddata_reg(0) <= '0';
            rddata_reg(1) <= fd_main_calr_cal_pps_int;
            rddata_reg(2) <= fd_main_calr_cal_dmtd_int;
            rddata_reg(6 downto 3) <= fd_main_calr_psel_int;
@@ -852,19 +852,15 @@ begin
            ack_in_progress <= '1';
          when "001101" => 
            if (wb_we_i = '1') then
-              fd_main_atmcr_c_thr_int <= wrdata_reg(3 downto 0);
+              fd_main_atmcr_c_thr_int <= wrdata_reg(7 downto 0);
              fd_main_atmcr_c_thr_swb <= '1';
              fd_main_atmcr_c_thr_swb_delay <= '1';
-              fd_main_atmcr_f_thr_int <= wrdata_reg(26 downto 4);
+              fd_main_atmcr_f_thr_int <= wrdata_reg(30 downto 8);
              fd_main_atmcr_f_thr_swb <= '1';
              fd_main_atmcr_f_thr_swb_delay <= '1';
            end if;
-            rddata_reg(3 downto 0) <= fd_main_atmcr_c_thr_int;
-            rddata_reg(26 downto 4) <= fd_main_atmcr_f_thr_int;
-            rddata_reg(27) <= 'X';
-            rddata_reg(28) <= 'X';
-            rddata_reg(29) <= 'X';
-            rddata_reg(30) <= 'X';
+            rddata_reg(7 downto 0) <= fd_main_atmcr_c_thr_int;
+            rddata_reg(30 downto 8) <= fd_main_atmcr_f_thr_int;
            rddata_reg(31) <= 'X';
            ack_sreg(3) <= '1';
            ack_in_progress <= '1';
@@ -911,7 +907,7 @@ begin
              fd_main_iepd_rst_stat_int <= wrdata_reg(0);
              fd_main_iepd_rst_stat_int_delay <= wrdata_reg(0);
            end if;
-            rddata_reg(0) <= 'X';
+            rddata_reg(0) <= '0';
            if (wb_we_i = '0') then
              fd_main_iepd_pdelay_lwb <= '1';
              fd_main_iepd_pdelay_lwb_delay <= '1';
@@ -957,7 +953,7 @@ begin
            rddata_reg(26) <= fd_main_scr_sel_gpio_int;
            rddata_reg(27) <= regs_i.scr_ready_i;
            rddata_reg(28) <= fd_main_scr_cpol_int;
-            rddata_reg(29) <= 'X';
+            rddata_reg(29) <= '0';
            rddata_reg(30) <= 'X';
            rddata_reg(31) <= 'X';
            ack_sreg(2) <= '1';
@@ -985,8 +981,8 @@ begin
            end if;
            rddata_reg(4 downto 0) <= fd_main_tsbcr_chan_mask_int;
            rddata_reg(5) <= fd_main_tsbcr_enable_int;
-            rddata_reg(6) <= 'X';
-            rddata_reg(7) <= 'X';
+            rddata_reg(6) <= '0';
+            rddata_reg(7) <= '0';
            rddata_reg(8) <= regs_i.tsbcr_full_i;
            rddata_reg(9) <= regs_i.tsbcr_empty_i;
            tsbcr_read_ack_o <= '1';
@@ -1139,7 +1135,7 @@ begin
            if (wb_we_i = '1') then
              fd_main_tsbr_advance_adv_int <= wrdata_reg(0);
            end if;
-            rddata_reg(0) <= 'X';
+            rddata_reg(0) <= '0';
            rddata_reg(0) <= 'X';
            rddata_reg(1) <= 'X';
            rddata_reg(2) <= 'X';
@@ -1376,7 +1372,7 @@ begin
  
  
 -- PLL Locked
-- Mezzanice Present
+-- Mezzanine Present
 -- DMTD Clock Status
 -- WR Timing Enable
  regs_o.tcr_wr_enable_o <= fd_main_tcr_wr_enable_int;
@@ -1478,8 +1474,8 @@ begin
  end process;
  
  
-- Reference clock cycles
-- asynchronous std_logic_vector register : Reference clock cycles (type RW/WO, clk_ref_i <-> clk_sys_i)
+-- Reference clock cycles (0...124999999)
+-- asynchronous std_logic_vector register : Reference clock cycles (0...124999999) (type RW/WO, clk_ref_i <-> clk_sys_i)
  process (clk_ref_i, rst_n_i)
  begin
    if (rst_n_i = '0') then 
@@ -1538,7 +1534,7 @@ begin
  end process;
  
  
-- Start TDC write
+-- Write to TDC
  process (clk_ref_i, rst_n_i)
  begin
    if (rst_n_i = '0') then 
@@ -1555,7 +1551,7 @@ begin
  end process;
  
  
-- Start TDC read
+-- Read from TDC
  process (clk_ref_i, rst_n_i)
  begin
    if (rst_n_i = '0') then 
@@ -1586,7 +1582,7 @@ begin
  end process;
  
  
-- Start enable
+-- Stop enable
  process (clk_ref_i, rst_n_i)
  begin
    if (rst_n_i = '0') then 
@@ -1620,7 +1616,7 @@ begin
  end process;
  
  
-- Stop enable
+-- Start enable
  process (clk_ref_i, rst_n_i)
  begin
    if (rst_n_i = '0') then 
@@ -1654,7 +1650,7 @@ begin
  end process;
  
  
-- write 1: Pulse the Alutrigger line
+-- Pulse <code>Alutrigger</code> line
  process (clk_ref_i, rst_n_i)
  begin
    if (rst_n_i = '0') then 
@@ -1671,7 +1667,7 @@ begin
  end process;
  
  
-- Triggers calibration pulses
+-- Generate calibration pulses (type 1 calibration)
  process (clk_ref_i, rst_n_i)
  begin
    if (rst_n_i = '0') then 
@@ -1704,10 +1700,10 @@ begin
  end process;
  
  
-- Produce DDMTD calibration pattern
+-- Produce DDMTD calibration pattern (type 2 calibration)
  regs_o.calr_cal_dmtd_o <= fd_main_calr_cal_dmtd_int;
-- Enable pulse generation
-- asynchronous std_logic_vector register : Enable pulse generation (type RW/RO, clk_ref_i <-> clk_sys_i)
+-- Calibration pulse output select/mask
+-- asynchronous std_logic_vector register : Calibration pulse output select/mask (type RW/RO, clk_ref_i <-> clk_sys_i)
  process (clk_ref_i, rst_n_i)
  begin
    if (rst_n_i = '0') then 
@@ -1758,7 +1754,7 @@ begin
      fd_main_atmcr_c_thr_swb_s0 <= '0';
      fd_main_atmcr_c_thr_swb_s1 <= '0';
      fd_main_atmcr_c_thr_swb_s2 <= '0';
-      regs_o.atmcr_c_thr_o <= "0000";
+      regs_o.atmcr_c_thr_o <= "00000000";
    elsif rising_edge(clk_ref_i) then
      fd_main_atmcr_c_thr_swb_s0 <= fd_main_atmcr_c_thr_swb;
      fd_main_atmcr_c_thr_swb_s1 <= fd_main_atmcr_c_thr_swb_s0;

--- a/hdl/rtl/fd_main_wishbone_slave.wb
+++ b/hdl/rtl/fd_main_wishbone_slave.wb
@@ -515,7 +515,7 @@ peripheral {
      field {
         name = "Wraparound Coarse Threshold";
         prefix = "C_THR";
-         size = 4;
+         size = 8;
         type = SLV;
         clock = "clk_ref_i";
         access_bus = READ_WRITE;

--- a/hdl/rtl/fine_delay_pkg.vhd
+++ b/hdl/rtl/fine_delay_pkg.vhd
@@ -6,7 +6,7 @@
 -- Author     : Tomasz Wlostowski
 -- Company    : CERN
 -- Created    : 2011-08-24
-- Last update: 2012-11-22
+-- Last update: 2013-04-30
 -- Platform   : FPGA-generic
 -- Standard   : VHDL'93
 -------------------------------------------------------------------------------
@@ -76,7 +76,7 @@ package fine_delay_pkg is
  constant c_FD_DMTD_CALIBRATION_PERIOD : integer := 144;

  -- Calibration pulse width
-  constant c_FD_DMTD_CALIBRATION_PWIDTH : integer := 10;
+  constant c_FD_DMTD_CALIBRATION_PWIDTH : integer := 32;

  constant c_FD_SDB_DEVICE : t_sdb_device := (
    abi_class     => x"0000",              -- undocumented device
@@ -90,7 +90,7 @@ package fine_delay_pkg is
      product     => (
        vendor_id => x"000000000000CE42",  -- CERN
        device_id => x"f19ede1a",
-        version   => x"00000001",
+        version   => x"00000003",
        date      => x"20120809",
        name      => "Fine-Delay-Core    ")));


--- a/hdl/syn/svec/wr/Manifest.py
+++ b/hdl/syn/svec/wr/Manifest.py
@@ -9,5 +9,5 @@ syn_package = "fgg900"
 syn_top = "svec_top"
 syn_project = "svec_fine_delay.xise"

-files = [ "wrc.ram" ]
+files = [ "wrc-release.ram" ]
 modules = { "local" : [ "../../../top/svec/wr", "../../../platform" ] }
--- a/hdl/syn/svec/wr/svec_fine_delay.xise
+++ b/hdl/syn/svec/wr/svec_fine_delay.xise
--- a/hdl/testbench/svec_wr_top/fdelay_board.svh
+++ b/hdl/testbench/svec_wr_top/fdelay_board.svh
@@ -197,21 +197,28 @@ module fdelay_board (
      );

   genvar     gg;
+
+   function bit[9:0] reverse_bits (bit [9:0] x);
+      reg [9:0] tmp;
+      int       i;
+
+      for(i=0;i<10;i++)
+        tmp[9-i]=x[i];
+      
+      
+      return tmp;
+   endfunction // reverse_bits
   
-   generate
-      for(gg=0;gg<4;gg++)
-        begin
-//           assign out_o[gg] = fmc.delay_pulse[gg];
+
+      
           
-           mc100ep195
-             U_delay_line(
-                 .len(fmc.delay_len[gg]),
-                 .i(fmc.delay_pulse[gg]),
-                 .delay(fmc.delay_val),
-                 .o(out_o[gg])
-                 ); 
-               end
-      endgenerate
+   mc100ep195
+    U_delay_line0(
+                  .len(fmc.delay_len[0]),
+                  .i(fmc.delay_pulse[0]),
+                  .delay(reverse_bits(fmc.delay_val)),
+                  .o(out_o[0]));
+   
   
 endmodule // main


--- a/hdl/testbench/svec_wr_top/main.sv
+++ b/hdl/testbench/svec_wr_top/main.sv
@@ -3,7 +3,6 @@

 `include "fdelay_board.svh"
 `include "simdrv_fine_delay.svh"
-`include "ideal_timestamper.svh"


 module delay_meas(input enable, input a, input b);
@@ -26,7 +25,6 @@ module delay_meas(input enable, input a, input b);
   end
   
   
-   

   initial forever begin
      wait(tag_a.num() > 0 && tag_b.num() > 0);
@@ -45,6 +43,43 @@ module delay_meas(input enable, input a, input b);
   end
 endmodule // delay_meas

+module period_meas(input enable, input a);
+
+   mailbox tag_a, tag_b;
+
+   event   q_notempty;
+   
+   initial begin
+      tag_a = new(1024);
+   end
+
+   time prev_a = 0;
+   
+   
+   always@(posedge a) begin
+      if(prev_a > 0)begin
+         if(enable) tag_a.put($time - prev_a);
+      end else
+        prev_a=$time;
+   end
+   
+   
+   
+
+   initial forever begin
+      wait(tag_a.num() > 0);
+      
+      while(tag_a.num() > 0)
+        begin
+           time delta;
+         
+           tag_a.get(delta);
+           
+           $display("Delay: %.3f ns",  real'(delta) / real'(1ns) );
+        end
+   end
+endmodule // delay_meas
+


 module main;
@@ -87,14 +122,11 @@ module main;
   wire [3:0] out0, out1;
   reg        pulse_enable = 0;
   
-   
   random_pulse_gen
     #(
-       .g_pulse_width  (100ns),
+       .g_pulse_width  (50ns),
       .g_min_spacing  (1001ns),
-       .g_max_spacing  (1001.1ns),
-       .g_repetition(1),
-       .g_burst_spacing(3ns))
+       .g_max_spacing  (1001.1ns))
   U_Gen0
     (
      .enable_i(pulse_enable),
@@ -108,15 +140,12 @@ module main;
      .fmc(I_fmc0.board)
      );

-  delay_meas U_DMeas0 (pulse_enable, trig0, out0[0]);
+   reg out0_delayed=0;

-   ideal_timestamper tsu_in(
-                            .clk_ref_i(I_fmc0.clk_ref_p),
-                            .rst_n_i(rst_n),
-                            .enable_i(1'b1),
-                            .trig_a_i(trig0),
-                            .csync_p1_i(1'b0));
+   always@(out0[0]) out0_delayed <= #10ps out0[0];
+   
   
+  period_meas U_DMeas0 (pulse_enable, out0[0]);
   
   task automatic init_vme64x_core(ref CBusAccessor_VME64x acc);
      /* map func0 to 0x80000000, A32 */
@@ -132,7 +161,7 @@ module main;
   initial begin
      CBusAccessor_VME64x acc = new(VME.master);
      CBusAccessor acc_casted = CBusAccessor'(acc);
-      Timestamp dly;
+      Timestamp dly, t_start;
      
      CSimDrv_FineDelay drv0;
      uint64_t d;
@@ -141,70 +170,52 @@ module main;

      init_vme64x_core(acc);
      acc_casted.set_default_xfer_size(A32|SINGLE|D32);
+
+//      acc.read('h20000, d, D32|A32|SINGLE);
+//      $display("Vector 1 = %x", d);
+      acc.read('h80030080, d, D32|A32|SINGLE);
+      $display("Vector 0 = %x", d);
+      acc.read('h80030084, d, D32|A32|SINGLE);
+      $display("Vector 1 = %x", d);
+      acc.read('h80030088, d, D32|A32|SINGLE);
+      $display("Vector 2 = %x", d);
+
+      $stop;
      
-      drv0 = new(acc, 'h10000);
+      
+      drv0 = new(acc, 'h80010000);
      drv0.init();

-      dly=new;
-      dly.from_ps(800000);
-      drv0.config_output(0, CSimDrv_FineDelay::DELAY, 1, dly, 250000);
+      t_start=new;    
+      drv0.get_time(t_start);
+      t_start.coarse += 2000;
+      
+      drv0.config_output(0, CSimDrv_FineDelay::PULSE_GEN, 1, t_start, 200000, 1001000, -1);
      
      $display("Init done");

+      
      pulse_enable = 1;

-   
-
+/* -----\/----- EXCLUDED -----\/-----
      forever begin
-         //       drv0.rbuf_update();
-         //         if(drv0.poll())
-         Timestamp ts, ts_ref;
-         //              ts = drv0.get();
+         drv0.rbuf_update();

-         while(ts_q_fd0.size() == 0)
-           #1ns;
-         
-         ts = ts_q_fd0.pop_front();
-         $display("TS: %.3f", ts.flatten());
-         
-         while(tsu_in.poll())
+         if(drv0.poll())
           begin
-              ts_ref = tsu_in.get();
+              Timestamp ts;
+              ts = drv0.get();
+             // $display("TS: %.3f", ts.flatten());
           end
-
-         $display("TS: %.3f, ref: %.3f, delta: %.3f", ts.flatten(), ts_ref.flatten(), ts_ref.flatten() - ts.flatten());
-         
-         
+         #1us;
      end
+ -----/\----- EXCLUDED -----/\----- */
   end // initial begin
-
-      Timestamp ts_q_fd0[$];
   

-
-      always@(posedge DUT.dcm0_clk_ref_0)
-        begin
-           if(DUT.U_FineDelay_Core0.tag_valid)
-             begin
-                Timestamp tr;
-                tr = new;
-                
-                $display("Got a tag");
-                tr.coarse = DUT.U_FineDelay_Core0.tag_coarse;
-                tr.utc = 0;
-                tr.frac = DUT.U_FineDelay_Core0.tag_frac;
-
-                ts_q_fd0.push_back(tr);
-                
-                
-                
-             end
-           
-        end
-
-   
  
 endmodule // main



+
--- a/hdl/testbench/svec_wr_top/simdrv_fine_delay.svh
+++ b/hdl/testbench/svec_wr_top/simdrv_fine_delay.svh
@@ -177,7 +177,7 @@ class CSimDrv_FineDelay;

      base = 'h100 + 'h100 * channel;
      
-      writel(base + `ADDR_FD_FRR, 800);
+      writel(base + `ADDR_FD_FRR, 865);
      writel(base + `ADDR_FD_U_STARTH, t_start.utc >> 32);
      writel(base + `ADDR_FD_U_STARTL, t_start.utc & 'hffffffff);
      writel(base + `ADDR_FD_C_START, t_start.coarse);

--- a/hdl/testbench/svec_wr_top/wave.do
+++ b/hdl/testbench/svec_wr_top/wave.do
 onerror {resume}
 quietly WaveActivateNextPane {} 0
-add wave -noupdate /main/DUT/g_with_wr_phy
-add wave -noupdate /main/DUT/g_simulation
-add wave -noupdate /main/DUT/clk_20m_vcxo_i
-add wave -noupdate /main/DUT/clk_125m_pllref_p_i
-add wave -noupdate /main/DUT/clk_125m_pllref_n_i
-add wave -noupdate /main/DUT/clk_125m_gtp_p_i
-add wave -noupdate /main/DUT/clk_125m_gtp_n_i
-add wave -noupdate /main/DUT/rst_n_i
-add wave -noupdate /main/DUT/VME_AS_n_i
-add wave -noupdate /main/DUT/VME_RST_n_i
-add wave -noupdate /main/DUT/VME_WRITE_n_i
-add wave -noupdate /main/DUT/VME_AM_i
-add wave -noupdate /main/DUT/VME_DS_n_i
-add wave -noupdate /main/DUT/VME_GA_i
-add wave -noupdate /main/DUT/VME_BERR_o
-add wave -noupdate /main/DUT/VME_DTACK_n_o
-add wave -noupdate /main/DUT/VME_RETRY_n_o
-add wave -noupdate /main/DUT/VME_RETRY_OE_o
-add wave -noupdate /main/DUT/VME_LWORD_n_b
-add wave -noupdate /main/DUT/VME_ADDR_b
-add wave -noupdate /main/DUT/VME_DATA_b
-add wave -noupdate /main/DUT/VME_BBSY_n_i
-add wave -noupdate /main/DUT/VME_IRQ_n_o
-add wave -noupdate /main/DUT/VME_IACK_n_i
-add wave -noupdate /main/DUT/VME_IACKIN_n_i
-add wave -noupdate /main/DUT/VME_IACKOUT_n_o
-add wave -noupdate /main/DUT/VME_DTACK_OE_o
-add wave -noupdate /main/DUT/VME_DATA_DIR_o
-add wave -noupdate /main/DUT/VME_DATA_OE_N_o
-add wave -noupdate /main/DUT/VME_ADDR_DIR_o
-add wave -noupdate /main/DUT/VME_ADDR_OE_N_o
-add wave -noupdate /main/DUT/sfp_txp_o
-add wave -noupdate /main/DUT/sfp_txn_o
-add wave -noupdate /main/DUT/sfp_rxp_i
-add wave -noupdate /main/DUT/sfp_rxn_i
-add wave -noupdate /main/DUT/sfp_mod_def0_b
-add wave -noupdate /main/DUT/sfp_mod_def1_b
-add wave -noupdate /main/DUT/sfp_mod_def2_b
-add wave -noupdate /main/DUT/sfp_rate_select_b
-add wave -noupdate /main/DUT/sfp_tx_fault_i
-add wave -noupdate /main/DUT/sfp_tx_disable_o
-add wave -noupdate /main/DUT/sfp_los_i
-add wave -noupdate /main/DUT/fmc0_prsntm2c_n_i
-add wave -noupdate /main/DUT/fmc1_prsntm2c_n_i
-add wave -noupdate /main/DUT/fmc0_scl_b
-add wave -noupdate /main/DUT/fmc0_sda_b
-add wave -noupdate /main/DUT/fmc1_scl_b
-add wave -noupdate /main/DUT/fmc1_sda_b
-add wave -noupdate /main/DUT/pll20dac_din_o
-add wave -noupdate /main/DUT/pll20dac_sclk_o
-add wave -noupdate /main/DUT/pll20dac_sync_n_o
-add wave -noupdate /main/DUT/pll25dac_din_o
-add wave -noupdate /main/DUT/pll25dac_sclk_o
-add wave -noupdate /main/DUT/pll25dac_sync_n_o
-add wave -noupdate /main/DUT/tempid_dq_b
-add wave -noupdate /main/DUT/fp_ledn_o
-add wave -noupdate /main/DUT/fd0_tdc_start_p_i
-add wave -noupdate /main/DUT/fd0_tdc_start_n_i
-add wave -noupdate /main/DUT/fd0_clk_ref_p_i
-add wave -noupdate /main/DUT/fd0_clk_ref_n_i
-add wave -noupdate /main/DUT/fd0_trig_a_i
-add wave -noupdate /main/DUT/fd0_tdc_cal_pulse_o
-add wave -noupdate /main/DUT/fd0_tdc_d_b
-add wave -noupdate /main/DUT/fd0_tdc_emptyf_i
-add wave -noupdate /main/DUT/fd0_tdc_alutrigger_o
-add wave -noupdate /main/DUT/fd0_tdc_wr_n_o
-add wave -noupdate /main/DUT/fd0_tdc_rd_n_o
-add wave -noupdate /main/DUT/fd0_tdc_oe_n_o
-add wave -noupdate /main/DUT/fd0_led_trig_o
-add wave -noupdate /main/DUT/fd0_tdc_start_dis_o
-add wave -noupdate /main/DUT/fd0_tdc_stop_dis_o
-add wave -noupdate /main/DUT/fd0_spi_cs_dac_n_o
-add wave -noupdate /main/DUT/fd0_spi_cs_pll_n_o
-add wave -noupdate /main/DUT/fd0_spi_cs_gpio_n_o
-add wave -noupdate /main/DUT/fd0_spi_sclk_o
-add wave -noupdate /main/DUT/fd0_spi_mosi_o
-add wave -noupdate /main/DUT/fd0_spi_miso_i
-add wave -noupdate /main/DUT/fd0_delay_len_o
-add wave -noupdate /main/DUT/fd0_delay_val_o
-add wave -noupdate /main/DUT/fd0_delay_pulse_o
-add wave -noupdate /main/DUT/fd0_dmtd_clk_o
-add wave -noupdate /main/DUT/fd0_dmtd_fb_in_i
-add wave -noupdate /main/DUT/fd0_dmtd_fb_out_i
-add wave -noupdate /main/DUT/fd0_pll_status_i
-add wave -noupdate /main/DUT/fd0_ext_rst_n_o
-add wave -noupdate /main/DUT/fd0_onewire_b
-add wave -noupdate /main/DUT/fd1_tdc_start_p_i
-add wave -noupdate /main/DUT/fd1_tdc_start_n_i
-add wave -noupdate /main/DUT/fd1_clk_ref_p_i
-add wave -noupdate /main/DUT/fd1_clk_ref_n_i
-add wave -noupdate /main/DUT/fd1_trig_a_i
-add wave -noupdate /main/DUT/fd1_tdc_cal_pulse_o
-add wave -noupdate /main/DUT/fd1_tdc_d_b
-add wave -noupdate /main/DUT/fd1_tdc_emptyf_i
-add wave -noupdate /main/DUT/fd1_tdc_alutrigger_o
-add wave -noupdate /main/DUT/fd1_tdc_wr_n_o
-add wave -noupdate /main/DUT/fd1_tdc_rd_n_o
-add wave -noupdate /main/DUT/fd1_tdc_oe_n_o
-add wave -noupdate /main/DUT/fd1_led_trig_o
-add wave -noupdate /main/DUT/fd1_tdc_start_dis_o
-add wave -noupdate /main/DUT/fd1_tdc_stop_dis_o
-add wave -noupdate /main/DUT/fd1_spi_cs_dac_n_o
-add wave -noupdate /main/DUT/fd1_spi_cs_pll_n_o
-add wave -noupdate /main/DUT/fd1_spi_cs_gpio_n_o
-add wave -noupdate /main/DUT/fd1_spi_sclk_o
-add wave -noupdate /main/DUT/fd1_spi_mosi_o
-add wave -noupdate /main/DUT/fd1_spi_miso_i
-add wave -noupdate /main/DUT/fd1_delay_len_o
-add wave -noupdate /main/DUT/fd1_delay_val_o
-add wave -noupdate /main/DUT/fd1_delay_pulse_o
-add wave -noupdate /main/DUT/fd1_dmtd_clk_o
-add wave -noupdate /main/DUT/fd1_dmtd_fb_in_i
-add wave -noupdate /main/DUT/fd1_dmtd_fb_out_i
-add wave -noupdate /main/DUT/fd1_pll_status_i
-add wave -noupdate /main/DUT/fd1_ext_rst_n_o
-add wave -noupdate /main/DUT/fd1_onewire_b
-add wave -noupdate /main/DUT/uart_rxd_i
-add wave -noupdate /main/DUT/uart_txd_o
-add wave -noupdate /main/DUT/VME_DATA_b_out
-add wave -noupdate /main/DUT/VME_ADDR_b_out
-add wave -noupdate /main/DUT/VME_LWORD_n_b_out
-add wave -noupdate /main/DUT/VME_DATA_DIR_int
-add wave -noupdate /main/DUT/VME_ADDR_DIR_int
-add wave -noupdate /main/DUT/dac_hpll_load_p1
-add wave -noupdate /main/DUT/dac_dpll_load_p1
-add wave -noupdate /main/DUT/dac_hpll_data
-add wave -noupdate /main/DUT/dac_dpll_data
-add wave -noupdate /main/DUT/phy_tx_data
-add wave -noupdate /main/DUT/phy_tx_k
-add wave -noupdate /main/DUT/phy_tx_disparity
-add wave -noupdate /main/DUT/phy_tx_enc_err
-add wave -noupdate /main/DUT/phy_rx_data
-add wave -noupdate /main/DUT/phy_rx_rbclk
-add wave -noupdate /main/DUT/phy_rx_k
-add wave -noupdate /main/DUT/phy_rx_enc_err
-add wave -noupdate /main/DUT/phy_rx_bitslide
-add wave -noupdate /main/DUT/phy_rst
-add wave -noupdate /main/DUT/phy_loopen
 add wave -noupdate /main/DUT/cnx_master_out
 add wave -noupdate /main/DUT/cnx_master_in
 add wave -noupdate /main/DUT/cnx_slave_out
 add wave -noupdate /main/DUT/cnx_slave_in
-add wave -noupdate /main/DUT/dcm0_clk_ref_0
-add wave -noupdate /main/DUT/dcm0_clk_ref_180
-add wave -noupdate /main/DUT/fd0_tdc_start
-add wave -noupdate /main/DUT/tdc0_data_out
-add wave -noupdate /main/DUT/tdc0_data_in
-add wave -noupdate /main/DUT/tdc0_data_oe
-add wave -noupdate /main/DUT/dcm1_clk_ref_0
-add wave -noupdate /main/DUT/dcm1_clk_ref_180
-add wave -noupdate /main/DUT/fd1_tdc_start
-add wave -noupdate /main/DUT/tdc1_data_out
-add wave -noupdate /main/DUT/tdc1_data_in
-add wave -noupdate /main/DUT/tdc1_data_oe
-add wave -noupdate /main/DUT/tm_link_up
-add wave -noupdate /main/DUT/tm_utc
-add wave -noupdate /main/DUT/tm_cycles
-add wave -noupdate /main/DUT/tm_time_valid
-add wave -noupdate /main/DUT/tm0_clk_aux_lock_en
-add wave -noupdate /main/DUT/tm0_clk_aux_locked
-add wave -noupdate /main/DUT/tm1_clk_aux_lock_en
-add wave -noupdate /main/DUT/tm1_clk_aux_locked
-add wave -noupdate /main/DUT/tm_dac_value
-add wave -noupdate /main/DUT/tm0_dac_wr
-add wave -noupdate /main/DUT/tm1_dac_wr
-add wave -noupdate /main/DUT/ddr0_pll_reset
-add wave -noupdate /main/DUT/ddr0_pll_locked
-add wave -noupdate /main/DUT/fd0_pll_status
-add wave -noupdate /main/DUT/ddr1_pll_reset
-add wave -noupdate /main/DUT/ddr1_pll_locked
-add wave -noupdate /main/DUT/fd1_pll_status
-add wave -noupdate /main/DUT/wrc_scl_out
-add wave -noupdate /main/DUT/wrc_scl_in
-add wave -noupdate /main/DUT/wrc_sda_out
-add wave -noupdate /main/DUT/wrc_sda_in
-add wave -noupdate /main/DUT/fd0_scl_out
-add wave -noupdate /main/DUT/fd0_scl_in
-add wave -noupdate /main/DUT/fd0_sda_out
-add wave -noupdate /main/DUT/fd0_sda_in
-add wave -noupdate /main/DUT/fd1_scl_out
-add wave -noupdate /main/DUT/fd1_scl_in
-add wave -noupdate /main/DUT/fd1_sda_out
-add wave -noupdate /main/DUT/fd1_sda_in
-add wave -noupdate /main/DUT/sfp_scl_out
-add wave -noupdate /main/DUT/sfp_scl_in
-add wave -noupdate /main/DUT/sfp_sda_out
-add wave -noupdate /main/DUT/sfp_sda_in
-add wave -noupdate /main/DUT/wrc_owr_en
-add wave -noupdate /main/DUT/wrc_owr_in
-add wave -noupdate /main/DUT/fd0_owr_en
-add wave -noupdate /main/DUT/fd0_owr_in
-add wave -noupdate /main/DUT/fd1_owr_en
-add wave -noupdate /main/DUT/fd1_owr_in
-add wave -noupdate /main/DUT/fd0_irq
-add wave -noupdate /main/DUT/fd1_irq
-add wave -noupdate /main/DUT/pllout_clk_sys
-add wave -noupdate /main/DUT/pllout_clk_dmtd
-add wave -noupdate /main/DUT/pllout_clk_fb_pllref
-add wave -noupdate /main/DUT/pllout_clk_fb_dmtd
-add wave -noupdate /main/DUT/clk_20m_vcxo_buf
-add wave -noupdate /main/DUT/clk_125m_pllref
-add wave -noupdate /main/DUT/clk_125m_gtp
-add wave -noupdate /main/DUT/clk_sys
-add wave -noupdate /main/DUT/clk_dmtd
-add wave -noupdate /main/DUT/local_reset_n
-add wave -noupdate /main/DUT/vme_master_out
-add wave -noupdate /main/DUT/vme_master_in
-add wave -noupdate /main/DUT/pins
-add wave -noupdate /main/DUT/rst_n_a
-add wave -noupdate /main/DUT/pps
-add wave -noupdate /main/DUT/led_divider
-add wave -noupdate /main/DUT/leds
-add wave -noupdate /main/DUT/etherbone_rst_n
-add wave -noupdate /main/DUT/etherbone_src_out
-add wave -noupdate /main/DUT/etherbone_src_in
-add wave -noupdate /main/DUT/etherbone_snk_out
-add wave -noupdate /main/DUT/etherbone_snk_in
-add wave -noupdate /main/DUT/etherbone_cfg_in
-add wave -noupdate /main/DUT/etherbone_cfg_out
 TreeUpdate [SetDefaultTree]
-WaveRestoreCursors {{Cursor 1} {23693000000 fs} 0}
+WaveRestoreCursors {{Cursor 1} {53004000000 fs} 0}
 configure wave -namecolwidth 183
 configure wave -valuecolwidth 100
 configure wave -justifyvalue left
@@ -235,4 +20,4 @@ configure wave -griddelta 40
 configure wave -timeline 0
 configure wave -timelineunits ns
 update
-WaveRestoreZoom {2400011620 fs} {12618218340 fs}
+WaveRestoreZoom {0 fs} {226247193600 fs}
--- a/hdl/testbench/svec_wr_top/wrc-simulation.ram
+++ b/hdl/testbench/svec_wr_top/wrc-simulation.ram
+write 0 98000000
+write 1 D0000000
+write 2 D0200000
+write 3 78010000
+write 4 38210000
+write 5 D0E10000
+write 6 98000000
+write 7 781C0000
+write 8 3B9C0FFC
+write 9 781A0000
+write a 3B5A8160
+write b F800001F
+write c 78030000
+write d 3863013C
+write e 28610000
+write f 3802C49C
+write 10 58220004
+write 11 C3A00000
+write 12 78030000
+write 13 3863013C
+write 14 28620000
+write 15 28430000
+write 16 20630001
+write 17 5C60FFFE
+write 18 78030000
+write 19 3863013C
+write 1a 28620000
+write 1b 58410008
+write 1c C3A00000
+write 1d 379CFFF8
+write 1e 5B8B0008
+write 1f 5B9D0004
+write 20 B8205800
+write 21 E0000002
+write 22 FBFFFFF0
+write 23 41610000
+write 24 356B0001
+write 25 5C20FFFD
+write 26 2B9D0004
+write 27 2B8B0008
+write 28 379C0008
+write 29 C3A00000
+write 2a 379CFFFC
+write 2b 5B9D0004
+write 2c 78020000
+write 2d 38420140
+write 2e 28410000
+write 2f 78030000
+write 30 34020012
+write 31 38630144
+write 32 58220000
+write 33 28620000
+write 34 78030000
+write 35 38630148
+write 36 58400000
+write 37 28620000
+write 38 78030000
+write 39 3863014C
+write 3a 58400000
+write 3b 28620000
+write 3c 58400000
+write 3d 34020000
+write 3e 38430008
+write 3f 58230000
+write 40 78030000
+write 41 38630150
+write 42 58220000
+write 43 28610000
+write 44 78030000
+write 45 34020004
+write 46 3863013C
+write 47 58220000
+write 48 28610000
+write 49 3802C49C
+write 4a 58220004
+write 4b 78010000
+write 4c 38210154
+write 4d FBFFFFD0
+write 4e E0000000
+write 4f 00020500
+write 50 00020300
+write 51 00020314
+write 52 00020318
+write 53 00020310
+write 54 0002031C
+write 55 54686520
+write 56 57522043
+write 57 6F726520
+write 58 73617973
+write 59 2068656C
+write 5a 6C6F210A
+write 5b 00000000
+write 5c 00000000
+write 5d 00000000
+write 5e 00000000
+write 5f 00000000
+write 60 00000000
+write 61 00000000
+write 62 00000000
+write 63 00000000
+write 64 00000000
+write 65 00000000
+write 66 00000000
+write 67 00000000
+write 68 00000000
+write 69 00000000
+write 6a 00000000
+write 6b 00000000
+write 6c 00000000
+write 6d 00000000
+write 6e 00000000
+write 6f 00000000
+write 70 00000000
+write 71 00000000
+write 72 00000000
+write 73 00000000
+write 74 00000000
+write 75 00000000
+write 76 00000000
+write 77 00000000
+write 78 00000000
+write 79 00000000
+write 7a 00000000
+write 7b 00000000
+write 7c 00000000
+write 7d 00000000
+write 7e 00000000
+write 7f 00000000
+write 80 00000000
+write 81 00000000
+write 82 00000000
+write 83 00000000
+write 84 00000000
+write 85 00000000
+write 86 00000000
+write 87 00000000
+write 88 00000000
+write 89 00000000
+write 8a 00000000
+write 8b 00000000
+write 8c 00000000
+write 8d 00000000
+write 8e 00000000
+write 8f 00000000
+write 90 00000000
+write 91 00000000
+write 92 00000000
+write 93 00000000
+write 94 00000000
+write 95 00000000
+write 96 00000000
+write 97 00000000
+write 98 00000000
+write 99 00000000
+write 9a 00000000
+write 9b 00000000
+write 9c 00000000
+write 9d 00000000
+write 9e 00000000
+write 9f 00000000
+write a0 00000000
+write a1 00000000
+write a2 00000000
+write a3 00000000
+write a4 00000000
+write a5 00000000
+write a6 00000000
+write a7 00000000
+write a8 00000000
+write a9 00000000
+write aa 00000000
+write ab 00000000
+write ac 00000000
+write ad 00000000
+write ae 00000000
+write af 00000000
+write b0 00000000
+write b1 00000000
+write b2 00000000
+write b3 00000000
+write b4 00000000
+write b5 00000000
+write b6 00000000
+write b7 00000000
+write b8 00000000
+write b9 00000000
+write ba 00000000
+write bb 00000000
+write bc 00000000
+write bd 00000000
+write be 00000000
+write bf 00000000
+write c0 00000000
+write c1 00000000
+write c2 00000000
+write c3 00000000
+write c4 00000000
+write c5 00000000
+write c6 00000000
+write c7 00000000
+write c8 00000000
+write c9 00000000
+write ca 00000000
+write cb 00000000
+write cc 00000000
+write cd 00000000
+write ce 00000000
+write cf 00000000
+write d0 00000000
+write d1 00000000
+write d2 00000000
+write d3 00000000
+write d4 00000000
+write d5 00000000
+write d6 00000000
+write d7 00000000
+write d8 00000000
+write d9 00000000
+write da 00000000
+write db 00000000
+write dc 00000000
+write dd 00000000
+write de 00000000
+write df 00000000
+write e0 00000000
+write e1 00000000
+write e2 00000000
+write e3 00000000
+write e4 00000000
+write e5 00000000
+write e6 00000000
+write e7 00000000
+write e8 00000000
+write e9 00000000
+write ea 00000000
+write eb 00000000
+write ec 00000000
+write ed 00000000
+write ee 00000000
+write ef 00000000
+write f0 00000000
+write f1 00000000
+write f2 00000000
+write f3 00000000
+write f4 00000000
+write f5 00000000
+write f6 00000000
+write f7 00000000
+write f8 00000000
+write f9 00000000
+write fa 00000000
+write fb 00000000
+write fc 00000000
+write fd 00000000
+write fe 00000000
+write ff 00000000
+write 100 00000000
+write 101 00000000
+write 102 00000000
+write 103 00000000
+write 104 00000000
+write 105 00000000
+write 106 00000000
+write 107 00000000
+write 108 00000000
+write 109 00000000
+write 10a 00000000
+write 10b 00000000
+write 10c 00000000
+write 10d 00000000
+write 10e 00000000
+write 10f 00000000
+write 110 00000000
+write 111 00000000
+write 112 00000000
+write 113 00000000
+write 114 00000000
+write 115 00000000
+write 116 00000000
+write 117 00000000
+write 118 00000000
+write 119 00000000
+write 11a 00000000
+write 11b 00000000
+write 11c 00000000
+write 11d 00000000
+write 11e 00000000
+write 11f 00000000
+write 120 00000000
+write 121 00000000
+write 122 00000000
+write 123 00000000
+write 124 00000000
+write 125 00000000
+write 126 00000000
+write 127 00000000
+write 128 00000000
+write 129 00000000
+write 12a 00000000
+write 12b 00000000
+write 12c 00000000
+write 12d 00000000
+write 12e 00000000
+write 12f 00000000
+write 130 00000000
+write 131 00000000
+write 132 00000000
+write 133 00000000
+write 134 00000000
+write 135 00000000
+write 136 00000000
+write 137 00000000
+write 138 00000000
+write 139 00000000
+write 13a 00000000
+write 13b 00000000
+write 13c 00000000
+write 13d 00000000
+write 13e 00000000
+write 13f 00000000
+write 140 00000000
+write 141 00000000
+write 142 00000000
+write 143 00000000
+write 144 00000000
+write 145 00000000
+write 146 00000000
+write 147 00000000
+write 148 00000000
+write 149 00000000
+write 14a 00000000
+write 14b 00000000
+write 14c 00000000
+write 14d 00000000
+write 14e 00000000
+write 14f 00000000
+write 150 00000000
+write 151 00000000
+write 152 00000000
+write 153 00000000
+write 154 00000000
+write 155 00000000
+write 156 00000000
+write 157 00000000
+write 158 00000000
+write 159 00000000
+write 15a 00000000
+write 15b 00000000
+write 15c 00000000
+write 15d 00000000
+write 15e 00000000
+write 15f 00000000
+write 160 00000000
+write 161 00000000
+write 162 00000000
+write 163 00000000
+write 164 00000000
+write 165 00000000
+write 166 00000000
+write 167 00000000
+write 168 00000000
+write 169 00000000
+write 16a 00000000
+write 16b 00000000
+write 16c 00000000
+write 16d 00000000
+write 16e 00000000
+write 16f 00000000
+write 170 00000000
+write 171 00000000
+write 172 00000000
+write 173 00000000
+write 174 00000000
+write 175 00000000
+write 176 00000000
+write 177 00000000
+write 178 00000000
+write 179 00000000
+write 17a 00000000
+write 17b 00000000
+write 17c 00000000
+write 17d 00000000
+write 17e 00000000
+write 17f 00000000
+write 180 00000000
+write 181 00000000
+write 182 00000000
+write 183 00000000
+write 184 00000000
+write 185 00000000
+write 186 00000000
+write 187 00000000
+write 188 00000000
+write 189 00000000
+write 18a 00000000
+write 18b 00000000
+write 18c 00000000
+write 18d 00000000
+write 18e 00000000
+write 18f 00000000
+write 190 00000000
+write 191 00000000
+write 192 00000000
+write 193 00000000
+write 194 00000000
+write 195 00000000
+write 196 00000000
+write 197 00000000
+write 198 00000000
+write 199 00000000
+write 19a 00000000
+write 19b 00000000
+write 19c 00000000
+write 19d 00000000
+write 19e 00000000
+write 19f 00000000
+write 1a0 00000000
+write 1a1 00000000
+write 1a2 00000000
+write 1a3 00000000
+write 1a4 00000000
+write 1a5 00000000
+write 1a6 00000000
+write 1a7 00000000
+write 1a8 00000000
+write 1a9 00000000
+write 1aa 00000000
+write 1ab 00000000
+write 1ac 00000000
+write 1ad 00000000
+write 1ae 00000000
+write 1af 00000000
+write 1b0 00000000
+write 1b1 00000000
+write 1b2 00000000
+write 1b3 00000000
+write 1b4 00000000
+write 1b5 00000000
+write 1b6 00000000
+write 1b7 00000000
+write 1b8 00000000
+write 1b9 00000000
+write 1ba 00000000
+write 1bb 00000000
+write 1bc 00000000
+write 1bd 00000000
+write 1be 00000000
+write 1bf 00000000
+write 1c0 00000000
+write 1c1 00000000
+write 1c2 00000000
+write 1c3 00000000
+write 1c4 00000000
+write 1c5 00000000
+write 1c6 00000000
+write 1c7 00000000
+write 1c8 00000000
+write 1c9 00000000
+write 1ca 00000000
+write 1cb 00000000
+write 1cc 00000000
+write 1cd 00000000
+write 1ce 00000000
+write 1cf 00000000
+write 1d0 00000000
+write 1d1 00000000
+write 1d2 00000000
+write 1d3 00000000
+write 1d4 00000000
+write 1d5 00000000
+write 1d6 00000000
+write 1d7 00000000
+write 1d8 00000000
+write 1d9 00000000
+write 1da 00000000
+write 1db 00000000
+write 1dc 00000000
+write 1dd 00000000
+write 1de 00000000
+write 1df 00000000
+write 1e0 00000000
+write 1e1 00000000
+write 1e2 00000000
+write 1e3 00000000
+write 1e4 00000000
+write 1e5 00000000
+write 1e6 00000000
+write 1e7 00000000
+write 1e8 00000000
+write 1e9 00000000
+write 1ea 00000000
+write 1eb 00000000
+write 1ec 00000000
+write 1ed 00000000
+write 1ee 00000000
+write 1ef 00000000
+write 1f0 00000000
+write 1f1 00000000
+write 1f2 00000000
+write 1f3 00000000
+write 1f4 00000000
+write 1f5 00000000
+write 1f6 00000000
+write 1f7 00000000
+write 1f8 00000000
+write 1f9 00000000
+write 1fa 00000000
+write 1fb 00000000
+write 1fc 00000000
+write 1fd 00000000
+write 1fe 00000000
+write 1ff 00000000
+write 200 00000000
+write 201 00000000
+write 202 00000000
+write 203 00000000
+write 204 00000000
+write 205 00000000
+write 206 00000000
+write 207 00000000
+write 208 00000000
+write 209 00000000
+write 20a 00000000
+write 20b 00000000
+write 20c 00000000
+write 20d 00000000
+write 20e 00000000
+write 20f 00000000
+write 210 00000000
+write 211 00000000
+write 212 00000000
+write 213 00000000
+write 214 00000000
+write 215 00000000
+write 216 00000000
+write 217 00000000
+write 218 00000000
+write 219 00000000
+write 21a 00000000
+write 21b 00000000
+write 21c 00000000
+write 21d 00000000
+write 21e 00000000
+write 21f 00000000
+write 220 00000000
+write 221 00000000
+write 222 00000000
+write 223 00000000
+write 224 00000000
+write 225 00000000
+write 226 00000000
+write 227 00000000
+write 228 00000000
+write 229 00000000
+write 22a 00000000
+write 22b 00000000
+write 22c 00000000
+write 22d 00000000
+write 22e 00000000
+write 22f 00000000
+write 230 00000000
+write 231 00000000
+write 232 00000000
+write 233 00000000
+write 234 00000000
+write 235 00000000
+write 236 00000000
+write 237 00000000
+write 238 00000000
+write 239 00000000
+write 23a 00000000
+write 23b 00000000
+write 23c 00000000
+write 23d 00000000
+write 23e 00000000
+write 23f 00000000
+write 240 00000000
+write 241 00000000
+write 242 00000000
+write 243 00000000
+write 244 00000000
+write 245 00000000
+write 246 00000000
+write 247 00000000
+write 248 00000000
+write 249 00000000
+write 24a 00000000
+write 24b 00000000
+write 24c 00000000
+write 24d 00000000
+write 24e 00000000
+write 24f 00000000
+write 250 00000000
+write 251 00000000
+write 252 00000000
+write 253 00000000
+write 254 00000000
+write 255 00000000
+write 256 00000000
+write 257 00000000
+write 258 00000000
+write 259 00000000
+write 25a 00000000
+write 25b 00000000
+write 25c 00000000
+write 25d 00000000
+write 25e 00000000
+write 25f 00000000
+write 260 00000000
+write 261 00000000
+write 262 00000000
+write 263 00000000
+write 264 00000000
+write 265 00000000
+write 266 00000000
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+write 3a1 00000000
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+write 3af 00000000
+write 3b0 00000000
+write 3b1 00000000
+write 3b2 00000000
+write 3b3 00000000
+write 3b4 00000000
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+write 3ba 00000000
+write 3bb 00000000
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+write 3bd 00000000
+write 3be 00000000
+write 3bf 00000000
+write 3c0 00000000
+write 3c1 00000000
+write 3c2 00000000
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+write 3d1 00000000
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+write 3e1 00000000
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+write 3e3 00000000
+write 3e4 00000000
+write 3e5 00000000
+write 3e6 00000000
+write 3e7 00000000
--- a/hdl/testbench/svec_wr_top/wrc.ram
+++ b/hdl/testbench/svec_wr_top/wrc.ram
--- a/hdl/top/spec/wr/Manifest.py
+++ b/hdl/top/spec/wr/Manifest.py
-files = ["spec_top.vhd", "spec_top.ucf", "spec_serial_dac.vhd", "spec_serial_dac_arb.vhd", "spec_reset_gen.vhd"]
+files = ["synthesis_descriptor.vhd", "spec_top.vhd", "spec_top.ucf", "spec_serial_dac.vhd", "spec_serial_dac_arb.vhd", "spec_reset_gen.vhd"]

 fetchto = "../../../ip_cores"


--- a/hdl/top/spec/wr/spec_top.ucf
+++ b/hdl/top/spec/wr/spec_top.ucf
@@ -171,6 +171,15 @@ NET "fmc_scl_b" IOSTANDARD =LVCMOS25;
 NET "fmc_sda_b" LOC =  F8 ;
 NET "fmc_sda_b" IOSTANDARD =LVCMOS25;

+#net "led_n_o[0]" loc=c20;
+#net "led_n_o[0]" IOSTANDARD=LVCMOS18;
+#net "led_n_o[1]" loc=F18;
+#net "led_n_o[1]" IOSTANDARD=LVCMOS18;
+#net "led_n_o[2]" loc=f20;
+#net "led_n_o[2]" IOSTANDARD=LVCMOS18;
+#net "led_n_o[3]" loc=G19;
+#net "led_n_o[3]" IOSTANDARD=LVCMOS18;
+

 NET "carrier_onewire_b" LOC = D4;
 NET "carrier_onewire_b" IOSTANDARD = "LVCMOS25";

--- a/hdl/top/spec/wr/spec_top.vhd
+++ b/hdl/top/spec/wr/spec_top.vhd
@@ -6,7 +6,7 @@
 -- Author     : Tomasz Wlostowski
 -- Company    : CERN
 -- Created    : 2011-08-24
-- Last update: 2013-02-22
+-- Last update: 2013-04-17
 -- Platform   : FPGA-generic
 -- Standard   : VHDL'93
 -------------------------------------------------------------------------------
@@ -50,6 +50,8 @@ use work.fine_delay_pkg.all;
 use work.etherbone_pkg.all;
 use work.wr_xilinx_pkg.all;

+use work.synthesis_descriptor.all;
+
 library UNISIM;
 use UNISIM.vcomponents.all;

@@ -264,35 +266,26 @@ architecture rtl of spec_top is
  constant c_MASTER_GENNUM    : integer := 0;
  constant c_MASTER_ETHERBONE : integer := 1;

-  constant c_SLAVE_FD     : integer := 0;
-  constant c_SLAVE_WRCORE : integer := 1;
-  constant c_SLAVE_VIC    : integer := 2;
+  constant c_SLAVE_FD       : integer := 0;
+  constant c_SLAVE_WRCORE   : integer := 1;
+  constant c_SLAVE_VIC      : integer := 2;
+  constant c_DESC_SYNTHESIS : integer := 3;
+  constant c_DESC_REPO_URL  : integer := 4;

  constant c_WRCORE_BRIDGE_SDB : t_sdb_bridge := f_xwb_bridge_manual_sdb(x"0003ffff", x"00030000");

-  constant c_xwb_vic_sdb : t_sdb_device := (
-    abi_class     => x"0000", -- undocumented device
-    abi_ver_major => x"01",
-    abi_ver_minor => x"01",
-    wbd_endian    => c_sdb_endian_big,
-    wbd_width     => x"7", -- 8/16/32-bit port granularity
-    sdb_component => (
-    addr_first    => x"0000000000000000",
-    addr_last     => x"00000000000000ff",
-    product => (
-    vendor_id     => x"000000000000CE42", -- CERN
-    device_id     => x"00000013",
-    version       => x"00000001",
-    date          => x"20120113",
-    name          => "WB-VIC-Int.Control ")));
-
-  constant c_INTERCONNECT_LAYOUT : t_sdb_record_array(c_NUM_WB_MASTERS-1 downto 0) :=
-    (c_SLAVE_WRCORE => f_sdb_embed_bridge(c_WRCORE_BRIDGE_SDB, x"000c0000"),
-     c_SLAVE_FD     => f_sdb_embed_device(c_FD_SDB_DEVICE, x"00080000"),
-     c_SLAVE_VIC    => f_sdb_embed_device(c_xwb_vic_sdb, x"00090000"));
+  constant c_INTERCONNECT_LAYOUT : t_sdb_record_array(c_NUM_WB_MASTERS+1 downto 0) :=
+    (c_SLAVE_WRCORE   => f_sdb_embed_bridge(c_WRCORE_BRIDGE_SDB, x"000c0000"),
+     c_SLAVE_FD       => f_sdb_embed_device(c_FD_SDB_DEVICE, x"00080000"),
+     c_SLAVE_VIC      => f_sdb_embed_device(c_xwb_vic_sdb, x"00090000"),
+     c_DESC_SYNTHESIS => f_sdb_embed_synthesis(c_sdb_synthesis_info),
+     c_DESC_REPO_URL  => f_sdb_embed_repo_url(c_sdb_repo_url));

  constant c_SDB_ADDRESS : t_wishbone_address := x"00000000";

+  constant c_VIC_VECTOR_TABLE : t_wishbone_address_array(0 to 0) :=
+    (0 => x"00080000");
+
  signal pllout_clk_sys       : std_logic;
  signal pllout_clk_dmtd      : std_logic;
  signal pllout_clk_fb_pllref : std_logic;
@@ -567,7 +560,7 @@ begin
 -------------------------------------------------------------------------------
 -- Top level interconnect and interrupt controller
 -------------------------------------------------------------------------------
-  
+
  U_Intercon : xwb_sdb_crossbar
    generic map (
      g_num_masters => c_NUM_WB_SLAVES,
@@ -588,7 +581,8 @@ begin
    generic map (
      g_interface_mode      => PIPELINED,
      g_address_granularity => BYTE,
-      g_num_interrupts      => 1)
+      g_num_interrupts      => 1,
+      g_init_vectors        => c_VIC_VECTOR_TABLE)
    port map (
      clk_sys_i    => clk_sys,
      rst_n_i      => local_reset_n,
@@ -626,10 +620,11 @@ begin
      g_with_external_clock_input => false,
      g_aux_clks                  => 1,
      g_ep_rxbuf_size             => 1024,
-      g_dpram_initf               => "wrc.ram",
+      g_dpram_initf               => "none",
      g_dpram_size                => 90112/4,
      g_interface_mode            => PIPELINED,
-      g_address_granularity       => BYTE)
+      g_address_granularity       => BYTE,
+      g_softpll_enable_debugger   => false)
    port map (
      clk_sys_i    => clk_sys,
      clk_dmtd_i   => clk_dmtd,
@@ -655,7 +650,7 @@ begin
      phy_rst_o          => phy_rst,
      phy_loopen_o       => phy_loopen,

-      led_act_o   => LED_RED,
+      led_act_o  => LED_RED,
      led_link_o => LED_GREEN,

      scl_o     => wrc_scl_out,
@@ -687,9 +682,9 @@ begin

      tm_link_up_o         => tm_link_up,
      tm_dac_value_o       => tm_dac_value,
-      tm_dac_wr_o          => tm_dac_wr,
-      tm_clk_aux_lock_en_i => tm_clk_aux_lock_en,
-      tm_clk_aux_locked_o  => tm_clk_aux_locked,
+      tm_dac_wr_o(0)          => tm_dac_wr,
+      tm_clk_aux_lock_en_i(0) => tm_clk_aux_lock_en,
+      tm_clk_aux_locked_o(0)  => tm_clk_aux_locked,
      tm_time_valid_o      => tm_time_valid,
      tm_tai_o             => tm_utc,
      tm_cycles_o          => tm_cycles,

--- a/hdl/top/spec/wr/synthesis_descriptor.vhd
+++ b/hdl/top/spec/wr/synthesis_descriptor.vhd
+-------------------------------------------------------------------------------
+-- Title      : Fine Delay FMC SPEC (Simple PCIe FMC Carrier) SDB descriptor
+-- Project    : Fine Delay FMC (fmc-delay-1ns-4cha)
+-------------------------------------------------------------------------------
+-- File       : synthesis_descriptor.vhd
+-- Author     : Tomasz Wlostowski
+-- Company    : CERN
+-- Created    : 2013-04-16
+-- Last update: 2013-04-16
+-- Platform   : FPGA-generic
+-- Standard   : VHDL'93
+-------------------------------------------------------------------------------
+-- Description: SDB descriptor for the top level of the FD on a SPEC carrier.
+-- Contains synthesis & source repository information.
+-- Warning: this file is modified whenever a synthesis is executed.
+-------------------------------------------------------------------------------
+--
+-- Copyright (c) 2013 CERN / BE-CO-HT
+--
+-- This source file is free software; you can redistribute it   
+-- and/or modify it under the terms of the GNU Lesser General   
+-- Public License as published by the Free Software Foundation; 
+-- either version 2.1 of the License, or (at your option) any   
+-- later version.                                               
+--
+-- This source is distributed in the hope that it will be       
+-- useful, but WITHOUT ANY WARRANTY; without even the implied   
+-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      
+-- PURPOSE.  See the GNU Lesser General Public License for more 
+-- details.                                                     
+--
+-- You should have received a copy of the GNU Lesser General    
+-- Public License along with this source; if not, download it   
+-- from http://www.gnu.org/licenses/lgpl-2.1.html
+--
+-------------------------------------------------------------------------------
+library ieee;
+use ieee.STD_LOGIC_1164.all;
+use work.wishbone_pkg.all;
+
+package synthesis_descriptor is
+  
+constant c_sdb_synthesis_info : t_sdb_synthesis :=
+  (
+    syn_module_name => "fine-delay-spec ",
+    syn_commit_id => "00000000000000000000000000000000",
+    syn_tool_name => "ISE     ",
+    syn_tool_version => x"00000133",
+    syn_date => x"00000000",
+    syn_username => "twlostow       ");
+
+constant c_sdb_repo_url : t_sdb_repo_url :=
+  (
+    repo_url => "git://ohwr.org/fmc-projects/fmc-delay-1ns-8cha.git             " 
+  );
+
+end package synthesis_descriptor;
--- a/hdl/top/svec/wr/Manifest.py
+++ b/hdl/top/svec/wr/Manifest.py
-files = [ "svec_top.vhd", "svec_top.ucf", "xvme64x_core.vhd" ]
+files = [ "synthesis_descriptor.vhd", "svec_top.vhd", "svec_top.ucf", "xvme64x_core.vhd" ]

 fetchto = "../../../ip_cores"


--- a/hdl/top/svec/wr/svec_top.ucf
+++ b/hdl/top/svec/wr/svec_top.ucf
@@ -150,23 +150,23 @@ NET "pll25dac_sync_n_o" LOC = P26;
 NET "uart_txd_o" LOC = U27;
 NET "uart_rxd_i" LOC = U25;

-NET "fp_ledn_o[0]" LOC = AD27;
-NET "fp_ledn_o[1]" LOC = AD26;
-NET "fp_ledn_o[2]" LOC = AC28;
-NET "fp_ledn_o[3]" LOC = AC27;
-NET "fp_ledn_o[4]" LOC = AE27;
-NET "fp_ledn_o[5]" LOC = AE30;
-NET "fp_ledn_o[6]" LOC = AF28;
-NET "fp_ledn_o[7]" LOC = AE28;
-
-NET "fp_ledn_o[0]" IOSTANDARD = "LVCMOS33";
-NET "fp_ledn_o[1]" IOSTANDARD = "LVCMOS33";
-NET "fp_ledn_o[2]" IOSTANDARD = "LVCMOS33";
-NET "fp_ledn_o[3]" IOSTANDARD = "LVCMOS33";
-NET "fp_ledn_o[4]" IOSTANDARD = "LVCMOS33";
-NET "fp_ledn_o[5]" IOSTANDARD = "LVCMOS33";
-NET "fp_ledn_o[6]" IOSTANDARD = "LVCMOS33";
-NET "fp_ledn_o[7]" IOSTANDARD = "LVCMOS33";
+#NET "fp_ledn_o[0]" LOC = AD27;
+#NET "fp_ledn_o[1]" LOC = AD26;
+#NET "fp_ledn_o[2]" LOC = AC28;
+#NET "fp_ledn_o[3]" LOC = AC27;
+#NET "fp_ledn_o[4]" LOC = AE27;
+#NET "fp_ledn_o[5]" LOC = AE30;
+#NET "fp_ledn_o[6]" LOC = AF28;
+#NET "fp_ledn_o[7]" LOC = AE28;
+
+#NET "fp_ledn_o[0]" IOSTANDARD = "LVCMOS33";
+#NET "fp_ledn_o[1]" IOSTANDARD = "LVCMOS33";
+#NET "fp_ledn_o[2]" IOSTANDARD = "LVCMOS33";
+#NET "fp_ledn_o[3]" IOSTANDARD = "LVCMOS33";
+#NET "fp_ledn_o[4]" IOSTANDARD = "LVCMOS33";
+#NET "fp_ledn_o[5]" IOSTANDARD = "LVCMOS33";
+#NET "fp_ledn_o[6]" IOSTANDARD = "LVCMOS33";
+#NET "fp_ledn_o[7]" IOSTANDARD = "LVCMOS33";

 #----------------------------------------
 # 1-wire thermoeter + unique ID
@@ -321,13 +321,13 @@ NET "uart_rxd_i" IOSTANDARD = "LVCMOS33";
 NET "tempid_dq_b" IOSTANDARD = "LVCMOS33";


-NET "fmc1_prsntm2c_n_i" LOC = N30;
-NET "fmc1_scl_b" LOC = P28;
-NET "fmc1_sda_b" LOC = P30;
+NET "fmc0_prsntm2c_n_i" LOC = N30;
+NET "fmc0_scl_b" LOC = P28;
+NET "fmc0_sda_b" LOC = P30;

-NET "fmc0_prsntm2c_n_i" LOC = AE29;
-NET "fmc0_scl_b" LOC = W29;
-NET "fmc0_sda_b" LOC = V30;
+NET "fmc1_prsntm2c_n_i" LOC = AE29;
+NET "fmc1_scl_b" LOC = W29;
+NET "fmc1_sda_b" LOC = V30;



@@ -379,293 +379,294 @@ TIMESPEC TS_x6 = FROM "gen_with_phy_U_GTP_ch1_rx_divclk" TO "clk_125m_pllref_p_i

 # This section has bee generated automatically by ucfgen.py. Do not hand-modify if not really necessary.
 # ucfgen pin assignments for mezzanine fmc-delay-v4 slot 0
-NET "fd1_clk_ref_p_i" LOC = "E16";
-NET "fd1_clk_ref_p_i" IOSTANDARD = "LVDS_25";
-NET "fd1_clk_ref_n_i" LOC = "D16";
-NET "fd1_clk_ref_n_i" IOSTANDARD = "LVDS_25";
-NET "fd1_tdc_start_p_i" LOC = "H15";
-NET "fd1_tdc_start_p_i" IOSTANDARD = "LVDS_25";
-NET "fd1_tdc_start_n_i" LOC = "G15";
-NET "fd1_tdc_start_n_i" IOSTANDARD = "LVDS_25";
-NET "fd1_delay_len_o[3]" LOC = "G10";
-NET "fd1_delay_len_o[3]" IOSTANDARD = "LVCMOS25";
-NET "fd1_delay_len_o[2]" LOC = "F10";
-NET "fd1_delay_len_o[2]" IOSTANDARD = "LVCMOS25";
-NET "fd1_delay_len_o[1]" LOC = "E9";
-NET "fd1_delay_len_o[1]" IOSTANDARD = "LVCMOS25";
-NET "fd1_delay_len_o[0]" LOC = "F9";
-NET "fd1_delay_len_o[0]" IOSTANDARD = "LVCMOS25";
-NET "fd1_delay_pulse_o[3]" LOC = "F12";
-NET "fd1_delay_pulse_o[3]" IOSTANDARD = "LVCMOS25";
-NET "fd1_delay_pulse_o[1]" LOC = "E11";
-NET "fd1_delay_pulse_o[1]" IOSTANDARD = "LVCMOS25";
-NET "fd1_delay_pulse_o[2]" LOC = "G12";
-NET "fd1_delay_pulse_o[2]" IOSTANDARD = "LVCMOS25";
-NET "fd1_delay_pulse_o[0]" LOC = "F11";
-NET "fd1_delay_pulse_o[0]" IOSTANDARD = "LVCMOS25";
-NET "fd1_delay_val_o[3]" LOC = "J12";
-NET "fd1_delay_val_o[3]" IOSTANDARD = "LVCMOS25";
-NET "fd1_delay_val_o[1]" LOC = "H11";
-NET "fd1_delay_val_o[1]" IOSTANDARD = "LVCMOS25";
-NET "fd1_delay_val_o[7]" LOC = "L11";
-NET "fd1_delay_val_o[7]" IOSTANDARD = "LVCMOS25";
-NET "fd1_delay_val_o[5]" LOC = "J13";
-NET "fd1_delay_val_o[5]" IOSTANDARD = "LVCMOS25";
-NET "fd1_delay_val_o[9]" LOC = "L12";
-NET "fd1_delay_val_o[9]" IOSTANDARD = "LVCMOS25";
-NET "fd1_spi_mosi_o" LOC = "M13";
-NET "fd1_spi_mosi_o" IOSTANDARD = "LVCMOS25";
-NET "fd1_spi_sclk_o" LOC = "L14";
-NET "fd1_spi_sclk_o" IOSTANDARD = "LVCMOS25";
-NET "fd1_tdc_oe_n_o" LOC = "M15";
-NET "fd1_tdc_oe_n_o" IOSTANDARD = "LVCMOS25";
-NET "fd1_tdc_start_dis_o" LOC = "F13";
-NET "fd1_tdc_start_dis_o" IOSTANDARD = "LVCMOS25";
-NET "fd1_spi_cs_gpio_n_o" LOC = "F15";
-NET "fd1_spi_cs_gpio_n_o" IOSTANDARD = "LVCMOS25";
-NET "fd1_tdc_cal_pulse_o" LOC = "G14";
-NET "fd1_tdc_cal_pulse_o" IOSTANDARD = "LVCMOS25";
-NET "fd1_dmtd_clk_o" LOC = "J14";
-NET "fd1_dmtd_clk_o" IOSTANDARD = "LVCMOS25";
-NET "fd1_tdc_wr_n_o" LOC = "B15";
-NET "fd1_tdc_wr_n_o" IOSTANDARD = "LVCMOS25";
-NET "fd1_tdc_alutrigger_o" LOC = "F19";
-NET "fd1_tdc_alutrigger_o" IOSTANDARD = "LVCMOS25";
-NET "fd1_led_trig_o" LOC = "H16";
-NET "fd1_led_trig_o" IOSTANDARD = "LVCMOS25";
-NET "fd1_tdc_d_b[26]" LOC = "F17";
-NET "fd1_tdc_d_b[26]" IOSTANDARD = "LVCMOS25";
-NET "fd1_tdc_d_b[24]" LOC = "G18";
-NET "fd1_tdc_d_b[24]" IOSTANDARD = "LVCMOS25";
-NET "fd1_tdc_d_b[20]" LOC = "F21";
-NET "fd1_tdc_d_b[20]" IOSTANDARD = "LVCMOS25";
-NET "fd1_tdc_d_b[22]" LOC = "G20";
-NET "fd1_tdc_d_b[22]" IOSTANDARD = "LVCMOS25";
-NET "fd1_tdc_d_b[18]" LOC = "L21";
-NET "fd1_tdc_d_b[18]" IOSTANDARD = "LVCMOS25";
-NET "fd1_tdc_d_b[16]" LOC = "M20";
-NET "fd1_tdc_d_b[16]" IOSTANDARD = "LVCMOS25";
-NET "fd1_tdc_d_b[10]" LOC = "F23";
-NET "fd1_tdc_d_b[10]" IOSTANDARD = "LVCMOS25";
-NET "fd1_tdc_d_b[14]" LOC = "G22";
-NET "fd1_tdc_d_b[14]" IOSTANDARD = "LVCMOS25";
-NET "fd1_tdc_d_b[8]" LOC = "B25";
-NET "fd1_tdc_d_b[8]" IOSTANDARD = "LVCMOS25";
-NET "fd1_tdc_d_b[12]" LOC = "M19";
-NET "fd1_tdc_d_b[12]" IOSTANDARD = "LVCMOS25";
-NET "fd1_tdc_d_b[3]" LOC = "D24";
-NET "fd1_tdc_d_b[3]" IOSTANDARD = "LVCMOS25";
-NET "fd1_tdc_d_b[5]" LOC = "E25";
-NET "fd1_tdc_d_b[5]" IOSTANDARD = "LVCMOS25";
-NET "fd1_tdc_d_b[7]" LOC = "J22";
-NET "fd1_tdc_d_b[7]" IOSTANDARD = "LVCMOS25";
-NET "fd1_tdc_d_b[2]" LOC = "H21";
-NET "fd1_tdc_d_b[2]" IOSTANDARD = "LVCMOS25";
-NET "fd1_trig_a_i" LOC = "C16";
-NET "fd1_trig_a_i" IOSTANDARD = "LVCMOS25";
-NET "fd1_delay_val_o[2]" LOC = "H12";
-NET "fd1_delay_val_o[2]" IOSTANDARD = "LVCMOS25";
-NET "fd1_delay_val_o[0]" LOC = "G11";
-NET "fd1_delay_val_o[0]" IOSTANDARD = "LVCMOS25";
-NET "fd1_delay_val_o[6]" LOC = "K11";
-NET "fd1_delay_val_o[6]" IOSTANDARD = "LVCMOS25";
-NET "fd1_delay_val_o[4]" LOC = "H13";
-NET "fd1_delay_val_o[4]" IOSTANDARD = "LVCMOS25";
-NET "fd1_delay_val_o[8]" LOC = "K12";
-NET "fd1_delay_val_o[8]" IOSTANDARD = "LVCMOS25";
-NET "fd1_spi_miso_i" LOC = "L13";
-NET "fd1_spi_miso_i" IOSTANDARD = "LVCMOS25";
-NET "fd1_spi_cs_pll_n_o" LOC = "K14";
-NET "fd1_spi_cs_pll_n_o" IOSTANDARD = "LVCMOS25";
-NET "fd1_spi_cs_dac_n_o" LOC = "K15";
-NET "fd1_spi_cs_dac_n_o" IOSTANDARD = "LVCMOS25";
-NET "fd1_tdc_stop_dis_o" LOC = "E13";
-NET "fd1_tdc_stop_dis_o" IOSTANDARD = "LVCMOS25";
-NET "fd1_ext_rst_n_o" LOC = "E15";
-NET "fd1_ext_rst_n_o" IOSTANDARD = "LVCMOS25";
-NET "fd1_pll_status_i" LOC = "F14";
-NET "fd1_pll_status_i" IOSTANDARD = "LVCMOS25";
-NET "fd1_dmtd_fb_out_i" LOC = "H14";
-NET "fd1_dmtd_fb_out_i" IOSTANDARD = "LVCMOS25";
-NET "fd1_tdc_rd_n_o" LOC = "A15";
-NET "fd1_tdc_rd_n_o" IOSTANDARD = "LVCMOS25";
-NET "fd1_tdc_emptyf_i" LOC = "E19";
-NET "fd1_tdc_emptyf_i" IOSTANDARD = "LVCMOS25";
-NET "fd1_onewire_b" LOC = "G16";
-NET "fd1_onewire_b" IOSTANDARD = "LVCMOS25";
-NET "fd1_tdc_d_b[27]" LOC = "E17";
-NET "fd1_tdc_d_b[27]" IOSTANDARD = "LVCMOS25";
-NET "fd1_tdc_d_b[25]" LOC = "F18";
-NET "fd1_tdc_d_b[25]" IOSTANDARD = "LVCMOS25";
-NET "fd1_tdc_d_b[21]" LOC = "E21";
-NET "fd1_tdc_d_b[21]" IOSTANDARD = "LVCMOS25";
-NET "fd1_tdc_d_b[23]" LOC = "F20";
-NET "fd1_tdc_d_b[23]" IOSTANDARD = "LVCMOS25";
-NET "fd1_tdc_d_b[19]" LOC = "K21";
-NET "fd1_tdc_d_b[19]" IOSTANDARD = "LVCMOS25";
-NET "fd1_tdc_d_b[17]" LOC = "L20";
-NET "fd1_tdc_d_b[17]" IOSTANDARD = "LVCMOS25";
-NET "fd1_tdc_d_b[11]" LOC = "E23";
-NET "fd1_tdc_d_b[11]" IOSTANDARD = "LVCMOS25";
-NET "fd1_tdc_d_b[15]" LOC = "F22";
-NET "fd1_tdc_d_b[15]" IOSTANDARD = "LVCMOS25";
-NET "fd1_tdc_d_b[9]" LOC = "A25";
-NET "fd1_tdc_d_b[9]" IOSTANDARD = "LVCMOS25";
-NET "fd1_tdc_d_b[13]" LOC = "L19";
-NET "fd1_tdc_d_b[13]" IOSTANDARD = "LVCMOS25";
-NET "fd1_tdc_d_b[1]" LOC = "C24";
-NET "fd1_tdc_d_b[1]" IOSTANDARD = "LVCMOS25";
-NET "fd1_tdc_d_b[4]" LOC = "D25";
-NET "fd1_tdc_d_b[4]" IOSTANDARD = "LVCMOS25";
-NET "fd1_tdc_d_b[6]" LOC = "H22";
-NET "fd1_tdc_d_b[6]" IOSTANDARD = "LVCMOS25";
-NET "fd1_tdc_d_b[0]" LOC = "G21";
-NET "fd1_tdc_d_b[0]" IOSTANDARD = "LVCMOS25";
-NET "fd1_dmtd_fb_in_i" LOC = "A16";
-NET "fd1_dmtd_fb_in_i" IOSTANDARD = "LVCMOS25";
-# ucfgen pin assignments for mezzanine fmc-delay-v4 slot 1
-NET "fd0_clk_ref_p_i" LOC = "AH16";
+NET "fd0_clk_ref_p_i" LOC = "E16";
 NET "fd0_clk_ref_p_i" IOSTANDARD = "LVDS_25";
-NET "fd0_clk_ref_n_i" LOC = "AK16";
+NET "fd0_clk_ref_n_i" LOC = "D16";
 NET "fd0_clk_ref_n_i" IOSTANDARD = "LVDS_25";
-NET "fd0_tdc_start_p_i" LOC = "AF16";
+NET "fd0_tdc_start_p_i" LOC = "H15";
 NET "fd0_tdc_start_p_i" IOSTANDARD = "LVDS_25";
-NET "fd0_tdc_start_n_i" LOC = "AG16";
+NET "fd0_tdc_start_n_i" LOC = "G15";
 NET "fd0_tdc_start_n_i" IOSTANDARD = "LVDS_25";
-NET "fd0_delay_len_o[3]" LOC = "AB21";
+NET "fd0_delay_len_o[3]" LOC = "G10";
 NET "fd0_delay_len_o[3]" IOSTANDARD = "LVCMOS25";
-NET "fd0_delay_len_o[2]" LOC = "AC21";
+NET "fd0_delay_len_o[2]" LOC = "F10";
 NET "fd0_delay_len_o[2]" IOSTANDARD = "LVCMOS25";
-NET "fd0_delay_len_o[1]" LOC = "AD24";
+NET "fd0_delay_len_o[1]" LOC = "E9";
 NET "fd0_delay_len_o[1]" IOSTANDARD = "LVCMOS25";
-NET "fd0_delay_len_o[0]" LOC = "AC24";
+NET "fd0_delay_len_o[0]" LOC = "F9";
 NET "fd0_delay_len_o[0]" IOSTANDARD = "LVCMOS25";
-NET "fd0_delay_pulse_o[3]" LOC = "AE22";
+NET "fd0_delay_pulse_o[3]" LOC = "F12";
 NET "fd0_delay_pulse_o[3]" IOSTANDARD = "LVCMOS25";
-NET "fd0_delay_pulse_o[1]" LOC = "AD17";
+NET "fd0_delay_pulse_o[1]" LOC = "E11";
 NET "fd0_delay_pulse_o[1]" IOSTANDARD = "LVCMOS25";
-NET "fd0_delay_pulse_o[2]" LOC = "AD22";
+NET "fd0_delay_pulse_o[2]" LOC = "G12";
 NET "fd0_delay_pulse_o[2]" IOSTANDARD = "LVCMOS25";
-NET "fd0_delay_pulse_o[0]" LOC = "AB17";
+NET "fd0_delay_pulse_o[0]" LOC = "F11";
 NET "fd0_delay_pulse_o[0]" IOSTANDARD = "LVCMOS25";
-NET "fd0_delay_val_o[3]" LOC = "AA19";
+NET "fd0_delay_val_o[3]" LOC = "J12";
 NET "fd0_delay_val_o[3]" IOSTANDARD = "LVCMOS25";
-NET "fd0_delay_val_o[1]" LOC = "W19";
+NET "fd0_delay_val_o[1]" LOC = "H11";
 NET "fd0_delay_val_o[1]" IOSTANDARD = "LVCMOS25";
-NET "fd0_delay_val_o[7]" LOC = "Y21";
+NET "fd0_delay_val_o[7]" LOC = "L11";
 NET "fd0_delay_val_o[7]" IOSTANDARD = "LVCMOS25";
-NET "fd0_delay_val_o[5]" LOC = "W20";
+NET "fd0_delay_val_o[5]" LOC = "J13";
 NET "fd0_delay_val_o[5]" IOSTANDARD = "LVCMOS25";
-NET "fd0_delay_val_o[9]" LOC = "AA22";
+NET "fd0_delay_val_o[9]" LOC = "L12";
 NET "fd0_delay_val_o[9]" IOSTANDARD = "LVCMOS25";
-NET "fd0_spi_mosi_o" LOC = "AB20";
+NET "fd0_spi_mosi_o" LOC = "M13";
 NET "fd0_spi_mosi_o" IOSTANDARD = "LVCMOS25";
-NET "fd0_spi_sclk_o" LOC = "AC19";
+NET "fd0_spi_sclk_o" LOC = "L14";
 NET "fd0_spi_sclk_o" IOSTANDARD = "LVCMOS25";
-NET "fd0_tdc_oe_n_o" LOC = "AF25";
+NET "fd0_tdc_oe_n_o" LOC = "M15";
 NET "fd0_tdc_oe_n_o" IOSTANDARD = "LVCMOS25";
-NET "fd0_tdc_start_dis_o" LOC = "AE24";
+NET "fd0_tdc_start_dis_o" LOC = "F13";
 NET "fd0_tdc_start_dis_o" IOSTANDARD = "LVCMOS25";
-NET "fd0_spi_cs_gpio_n_o" LOC = "AE19";
+NET "fd0_spi_cs_gpio_n_o" LOC = "F15";
 NET "fd0_spi_cs_gpio_n_o" IOSTANDARD = "LVCMOS25";
-NET "fd0_tdc_cal_pulse_o" LOC = "AE23";
+NET "fd0_tdc_cal_pulse_o" LOC = "G14";
 NET "fd0_tdc_cal_pulse_o" IOSTANDARD = "LVCMOS25";
-NET "fd0_dmtd_clk_o" LOC = "AE21";
+NET "fd0_dmtd_clk_o" LOC = "J14";
 NET "fd0_dmtd_clk_o" IOSTANDARD = "LVCMOS25";
-NET "fd0_tdc_wr_n_o" LOC = "AC16";
+NET "fd0_tdc_wr_n_o" LOC = "B15";
 NET "fd0_tdc_wr_n_o" IOSTANDARD = "LVCMOS25";
-NET "fd0_tdc_alutrigger_o" LOC = "AB14";
+NET "fd0_tdc_alutrigger_o" LOC = "F19";
 NET "fd0_tdc_alutrigger_o" IOSTANDARD = "LVCMOS25";
-NET "fd0_led_trig_o" LOC = "Y17";
+NET "fd0_led_trig_o" LOC = "H16";
 NET "fd0_led_trig_o" IOSTANDARD = "LVCMOS25";
-NET "fd0_tdc_d_b[26]" LOC = "Y15";
+NET "fd0_tdc_d_b[26]" LOC = "F17";
 NET "fd0_tdc_d_b[26]" IOSTANDARD = "LVCMOS25";
-NET "fd0_tdc_d_b[24]" LOC = "AC15";
+NET "fd0_tdc_d_b[24]" LOC = "G18";
 NET "fd0_tdc_d_b[24]" IOSTANDARD = "LVCMOS25";
-NET "fd0_tdc_d_b[20]" LOC = "AE15";
+NET "fd0_tdc_d_b[20]" LOC = "F21";
 NET "fd0_tdc_d_b[20]" IOSTANDARD = "LVCMOS25";
-NET "fd0_tdc_d_b[22]" LOC = "Y16";
+NET "fd0_tdc_d_b[22]" LOC = "G20";
 NET "fd0_tdc_d_b[22]" IOSTANDARD = "LVCMOS25";
-NET "fd0_tdc_d_b[18]" LOC = "Y14";
+NET "fd0_tdc_d_b[18]" LOC = "L21";
 NET "fd0_tdc_d_b[18]" IOSTANDARD = "LVCMOS25";
-NET "fd0_tdc_d_b[16]" LOC = "W14";
+NET "fd0_tdc_d_b[16]" LOC = "M20";
 NET "fd0_tdc_d_b[16]" IOSTANDARD = "LVCMOS25";
-NET "fd0_tdc_d_b[10]" LOC = "AB12";
+NET "fd0_tdc_d_b[10]" LOC = "F23";
 NET "fd0_tdc_d_b[10]" IOSTANDARD = "LVCMOS25";
-NET "fd0_tdc_d_b[14]" LOC = "AD12";
+NET "fd0_tdc_d_b[14]" LOC = "G22";
 NET "fd0_tdc_d_b[14]" IOSTANDARD = "LVCMOS25";
-NET "fd0_tdc_d_b[8]" LOC = "AD10";
+NET "fd0_tdc_d_b[8]" LOC = "B25";
 NET "fd0_tdc_d_b[8]" IOSTANDARD = "LVCMOS25";
-NET "fd0_tdc_d_b[12]" LOC = "AE11";
+NET "fd0_tdc_d_b[12]" LOC = "M19";
 NET "fd0_tdc_d_b[12]" IOSTANDARD = "LVCMOS25";
-NET "fd0_tdc_d_b[3]" LOC = "AJ15";
+NET "fd0_tdc_d_b[3]" LOC = "D24";
 NET "fd0_tdc_d_b[3]" IOSTANDARD = "LVCMOS25";
-NET "fd0_tdc_d_b[5]" LOC = "AE13";
+NET "fd0_tdc_d_b[5]" LOC = "E25";
 NET "fd0_tdc_d_b[5]" IOSTANDARD = "LVCMOS25";
-NET "fd0_tdc_d_b[7]" LOC = "AC11";
+NET "fd0_tdc_d_b[7]" LOC = "J22";
 NET "fd0_tdc_d_b[7]" IOSTANDARD = "LVCMOS25";
-NET "fd0_tdc_d_b[2]" LOC = "AG8";
+NET "fd0_tdc_d_b[2]" LOC = "H21";
 NET "fd0_tdc_d_b[2]" IOSTANDARD = "LVCMOS25";
-NET "fd0_trig_a_i" LOC = "AJ17";
+NET "fd0_trig_a_i" LOC = "C16";
 NET "fd0_trig_a_i" IOSTANDARD = "LVCMOS25";
-NET "fd0_delay_val_o[2]" LOC = "AB19";
+NET "fd0_delay_val_o[2]" LOC = "H12";
 NET "fd0_delay_val_o[2]" IOSTANDARD = "LVCMOS25";
-NET "fd0_delay_val_o[0]" LOC = "Y19";
+NET "fd0_delay_val_o[0]" LOC = "G11";
 NET "fd0_delay_val_o[0]" IOSTANDARD = "LVCMOS25";
-NET "fd0_delay_val_o[6]" LOC = "AA21";
+NET "fd0_delay_val_o[6]" LOC = "K11";
 NET "fd0_delay_val_o[6]" IOSTANDARD = "LVCMOS25";
-NET "fd0_delay_val_o[4]" LOC = "Y20";
+NET "fd0_delay_val_o[4]" LOC = "H13";
 NET "fd0_delay_val_o[4]" IOSTANDARD = "LVCMOS25";
-NET "fd0_delay_val_o[8]" LOC = "AC22";
+NET "fd0_delay_val_o[8]" LOC = "K12";
 NET "fd0_delay_val_o[8]" IOSTANDARD = "LVCMOS25";
-NET "fd0_spi_miso_i" LOC = "AC20";
+NET "fd0_spi_miso_i" LOC = "L13";
 NET "fd0_spi_miso_i" IOSTANDARD = "LVCMOS25";
-NET "fd0_spi_cs_pll_n_o" LOC = "AD19";
+NET "fd0_spi_cs_pll_n_o" LOC = "K14";
 NET "fd0_spi_cs_pll_n_o" IOSTANDARD = "LVCMOS25";
-NET "fd0_spi_cs_dac_n_o" LOC = "AG25";
+NET "fd0_spi_cs_dac_n_o" LOC = "K15";
 NET "fd0_spi_cs_dac_n_o" IOSTANDARD = "LVCMOS25";
-NET "fd0_tdc_stop_dis_o" LOC = "AF24";
+NET "fd0_tdc_stop_dis_o" LOC = "E13";
 NET "fd0_tdc_stop_dis_o" IOSTANDARD = "LVCMOS25";
-NET "fd0_ext_rst_n_o" LOC = "AF19";
+NET "fd0_ext_rst_n_o" LOC = "E15";
 NET "fd0_ext_rst_n_o" IOSTANDARD = "LVCMOS25";
-NET "fd0_pll_status_i" LOC = "AF23";
+NET "fd0_pll_status_i" LOC = "F14";
 NET "fd0_pll_status_i" IOSTANDARD = "LVCMOS25";
-NET "fd0_dmtd_fb_out_i" LOC = "AF21";
+NET "fd0_dmtd_fb_out_i" LOC = "H14";
 NET "fd0_dmtd_fb_out_i" IOSTANDARD = "LVCMOS25";
-NET "fd0_tdc_rd_n_o" LOC = "AD16";
+NET "fd0_tdc_rd_n_o" LOC = "A15";
 NET "fd0_tdc_rd_n_o" IOSTANDARD = "LVCMOS25";
-NET "fd0_tdc_emptyf_i" LOC = "AC14";
+NET "fd0_tdc_emptyf_i" LOC = "E19";
 NET "fd0_tdc_emptyf_i" IOSTANDARD = "LVCMOS25";
-NET "fd0_onewire_b" LOC = "AA17";
+NET "fd0_onewire_b" LOC = "G16";
 NET "fd0_onewire_b" IOSTANDARD = "LVCMOS25";
-NET "fd0_tdc_d_b[27]" LOC = "AA15";
+NET "fd0_tdc_d_b[27]" LOC = "E17";
 NET "fd0_tdc_d_b[27]" IOSTANDARD = "LVCMOS25";
-NET "fd0_tdc_d_b[25]" LOC = "AD15";
+NET "fd0_tdc_d_b[25]" LOC = "F18";
 NET "fd0_tdc_d_b[25]" IOSTANDARD = "LVCMOS25";
-NET "fd0_tdc_d_b[21]" LOC = "AF15";
+NET "fd0_tdc_d_b[21]" LOC = "E21";
 NET "fd0_tdc_d_b[21]" IOSTANDARD = "LVCMOS25";
-NET "fd0_tdc_d_b[23]" LOC = "AB16";
+NET "fd0_tdc_d_b[23]" LOC = "F20";
 NET "fd0_tdc_d_b[23]" IOSTANDARD = "LVCMOS25";
-NET "fd0_tdc_d_b[19]" LOC = "AA14";
+NET "fd0_tdc_d_b[19]" LOC = "K21";
 NET "fd0_tdc_d_b[19]" IOSTANDARD = "LVCMOS25";
-NET "fd0_tdc_d_b[17]" LOC = "Y13";
+NET "fd0_tdc_d_b[17]" LOC = "L20";
 NET "fd0_tdc_d_b[17]" IOSTANDARD = "LVCMOS25";
-NET "fd0_tdc_d_b[11]" LOC = "AC12";
+NET "fd0_tdc_d_b[11]" LOC = "E23";
 NET "fd0_tdc_d_b[11]" IOSTANDARD = "LVCMOS25";
-NET "fd0_tdc_d_b[15]" LOC = "AE12";
+NET "fd0_tdc_d_b[15]" LOC = "F22";
 NET "fd0_tdc_d_b[15]" IOSTANDARD = "LVCMOS25";
-NET "fd0_tdc_d_b[9]" LOC = "AE10";
+NET "fd0_tdc_d_b[9]" LOC = "A25";
 NET "fd0_tdc_d_b[9]" IOSTANDARD = "LVCMOS25";
-NET "fd0_tdc_d_b[13]" LOC = "AF11";
+NET "fd0_tdc_d_b[13]" LOC = "L19";
 NET "fd0_tdc_d_b[13]" IOSTANDARD = "LVCMOS25";
-NET "fd0_tdc_d_b[1]" LOC = "AK15";
+NET "fd0_tdc_d_b[1]" LOC = "C24";
 NET "fd0_tdc_d_b[1]" IOSTANDARD = "LVCMOS25";
-NET "fd0_tdc_d_b[4]" LOC = "AF13";
+NET "fd0_tdc_d_b[4]" LOC = "D25";
 NET "fd0_tdc_d_b[4]" IOSTANDARD = "LVCMOS25";
-NET "fd0_tdc_d_b[6]" LOC = "AD11";
+NET "fd0_tdc_d_b[6]" LOC = "H22";
 NET "fd0_tdc_d_b[6]" IOSTANDARD = "LVCMOS25";
-NET "fd0_tdc_d_b[0]" LOC = "AH8";
+NET "fd0_tdc_d_b[0]" LOC = "G21";
 NET "fd0_tdc_d_b[0]" IOSTANDARD = "LVCMOS25";
-NET "fd0_dmtd_fb_in_i" LOC = "AK17";
+NET "fd0_dmtd_fb_in_i" LOC = "A16";
 NET "fd0_dmtd_fb_in_i" IOSTANDARD = "LVCMOS25";
+
+# ucfgen pin assignments for mezzanine fmc-delay-v4 slot 1
+NET "fd1_clk_ref_p_i" LOC = "AH16";
+NET "fd1_clk_ref_p_i" IOSTANDARD = "LVDS_25";
+NET "fd1_clk_ref_n_i" LOC = "AK16";
+NET "fd1_clk_ref_n_i" IOSTANDARD = "LVDS_25";
+NET "fd1_tdc_start_p_i" LOC = "AF16";
+NET "fd1_tdc_start_p_i" IOSTANDARD = "LVDS_25";
+NET "fd1_tdc_start_n_i" LOC = "AG16";
+NET "fd1_tdc_start_n_i" IOSTANDARD = "LVDS_25";
+NET "fd1_delay_len_o[3]" LOC = "AB21";
+NET "fd1_delay_len_o[3]" IOSTANDARD = "LVCMOS25";
+NET "fd1_delay_len_o[2]" LOC = "AC21";
+NET "fd1_delay_len_o[2]" IOSTANDARD = "LVCMOS25";
+NET "fd1_delay_len_o[1]" LOC = "AD24";
+NET "fd1_delay_len_o[1]" IOSTANDARD = "LVCMOS25";
+NET "fd1_delay_len_o[0]" LOC = "AC24";
+NET "fd1_delay_len_o[0]" IOSTANDARD = "LVCMOS25";
+NET "fd1_delay_pulse_o[3]" LOC = "AE22";
+NET "fd1_delay_pulse_o[3]" IOSTANDARD = "LVCMOS25";
+NET "fd1_delay_pulse_o[1]" LOC = "AD17";
+NET "fd1_delay_pulse_o[1]" IOSTANDARD = "LVCMOS25";
+NET "fd1_delay_pulse_o[2]" LOC = "AD22";
+NET "fd1_delay_pulse_o[2]" IOSTANDARD = "LVCMOS25";
+NET "fd1_delay_pulse_o[0]" LOC = "AB17";
+NET "fd1_delay_pulse_o[0]" IOSTANDARD = "LVCMOS25";
+NET "fd1_delay_val_o[3]" LOC = "AA19";
+NET "fd1_delay_val_o[3]" IOSTANDARD = "LVCMOS25";
+NET "fd1_delay_val_o[1]" LOC = "W19";
+NET "fd1_delay_val_o[1]" IOSTANDARD = "LVCMOS25";
+NET "fd1_delay_val_o[7]" LOC = "Y21";
+NET "fd1_delay_val_o[7]" IOSTANDARD = "LVCMOS25";
+NET "fd1_delay_val_o[5]" LOC = "W20";
+NET "fd1_delay_val_o[5]" IOSTANDARD = "LVCMOS25";
+NET "fd1_delay_val_o[9]" LOC = "AA22";
+NET "fd1_delay_val_o[9]" IOSTANDARD = "LVCMOS25";
+NET "fd1_spi_mosi_o" LOC = "AB20";
+NET "fd1_spi_mosi_o" IOSTANDARD = "LVCMOS25";
+NET "fd1_spi_sclk_o" LOC = "AC19";
+NET "fd1_spi_sclk_o" IOSTANDARD = "LVCMOS25";
+NET "fd1_tdc_oe_n_o" LOC = "AF25";
+NET "fd1_tdc_oe_n_o" IOSTANDARD = "LVCMOS25";
+NET "fd1_tdc_start_dis_o" LOC = "AE24";
+NET "fd1_tdc_start_dis_o" IOSTANDARD = "LVCMOS25";
+NET "fd1_spi_cs_gpio_n_o" LOC = "AE19";
+NET "fd1_spi_cs_gpio_n_o" IOSTANDARD = "LVCMOS25";
+NET "fd1_tdc_cal_pulse_o" LOC = "AE23";
+NET "fd1_tdc_cal_pulse_o" IOSTANDARD = "LVCMOS25";
+NET "fd1_dmtd_clk_o" LOC = "AE21";
+NET "fd1_dmtd_clk_o" IOSTANDARD = "LVCMOS25";
+NET "fd1_tdc_wr_n_o" LOC = "AC16";
+NET "fd1_tdc_wr_n_o" IOSTANDARD = "LVCMOS25";
+NET "fd1_tdc_alutrigger_o" LOC = "AB14";
+NET "fd1_tdc_alutrigger_o" IOSTANDARD = "LVCMOS25";
+NET "fd1_led_trig_o" LOC = "Y17";
+NET "fd1_led_trig_o" IOSTANDARD = "LVCMOS25";
+NET "fd1_tdc_d_b[26]" LOC = "Y15";
+NET "fd1_tdc_d_b[26]" IOSTANDARD = "LVCMOS25";
+NET "fd1_tdc_d_b[24]" LOC = "AC15";
+NET "fd1_tdc_d_b[24]" IOSTANDARD = "LVCMOS25";
+NET "fd1_tdc_d_b[20]" LOC = "AE15";
+NET "fd1_tdc_d_b[20]" IOSTANDARD = "LVCMOS25";
+NET "fd1_tdc_d_b[22]" LOC = "Y16";
+NET "fd1_tdc_d_b[22]" IOSTANDARD = "LVCMOS25";
+NET "fd1_tdc_d_b[18]" LOC = "Y14";
+NET "fd1_tdc_d_b[18]" IOSTANDARD = "LVCMOS25";
+NET "fd1_tdc_d_b[16]" LOC = "W14";
+NET "fd1_tdc_d_b[16]" IOSTANDARD = "LVCMOS25";
+NET "fd1_tdc_d_b[10]" LOC = "AB12";
+NET "fd1_tdc_d_b[10]" IOSTANDARD = "LVCMOS25";
+NET "fd1_tdc_d_b[14]" LOC = "AD12";
+NET "fd1_tdc_d_b[14]" IOSTANDARD = "LVCMOS25";
+NET "fd1_tdc_d_b[8]" LOC = "AD10";
+NET "fd1_tdc_d_b[8]" IOSTANDARD = "LVCMOS25";
+NET "fd1_tdc_d_b[12]" LOC = "AE11";
+NET "fd1_tdc_d_b[12]" IOSTANDARD = "LVCMOS25";
+NET "fd1_tdc_d_b[3]" LOC = "AJ15";
+NET "fd1_tdc_d_b[3]" IOSTANDARD = "LVCMOS25";
+NET "fd1_tdc_d_b[5]" LOC = "AE13";
+NET "fd1_tdc_d_b[5]" IOSTANDARD = "LVCMOS25";
+NET "fd1_tdc_d_b[7]" LOC = "AC11";
+NET "fd1_tdc_d_b[7]" IOSTANDARD = "LVCMOS25";
+NET "fd1_tdc_d_b[2]" LOC = "AG8";
+NET "fd1_tdc_d_b[2]" IOSTANDARD = "LVCMOS25";
+NET "fd1_trig_a_i" LOC = "AJ17";
+NET "fd1_trig_a_i" IOSTANDARD = "LVCMOS25";
+NET "fd1_delay_val_o[2]" LOC = "AB19";
+NET "fd1_delay_val_o[2]" IOSTANDARD = "LVCMOS25";
+NET "fd1_delay_val_o[0]" LOC = "Y19";
+NET "fd1_delay_val_o[0]" IOSTANDARD = "LVCMOS25";
+NET "fd1_delay_val_o[6]" LOC = "AA21";
+NET "fd1_delay_val_o[6]" IOSTANDARD = "LVCMOS25";
+NET "fd1_delay_val_o[4]" LOC = "Y20";
+NET "fd1_delay_val_o[4]" IOSTANDARD = "LVCMOS25";
+NET "fd1_delay_val_o[8]" LOC = "AC22";
+NET "fd1_delay_val_o[8]" IOSTANDARD = "LVCMOS25";
+NET "fd1_spi_miso_i" LOC = "AC20";
+NET "fd1_spi_miso_i" IOSTANDARD = "LVCMOS25";
+NET "fd1_spi_cs_pll_n_o" LOC = "AD19";
+NET "fd1_spi_cs_pll_n_o" IOSTANDARD = "LVCMOS25";
+NET "fd1_spi_cs_dac_n_o" LOC = "AG25";
+NET "fd1_spi_cs_dac_n_o" IOSTANDARD = "LVCMOS25";
+NET "fd1_tdc_stop_dis_o" LOC = "AF24";
+NET "fd1_tdc_stop_dis_o" IOSTANDARD = "LVCMOS25";
+NET "fd1_ext_rst_n_o" LOC = "AF19";
+NET "fd1_ext_rst_n_o" IOSTANDARD = "LVCMOS25";
+NET "fd1_pll_status_i" LOC = "AF23";
+NET "fd1_pll_status_i" IOSTANDARD = "LVCMOS25";
+NET "fd1_dmtd_fb_out_i" LOC = "AF21";
+NET "fd1_dmtd_fb_out_i" IOSTANDARD = "LVCMOS25";
+NET "fd1_tdc_rd_n_o" LOC = "AD16";
+NET "fd1_tdc_rd_n_o" IOSTANDARD = "LVCMOS25";
+NET "fd1_tdc_emptyf_i" LOC = "AC14";
+NET "fd1_tdc_emptyf_i" IOSTANDARD = "LVCMOS25";
+NET "fd1_onewire_b" LOC = "AA17";
+NET "fd1_onewire_b" IOSTANDARD = "LVCMOS25";
+NET "fd1_tdc_d_b[27]" LOC = "AA15";
+NET "fd1_tdc_d_b[27]" IOSTANDARD = "LVCMOS25";
+NET "fd1_tdc_d_b[25]" LOC = "AD15";
+NET "fd1_tdc_d_b[25]" IOSTANDARD = "LVCMOS25";
+NET "fd1_tdc_d_b[21]" LOC = "AF15";
+NET "fd1_tdc_d_b[21]" IOSTANDARD = "LVCMOS25";
+NET "fd1_tdc_d_b[23]" LOC = "AB16";
+NET "fd1_tdc_d_b[23]" IOSTANDARD = "LVCMOS25";
+NET "fd1_tdc_d_b[19]" LOC = "AA14";
+NET "fd1_tdc_d_b[19]" IOSTANDARD = "LVCMOS25";
+NET "fd1_tdc_d_b[17]" LOC = "Y13";
+NET "fd1_tdc_d_b[17]" IOSTANDARD = "LVCMOS25";
+NET "fd1_tdc_d_b[11]" LOC = "AC12";
+NET "fd1_tdc_d_b[11]" IOSTANDARD = "LVCMOS25";
+NET "fd1_tdc_d_b[15]" LOC = "AE12";
+NET "fd1_tdc_d_b[15]" IOSTANDARD = "LVCMOS25";
+NET "fd1_tdc_d_b[9]" LOC = "AE10";
+NET "fd1_tdc_d_b[9]" IOSTANDARD = "LVCMOS25";
+NET "fd1_tdc_d_b[13]" LOC = "AF11";
+NET "fd1_tdc_d_b[13]" IOSTANDARD = "LVCMOS25";
+NET "fd1_tdc_d_b[1]" LOC = "AK15";
+NET "fd1_tdc_d_b[1]" IOSTANDARD = "LVCMOS25";
+NET "fd1_tdc_d_b[4]" LOC = "AF13";
+NET "fd1_tdc_d_b[4]" IOSTANDARD = "LVCMOS25";
+NET "fd1_tdc_d_b[6]" LOC = "AD11";
+NET "fd1_tdc_d_b[6]" IOSTANDARD = "LVCMOS25";
+NET "fd1_tdc_d_b[0]" LOC = "AH8";
+NET "fd1_tdc_d_b[0]" IOSTANDARD = "LVCMOS25";
+NET "fd1_dmtd_fb_in_i" LOC = "AK17";
+NET "fd1_dmtd_fb_in_i" IOSTANDARD = "LVCMOS25";
 # <ucfgen_end>
--- a/hdl/top/svec/wr/svec_top.vhd
+++ b/hdl/top/svec/wr/svec_top.vhd
@@ -6,7 +6,7 @@
 -- Author     : Tomasz Wlostowski
 -- Company    : CERN
 -- Created    : 2011-08-24
-- Last update: 2013-02-21
+-- Last update: 2013-05-17
 -- Platform   : FPGA-generic
 -- Standard   : VHDL'93
 -------------------------------------------------------------------------------
@@ -51,6 +51,8 @@ use work.fine_delay_pkg.all;
 use work.etherbone_pkg.all;
 use work.wr_xilinx_pkg.all;

+use work.synthesis_descriptor.all;
+
 library UNISIM;
 use UNISIM.vcomponents.all;

@@ -142,8 +144,6 @@ entity svec_top is

      tempid_dq_b : inout std_logic;

-      fp_ledn_o : out std_logic_vector(7 downto 0);
-
      -------------------------------------------------------------------------
      -- Fine Delay Pins
      -------------------------------------------------------------------------
@@ -237,7 +237,6 @@ architecture rtl of svec_top is
    port (
      clk_i           : in  std_logic;
      rst_n_i         : in  std_logic;
-      rst_n_o         : out std_logic;
      VME_AS_n_i      : in  std_logic;
      VME_RST_n_i     : in  std_logic;
      VME_WRITE_n_i   : in  std_logic;
@@ -302,8 +301,6 @@ architecture rtl of svec_top is
  signal VME_ADDR_b_out                                        : std_logic_vector(31 downto 1);
  signal VME_LWORD_n_b_out, VME_DATA_DIR_int, VME_ADDR_DIR_int : std_logic;

-
-
  signal dac_hpll_load_p1 : std_logic;
  signal dac_dpll_load_p1 : std_logic;
  signal dac_hpll_data    : std_logic_vector(15 downto 0);
@@ -328,38 +325,31 @@ architecture rtl of svec_top is
  constant c_MASTER_VME       : integer := 0;
  constant c_MASTER_ETHERBONE : integer := 1;

-  constant c_SLAVE_FD1    : integer := 0;
-  constant c_SLAVE_FD0    : integer := 1;
-  constant c_SLAVE_WRCORE : integer := 2;
-  constant c_SLAVE_VIC    : integer := 3;
-
-  constant c_WRCORE_BRIDGE_SDB : t_sdb_bridge := f_xwb_bridge_manual_sdb(x"0003ffff", x"00040000");
-
-  constant c_xwb_vic_sdb : t_sdb_device := (
-    abi_class     => x"0000",              -- undocumented device
-    abi_ver_major => x"01",
-    abi_ver_minor => x"01",
-    wbd_endian    => c_sdb_endian_big,
-    wbd_width     => x"7",                 -- 8/16/32-bit port granularity
-    sdb_component => (
-      addr_first  => x"0000000000000000",
-      addr_last   => x"00000000000000ff",
-      product     => (
-        vendor_id => x"000000000000CE42",  -- CERN
-        device_id => x"00000013",
-        version   => x"00000001",
-        date      => x"20120113",
-        name      => "WB-VIC-Int.Control ")));
-
-  constant c_INTERCONNECT_LAYOUT : t_sdb_record_array(c_NUM_WB_MASTERS-1 downto 0) :=
-    (c_SLAVE_WRCORE => f_sdb_embed_bridge(c_WRCORE_BRIDGE_SDB, x"00040000"),
-     c_SLAVE_FD0    => f_sdb_embed_device(c_FD_SDB_DEVICE, x"00010000"),
-     c_SLAVE_FD1    => f_sdb_embed_device(c_FD_SDB_DEVICE, x"00020000"),
-     c_SLAVE_VIC    => f_sdb_embed_device(c_xwb_vic_sdb, x"00030000")
+  constant c_SLAVE_FD1      : integer := 1;
+  constant c_SLAVE_FD0      : integer := 0;
+  constant c_SLAVE_WRCORE   : integer := 3;
+  constant c_SLAVE_VIC      : integer := 2;
+  constant c_DESC_SYNTHESIS : integer := 4;
+  constant c_DESC_REPO_URL  : integer := 5;
+
+  constant c_WRCORE_BRIDGE_SDB : t_sdb_bridge := f_xwb_bridge_manual_sdb(x"0003ffff", x"00070000");
+
+  constant c_INTERCONNECT_LAYOUT : t_sdb_record_array(c_NUM_WB_MASTERS + 1 downto 0) :=
+    (
+     c_SLAVE_FD0      => f_sdb_embed_device(c_FD_SDB_DEVICE, x"00010000"),
+     c_SLAVE_FD1      => f_sdb_embed_device(c_FD_SDB_DEVICE, x"00020000"),
+     c_SLAVE_VIC      => f_sdb_embed_device(c_xwb_vic_sdb, x"00030000"),
+     c_SLAVE_WRCORE   => f_sdb_embed_bridge(c_WRCORE_BRIDGE_SDB, x"00040000"),
+     c_DESC_SYNTHESIS => f_sdb_embed_synthesis(c_sdb_synthesis_info),
+     c_DESC_REPO_URL  => f_sdb_embed_repo_url(c_sdb_repo_url)
     );

  constant c_SDB_ADDRESS : t_wishbone_address := x"00000000";

+  constant c_VIC_VECTOR_TABLE : t_wishbone_address_array(0 to 1) :=
+    (0 => x"00010000",
+     1 => x"00020000");
+
  signal cnx_master_out : t_wishbone_master_out_array(c_NUM_WB_MASTERS-1 downto 0);
  signal cnx_master_in  : t_wishbone_master_in_array(c_NUM_WB_MASTERS-1 downto 0);

@@ -376,17 +366,14 @@ architecture rtl of svec_top is
  signal tdc1_data_out, tdc1_data_in      : std_logic_vector(27 downto 0);
  signal tdc1_data_oe                     : std_logic;

-  signal tm_link_up          : std_logic;
-  signal tm_utc              : std_logic_vector(39 downto 0);
-  signal tm_cycles           : std_logic_vector(27 downto 0);
-  signal tm_time_valid       : std_logic;
-  signal tm0_clk_aux_lock_en : std_logic;
-  signal tm0_clk_aux_locked  : std_logic;
-  signal tm1_clk_aux_lock_en : std_logic;
-  signal tm1_clk_aux_locked  : std_logic;
-  signal tm_dac_value        : std_logic_vector(23 downto 0);
-  signal tm0_dac_wr          : std_logic;
-  signal tm1_dac_wr          : std_logic;
+  signal tm_link_up         : std_logic;
+  signal tm_utc             : std_logic_vector(39 downto 0);
+  signal tm_cycles          : std_logic_vector(27 downto 0);
+  signal tm_time_valid      : std_logic;
+  signal tm_clk_aux_lock_en : std_logic_vector(1 downto 0);
+  signal tm_clk_aux_locked  : std_logic_vector(1 downto 0);
+  signal tm_dac_value       : std_logic_vector(23 downto 0);
+  signal tm_dac_wr          : std_logic_vector(1 downto 0);

  signal ddr0_pll_reset                  : std_logic;
  signal ddr0_pll_locked, fd0_pll_status : std_logic;
@@ -419,11 +406,8 @@ architecture rtl of svec_top is
  signal vme_master_out : t_wishbone_master_out;
  signal vme_master_in  : t_wishbone_master_in;

-  signal pins    : std_logic_vector(31 downto 0);
-  signal pps     : std_logic;
-
-  signal led_divider : unsigned(22 downto 0);
-  signal leds        : std_logic_vector(7 downto 0);
+  signal pins : std_logic_vector(31 downto 0);
+  signal pps  : std_logic;

  signal vic_master_irq : std_logic;

@@ -674,17 +658,17 @@ begin
      g_phys_uart                 => true,
      g_virtual_uart              => true,
      g_with_external_clock_input => false,
-      g_aux_clks                  => 1,
-      g_ep_rxbuf_size             => 1024,
-      g_dpram_initf               => "wrc.ram",
-      g_dpram_size                => 90112/4,  --16384,
+      g_aux_clks                  => 2,
      g_interface_mode            => PIPELINED,
-      g_address_granularity       => BYTE)
+      g_address_granularity       => BYTE,
+--      g_softpll_enable_debugger   => true,
+      g_dpram_initf               => "none")
    port map (
      clk_sys_i    => clk_sys,
      clk_dmtd_i   => clk_dmtd,
      clk_ref_i    => clk_125m_pllref,
      clk_aux_i(0) => dcm0_clk_ref_0,
+      clk_aux_i(1) => dcm1_clk_ref_0,
      rst_n_i      => local_reset_n,

      dac_hpll_load_p1_o => dac_hpll_load_p1,
@@ -705,8 +689,8 @@ begin
      phy_rst_o          => phy_rst,
      phy_loopen_o       => phy_loopen,

-      led_link_o   => open,
-      led_act_o => open,
+      led_link_o => open,
+      led_act_o  => open,

      scl_o     => wrc_scl_out,
      scl_i     => wrc_scl_in,
@@ -740,9 +724,9 @@ begin

      tm_link_up_o         => tm_link_up,
      tm_dac_value_o       => tm_dac_value,
-      tm_dac_wr_o          => tm0_dac_wr,
-      tm_clk_aux_lock_en_i => tm0_clk_aux_lock_en,
-      tm_clk_aux_locked_o  => tm0_clk_aux_locked,
+      tm_dac_wr_o          => tm_dac_wr(0),
+      tm_clk_aux_lock_en_i => tm_clk_aux_lock_en(0),
+      tm_clk_aux_locked_o  => tm_clk_aux_locked(0),
      tm_time_valid_o      => tm_time_valid,
      tm_tai_o             => tm_utc,
      tm_cycles_o          => tm_cycles,
@@ -821,7 +805,8 @@ begin
    generic map (
      g_interface_mode      => PIPELINED,
      g_address_granularity => BYTE,
-      g_num_interrupts      => 2)
+      g_num_interrupts      => 2,
+      g_init_vectors        => c_VIC_VECTOR_TABLE)
    port map (
      clk_sys_i    => clk_sys,
      rst_n_i      => local_reset_n,
@@ -951,12 +936,11 @@ begin
      tm_time_valid_i      => tm_time_valid,
      tm_cycles_i          => tm_cycles,
      tm_utc_i             => tm_utc,
-      tm_clk_aux_lock_en_o => tm0_clk_aux_lock_en,
-      tm_clk_aux_locked_i  => tm0_clk_aux_locked,
-      tm_clk_dmtd_locked_i => '1',      -- FIXME: fan out real signal from the
--      WRCore
+      tm_clk_aux_lock_en_o => tm_clk_aux_lock_en(0),
+      tm_clk_aux_locked_i  => tm_clk_aux_locked(0),
+      tm_clk_dmtd_locked_i => '1',
      tm_dac_value_i       => tm_dac_value,
-      tm_dac_wr_i          => tm0_dac_wr,
+      tm_dac_wr_i          => tm_dac_wr(0),

      owr_en_o        => fd0_owr_en,
      owr_i           => fd0_owr_in,
@@ -1065,12 +1049,12 @@ begin
      tm_time_valid_i      => tm_time_valid,
      tm_cycles_i          => tm_cycles,
      tm_utc_i             => tm_utc,
-      tm_clk_aux_lock_en_o => tm1_clk_aux_lock_en,
-      tm_clk_aux_locked_i  => tm1_clk_aux_locked,
+      tm_clk_aux_lock_en_o => tm_clk_aux_lock_en(1),
+      tm_clk_aux_locked_i  => tm_clk_aux_locked(1),
      tm_clk_dmtd_locked_i => '1',  --    FIXME: fan out real signal from the
      --    --    WRCore
      tm_dac_value_i       => tm_dac_value,
-      tm_dac_wr_i          => tm1_dac_wr,
+      tm_dac_wr_i          => '0',

      owr_en_o        => fd1_owr_en,
      owr_i           => fd1_owr_in,
@@ -1104,26 +1088,6 @@ begin

  sfp_tx_disable_o <= '0';

-
-  p_drive_leds : process(clk_sys)
-  begin
-    if rising_edge(clk_sys) then
-      
-      if(local_reset_n = '0') then
-        leds        <= "01111111";
-        led_divider <= (others => '0');
-      else
-        led_divider <= led_divider+ 1;
-        if(led_divider = 0) then
-          leds <= leds(6 downto 0) & leds(7);
-        end if;
-        
-      end if;
-    end if;
-  end process;
-
-  fp_ledn_o <= leds;
-  
 end rtl;


--- a/hdl/top/svec/wr/synthesis_descriptor.vhd
+++ b/hdl/top/svec/wr/synthesis_descriptor.vhd
+-------------------------------------------------------------------------------
+-- Title      : Fine Delay FMC SVEC (Simple VME FMC Carrier) SDB descriptor
+-- Project    : Fine Delay FMC (fmc-delay-1ns-4cha)
+-------------------------------------------------------------------------------
+-- File       : synthesis_descriptor.vhd
+-- Author     : Tomasz Wlostowski
+-- Company    : CERN
+-- Created    : 2013-04-16
+-- Last update: 2013-04-16
+-- Platform   : FPGA-generic
+-- Standard   : VHDL'93
+-------------------------------------------------------------------------------
+-- Description: SDB descriptor for the top level of the FD on a SVEC carrier.
+-- Contains synthesis & source repository information.
+-- Warning: this file is modified whenever a synthesis is executed.
+-------------------------------------------------------------------------------
+--
+-- Copyright (c) 2013 CERN / BE-CO-HT
+--
+-- This source file is free software; you can redistribute it   
+-- and/or modify it under the terms of the GNU Lesser General   
+-- Public License as published by the Free Software Foundation; 
+-- either version 2.1 of the License, or (at your option) any   
+-- later version.                                               
+--
+-- This source is distributed in the hope that it will be       
+-- useful, but WITHOUT ANY WARRANTY; without even the implied   
+-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      
+-- PURPOSE.  See the GNU Lesser General Public License for more 
+-- details.                                                     
+--
+-- You should have received a copy of the GNU Lesser General    
+-- Public License along with this source; if not, download it   
+-- from http://www.gnu.org/licenses/lgpl-2.1.html
+--
+-------------------------------------------------------------------------------
+library ieee;
+use ieee.STD_LOGIC_1164.all;
+use work.wishbone_pkg.all;
+
+package synthesis_descriptor is
+  
+constant c_sdb_synthesis_info : t_sdb_synthesis :=
+  (
+    syn_module_name => "fine-delay-svec ",
+    syn_commit_id => "00000000000000000000000000000000",
+    syn_tool_name => "ISE     ",
+    syn_tool_version => x"00000133",
+    syn_date => x"00000000",
+    syn_username => "twlostow       ");
+
+constant c_sdb_repo_url : t_sdb_repo_url :=
+  (
+    repo_url => "git://ohwr.org/fmc-projects/fmc-delay-1ns-8cha.git             " 
+  );
+
+end package synthesis_descriptor;
--- a/hdl/top/svec/wr/xvme64x_core.vhd
+++ b/hdl/top/svec/wr/xvme64x_core.vhd
@@ -9,8 +9,6 @@ entity xvme64x_core is
    clk_i   : in std_logic;
    rst_n_i : in std_logic;

-    rst_n_o : out std_logic;
-
    VME_AS_n_i      : in  std_logic;
    VME_RST_n_i     : in  std_logic;
    VME_WRITE_n_i   : in  std_logic;
@@ -51,12 +49,12 @@ architecture wrapper of xvme64x_core is

  component VME64xCore_Top
    generic (
-      g_wb_data_width      : integer := 32;
+      g_wb_data_width : integer := 32;
      g_wb_addr_width : integer := 64;
-      g_CRAM_SIZE  : integer := 1024);
+      g_CRAM_SIZE     : integer := 1024);
    port (
      clk_i           : in  std_logic;
-      reset_o         : out std_logic;
+      rst_n_i         : in  std_logic;
      VME_AS_n_i      : in  std_logic;
      VME_RST_n_i     : in  std_logic;
      VME_WRITE_n_i   : in  std_logic;
@@ -98,19 +96,16 @@ architecture wrapper of xvme64x_core is
      debug           : out std_logic_vector(7 downto 0));
  end component;

-  signal rst_in, rst_out          : std_logic;
+  signal rst_in, rst_out : std_logic;
  signal dat_out, dat_in : std_logic_vector(31 downto 0);
-  signal adr_out : std_logic_vector(63 downto 0);
+  signal adr_out         : std_logic_vector(63 downto 0);
  
 begin  -- wrapper

-  rst_in  <= not rst_n_i;
-  rst_n_o <= rst_n_i and (not rst_out);
-
  U_Wrapped_VME : VME64xCore_Top
    port map (
      clk_i           => clk_i,
-      reset_o         => rst_out,
+      rst_n_i         => rst_n_i,
      VME_AS_n_i      => VME_AS_n_i,
      VME_RST_n_i     => VME_RST_n_i,
      VME_WRITE_n_i   => VME_WRITE_n_i,
@@ -121,13 +116,13 @@ begin  -- wrapper
      VME_DTACK_n_o   => VME_DTACK_n_o,
      VME_RETRY_n_o   => VME_RETRY_n_o,
      VME_RETRY_OE_o  => VME_RETRY_OE_o,
-      VME_LWORD_n_i => VME_LWORD_n_b_i,
-      VME_LWORD_n_o => VME_LWORD_n_b_o,
-      VME_ADDR_i    => VME_ADDR_b_i,
-      VME_ADDR_o    => VME_ADDR_b_o,
-      VME_DATA_i    => VME_DATA_b_i,
-      VME_DATA_o    => VME_DATA_b_o,
-      VME_IRQ_o     => VME_IRQ_n_o,
+      VME_LWORD_n_i   => VME_LWORD_n_b_i,
+      VME_LWORD_n_o   => VME_LWORD_n_b_o,
+      VME_ADDR_i      => VME_ADDR_b_i,
+      VME_ADDR_o      => VME_ADDR_b_o,
+      VME_DATA_i      => VME_DATA_b_i,
+      VME_DATA_o      => VME_DATA_b_o,
+      VME_IRQ_o       => VME_IRQ_n_o,
      VME_IACKIN_n_i  => VME_IACKIN_n_i,
      VME_IACK_n_i    => VME_IACK_n_i,
      VME_IACKOUT_n_o => VME_IACKOUT_n_o,
@@ -137,18 +132,18 @@ begin  -- wrapper
      VME_ADDR_DIR_o  => VME_ADDR_DIR_o,
      VME_ADDR_OE_N_o => VME_ADDR_OE_N_o,

-      DAT_i   => dat_in,
-      DAT_o   => dat_out,
-      ADR_o   => adr_out,
-      CYC_o   => master_o.cyc,
-      ERR_i   => master_i.err,
-      RTY_i   => master_i.rty,
-      SEL_o   => open,
-      STB_o   => master_o.stb,
-      ACK_i   => master_i.ack,
-      WE_o    => master_o.we,
-      STALL_i => master_i.stall,
-      IRQ_i   => irq_i,
+      DAT_i     => dat_in,
+      DAT_o     => dat_out,
+      ADR_o     => adr_out,
+      CYC_o     => master_o.cyc,
+      ERR_i     => master_i.err,
+      RTY_i     => master_i.rty,
+      SEL_o     => open,
+      STB_o     => master_o.stb,
+      ACK_i     => master_i.ack,
+      WE_o      => master_o.we,
+      STALL_i   => master_i.stall,
+      IRQ_i     => irq_i,
      INT_ack_o => irq_ack_o
      );


--- a/software/include/acam_gpx.h
+++ b/software/include/acam_gpx.h
@@ -20,7 +20,15 @@
 #define AR2_Disable(chan) (1<<(3+chan))
 #define AR2_Adj(chan, value) (((value)&0xf)<<(12+4*(chan-7)))

-#define AR3_RaSpeed(num,val) (val << (num*2 + 21))
+#define AR2_DelRise1(value) (((value)&0x3)<<(20))
+#define AR2_DelFall1(value) (((value)&0x3)<<(22))
+#define AR2_DelRise2(value) (((value)&0x3)<<(24))
+#define AR2_DelFall2(value) (((value)&0x3)<<(26))
+
+#define AR3_DelTx(chan, value) (((value)&0x3)<<(5 + (chan -1 ) * 2))
+#define AR3_RaSpeed(chan, value) (((value)&0x3)<<(21 + (chan ) * 2))
+
+#define AR4_RaSpeed(chan, value) (((value)&0x3)<<(10 + (chan-3) * 2))

 #define AR3_Zero (0) // nothing interesting for the Fine Delay


--- a/software/include/fd_channel_regs.h
+++ b/software/include/fd_channel_regs.h
@@ -3,7 +3,7 @@

  * File           : fd_channel_regs.h
  * Author         : auto-generated by wbgen2 from fd_channel_wishbone_slave.wb
-  * Created        : Wed Apr 11 11:05:22 2012
+  * Created        : Fri Feb 15 12:07:17 2013
  * Standard       : ANSI C

    THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE fd_channel_wishbone_slave.wb
@@ -57,8 +57,8 @@
 /* definitions for field: Disable Fine Part update in reg: Delay Control Register */
 #define FD_DCR_NO_FINE                        WBGEN2_GEN_MASK(7, 1)

-/* definitions for field: Disable Fine Part update in reg: Delay Control Register */
-#define FD_DCR_FORCE_HI                        WBGEN2_GEN_MASK(8, 1)
+/* definitions for field: Force Output High in reg: Delay Control Register */
+#define FD_DCR_FORCE_HI                       WBGEN2_GEN_MASK(8, 1)

 /* definitions for register: Fine Range Register */


--- a/software/include/fd_main_regs.h
+++ b/software/include/fd_main_regs.h
@@ -3,7 +3,7 @@

  * File           : fd_main_regs.h
  * Author         : auto-generated by wbgen2 from fd_main_wishbone_slave.wb
-  * Created        : Mon Jun  4 13:42:20 2012
+  * Created        : Fri Feb 15 12:07:16 2013
  * Standard       : ANSI C

    THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE fd_main_wishbone_slave.wb
@@ -64,7 +64,7 @@
 /* definitions for field: PLL Locked in reg: Global Control Register */
 #define FD_GCR_DDR_LOCKED                     WBGEN2_GEN_MASK(2, 1)

-/* definitions for field: Mezzanice Present in reg: Global Control Register */
+/* definitions for field: Mezzanine Present in reg: Global Control Register */
 #define FD_GCR_FMC_PRESENT                    WBGEN2_GEN_MASK(3, 1)

 /* definitions for register: Timing Control Register */
@@ -99,46 +99,46 @@

 /* definitions for register: Time Register - sub-second 125 MHz clock cycles  */

-/* definitions for register: TDC Data Register */
+/* definitions for register: Host-driven TDC Data Register */

-/* definitions for register: TDC control/status reg */
+/* definitions for register: Host-driven TDC Control/Status */

-/* definitions for field: Start TDC write in reg: TDC control/status reg */
+/* definitions for field: Write to TDC in reg: Host-driven TDC Control/Status */
 #define FD_TDCSR_WRITE                        WBGEN2_GEN_MASK(0, 1)

-/* definitions for field: Start TDC read in reg: TDC control/status reg */
+/* definitions for field: Read from TDC in reg: Host-driven TDC Control/Status */
 #define FD_TDCSR_READ                         WBGEN2_GEN_MASK(1, 1)

-/* definitions for field: Empty flag in reg: TDC control/status reg */
+/* definitions for field: Empty flag in reg: Host-driven TDC Control/Status */
 #define FD_TDCSR_EMPTY                        WBGEN2_GEN_MASK(2, 1)

-/* definitions for field: Start enable in reg: TDC control/status reg */
+/* definitions for field: Stop enable in reg: Host-driven TDC Control/Status */
 #define FD_TDCSR_STOP_EN                      WBGEN2_GEN_MASK(3, 1)

-/* definitions for field: Start disable in reg: TDC control/status reg */
+/* definitions for field: Start disable in reg: Host-driven TDC Control/Status */
 #define FD_TDCSR_START_DIS                    WBGEN2_GEN_MASK(4, 1)

-/* definitions for field: Stop enable in reg: TDC control/status reg */
+/* definitions for field: Start enable in reg: Host-driven TDC Control/Status */
 #define FD_TDCSR_START_EN                     WBGEN2_GEN_MASK(5, 1)

-/* definitions for field: Stop disable in reg: TDC control/status reg */
+/* definitions for field: Stop disable in reg: Host-driven TDC Control/Status */
 #define FD_TDCSR_STOP_DIS                     WBGEN2_GEN_MASK(6, 1)

-/* definitions for field: write 1: Pulse the Alutrigger line in reg: TDC control/status reg */
+/* definitions for field: Pulse <code>Alutrigger</code> line in reg: Host-driven TDC Control/Status */
 #define FD_TDCSR_ALUTRIG                      WBGEN2_GEN_MASK(7, 1)

 /* definitions for register: Calibration register */

-/* definitions for field: Triggers calibration pulses in reg: Calibration register */
+/* definitions for field: Generate calibration pulses (type 1 calibration) in reg: Calibration register */
 #define FD_CALR_CAL_PULSE                     WBGEN2_GEN_MASK(0, 1)

 /* definitions for field: PPS Calibration output enable in reg: Calibration register */
 #define FD_CALR_CAL_PPS                       WBGEN2_GEN_MASK(1, 1)

-/* definitions for field: Produce DDMTD calibration pattern in reg: Calibration register */
+/* definitions for field: Produce DDMTD calibration pattern (type 2 calibration) in reg: Calibration register */
 #define FD_CALR_CAL_DMTD                      WBGEN2_GEN_MASK(2, 1)

-/* definitions for field: Enable pulse generation in reg: Calibration register */
+/* definitions for field: Calibration pulse output select/mask in reg: Calibration register */
 #define FD_CALR_PSEL_MASK                     WBGEN2_GEN_MASK(3, 4)
 #define FD_CALR_PSEL_SHIFT                    3
 #define FD_CALR_PSEL_W(value)                 WBGEN2_GEN_WRITE(value, 3, 4)
@@ -171,16 +171,16 @@
 /* definitions for register: Acam Timestamp Merging Control Register */

 /* definitions for field: Wraparound Coarse Threshold in reg: Acam Timestamp Merging Control Register */
-#define FD_ATMCR_C_THR_MASK                   WBGEN2_GEN_MASK(0, 4)
+#define FD_ATMCR_C_THR_MASK                   WBGEN2_GEN_MASK(0, 8)
 #define FD_ATMCR_C_THR_SHIFT                  0
-#define FD_ATMCR_C_THR_W(value)               WBGEN2_GEN_WRITE(value, 0, 4)
-#define FD_ATMCR_C_THR_R(reg)                 WBGEN2_GEN_READ(reg, 0, 4)
+#define FD_ATMCR_C_THR_W(value)               WBGEN2_GEN_WRITE(value, 0, 8)
+#define FD_ATMCR_C_THR_R(reg)                 WBGEN2_GEN_READ(reg, 0, 8)

 /* definitions for field: Wraparound Fine Threshold in reg: Acam Timestamp Merging Control Register */
-#define FD_ATMCR_F_THR_MASK                   WBGEN2_GEN_MASK(4, 23)
-#define FD_ATMCR_F_THR_SHIFT                  4
-#define FD_ATMCR_F_THR_W(value)               WBGEN2_GEN_WRITE(value, 4, 23)
-#define FD_ATMCR_F_THR_R(reg)                 WBGEN2_GEN_READ(reg, 4, 23)
+#define FD_ATMCR_F_THR_MASK                   WBGEN2_GEN_MASK(8, 23)
+#define FD_ATMCR_F_THR_SHIFT                  8
+#define FD_ATMCR_F_THR_W(value)               WBGEN2_GEN_WRITE(value, 8, 23)
+#define FD_ATMCR_F_THR_R(reg)                 WBGEN2_GEN_READ(reg, 8, 23)

 /* definitions for register: Acam Start Offset Register */

@@ -399,9 +399,9 @@
 #define FD_REG_TM_SECL 0x00000014
 /* [0x18]: REG Time Register - sub-second 125 MHz clock cycles  */
 #define FD_REG_TM_CYCLES 0x00000018
-/* [0x1c]: REG TDC Data Register */
+/* [0x1c]: REG Host-driven TDC Data Register */
 #define FD_REG_TDR 0x0000001c
-/* [0x20]: REG TDC control/status reg */
+/* [0x20]: REG Host-driven TDC Control/Status */
 #define FD_REG_TDCSR 0x00000020
 /* [0x24]: REG Calibration register */
 #define FD_REG_CALR 0x00000024

--- a/software/include/fdelay_lib.h
+++ b/software/include/fdelay_lib.h
@@ -66,6 +66,7 @@ PUBLIC API
 */


+fdelay_device_t *fdelay_create();

 /* Creates a local instance of Fine Delay Core at address base_addr on the SPEC at bus/devfn. Returns 0 on success, negative on error. */
 int spec_fdelay_create_bd(fdelay_device_t *dev, int bus, int dev_fn, uint32_t base);
@@ -117,6 +118,7 @@ int fdelay_configure_capture (fdelay_device_t *dev, int enable, int channel_mask
 int fdelay_read (fdelay_device_t *dev, fdelay_time_t *timestamps, int how_many);


+int fdelay_configure_output(fdelay_device_t *dev, int channel, int enable, int64_t delay_ps, int64_t width_ps, int64_t delta_ps, int rep_count)   ;
 /* (delay mode only) Configures output(s) selected in channel_mask to work in delay mode. Delta_ps = spacing between
 the rising edges of subsequent pulses. */
 int fdelay_configure_delay (fdelay_device_t *dev, int channel_mask, int enable, int64_t delay_ps, int64_t width_ps, int64_t delta_ps, int repeat_count);
@@ -134,5 +136,6 @@ int fdelay_get_time(fdelay_device_t *dev, fdelay_time_t *t);
 int fdelay_set_time(fdelay_device_t *dev, const fdelay_time_t t);

 int fdelay_dmtd_calibration(fdelay_device_t *dev, double *offsets);
+float fdelay_get_board_temperature(fdelay_device_t *dev);

 #endif
--- a/software/include/fdelay_private.h
+++ b/software/include/fdelay_private.h
@@ -31,6 +31,7 @@
 /* ACAM TDC operation modes */
 #define ACAM_RMODE 0
 #define ACAM_IMODE 1
+#define ACAM_GMODE 2

 /* MCP23S17 register addresses (only ones which are used by the lib) */
 #define MCP_IODIR 0x0

--- a/software/lib/Makefile
+++ b/software/lib/Makefile
 SPEC_SW ?= $(shell readlink -f ~/wr-repos/spec-sw)
 ETHERBONE ?= $(shell readlink -f ~/wr-repos/etherbone-core/api)

-OBJS = fdelay_lib.o i2c_master.o onewire.o fdelay_bus.o spec/tools/speclib.o spec/kernel/loader-ll.o fdelay_dmtd_calibration.o simple-eb.o 
+OBJS = fdelay_lib.o i2c_master.o onewire.o fdelay_bus.o fdelay_dmtd_calibration.o sveclib/sveclib.o sveclib/libvmebus.o speclib/speclib.o

-CFLAGS = -I../include -g -Imini_bone -Ispec/tools -Ietherbone
+CFLAGS = -I../include -g -Imini_bone -Ispec/tools -Isveclib -I.

-ifeq ($(SPEC_SW),)
-throw_error:
-	@echo "SPEC software package location environment variable is not set. Can't compile :("
-endif
+#ifeq ($(SPEC_SW),)
+#throw_error:
+#	@echo "SPEC software package location environment variable is not set. Can't compile :("
+#endif

-all:	spec lib
+all:	lib

-spec:	
-		ln -s $(SPEC_SW) spec
-		ln -s $(ETHERBONE) etherbone
+#spec:	
+#		ln -s $(SPEC_SW) spec
+#		ln -s $(ETHERBONE) etherbone

 lib:	$(OBJS)
-		gcc -shared -o libfinedelay.so $(OBJS) -letherbone
+		gcc -shared -o libfinedelay.so $(OBJS) 
 		ar rc libfinedelay.a $(OBJS)

 clean:	

--- a/software/lib/fdelay_bus.c
+++ b/software/lib/fdelay_bus.c
@@ -4,13 +4,24 @@
 #include <getopt.h>

 #include "fdelay_lib.h"
-#include "simple-eb.h"

-#include "spec/tools/speclib.h"
+#include "sveclib/sveclib.h"
+#include "speclib/speclib.h"
+
 #include "fdelay_lib.h"

 void printk() {};

+static void fd_svec_writel(void *priv, uint32_t data, uint32_t addr)
+{
+	svec_writel(priv, data, addr);
+}
+
+static uint32_t fd_svec_readl(void *priv, uint32_t addr)
+{
+	return svec_readl(priv, addr);
+}
+
 static void fd_spec_writel(void *priv, uint32_t data, uint32_t addr)
 {
 	spec_writel(priv, data, addr);
@@ -22,94 +33,79 @@ static uint32_t fd_spec_readl(void *priv, uint32_t addr)
 }

 #if 0
-static int spec_fdelay_create(fdelay_device_t *dev, int bus, int dev_fn)
-{
-	uint32_t base;
+#endif

-	dev->priv_io = spec_open(bus, dev_fn);

-	if(!dev->priv_io)
+
+#define VENDOR_CERN 0xce42
+#define DEVICE_FD_CORE 0xf19ede1a
+#define DEVICE_VUART 0xe2d13d04
+
+static int probe_svec(fdelay_device_t *dev, const char *location)
+{
+	uint32_t map_base;
+	int slot;
+	void *card; 
+	uint32_t core_base;
+
+	if (!strncmp(location, "svec:"), 5) {
+	    sscanf(location+5, "%d,%x,%x", &slot, &map_base, &core_base);
+	} else 
+	    return -1;
+
+	card = svec_open(slot);
+	svec_set_map_base(card, map_base);
+    	if(!card)
 	{
-	 	fprintf(stderr,"Can't map the SPEC @ %x:%x\n", bus, dev_fn);
-	 	return -1;
+		fprintf(stderr,"SVEC probe failed.\n");
+		return -1;
 	}

-	dev->writel = fd_spec_writel;
-	dev->readl = fd_spec_readl;
-	dev->base_addr = base;
+	dev->priv_io = card;
+	dev->writel = fd_svec_writel;
+	dev->readl = fd_svec_readl;
+	dev->base_addr = core_base;

-	//spec_vuart_init(dev->priv_io, 0xe0500); /* for communication with WRCore during DMTD calibration */
-
-    return 0;
+	dbg("svec: using slot %d, A32/D32 base: 0x%x, core base 0x%x\n", slot, map_base, core_base);
+	return 0;
 }
-#endif


-static void fd_eb_writel(void *priv, uint32_t data, uint32_t addr)
-{
-	ebs_write((eb_device_t) priv, addr, data);
-}
+void loader_low_level() {};

-static uint32_t fd_eb_readl(void *priv, uint32_t addr)
+static int probe_spec(fdelay_device_t *dev, const char *location)
 {
-	return ebs_read((eb_device_t) priv, addr);
-}
+	uint32_t core_base;
+	int slot;

+	if (!strncmp(location, "spec:"), 5) {
+	    sscanf(location+5, "%d,%x", &slot, &core_base);
+	} else 
+	    return -1;

+	dev->priv_io = spec_open(slot, -1);

-#define VENDOR_CERN 0xce42
-#define DEVICE_FD_CORE 0xf19ede1a
-#define DEVICE_VUART 0xe2d13d04
+	if(!dev->priv_io)
+	{
+	 	fprintf(stderr,"Can't map the SPEC @ slot %d\n", slot);
+	 	return -1;
+	}
+
+	dev->writel = fd_spec_writel;
+	dev->readl = fd_spec_readl;
+	dev->base_addr = core_base;
+
+	dbg("spec: using slot %d, core base 0x%x\n", slot, core_base);

+        return 0;
+}

 int fdelay_probe(fdelay_device_t *dev, const char *location)
 {
-	int bus = -1, dev_fn = -1;
-	char ip_addr[128];
-	int use_eb = 0;
-	uint32_t base_core;
-
-	if(!strncmp(location, "eb:", 3))
-	{
-		snprintf(ip_addr, sizeof(ip_addr), "udp/%s", location+3);
-		use_eb = 1;
-	} else if (!strncmp(location, "spec:"), 5) {
-		sscanf(location+5, "%d,%d", &bus, &dev_fn);
-	}
-
-	if(use_eb)
-	{
-		dbg("Probing with Etherbone [%s]\n", ip_addr);
-
-		if(	ebs_init() != EB_OK)
-		{
-	 		fprintf(stderr,"Can't initialize Etherbone library.\n");
-	 		return -1;
-		}
-
-		if(ebs_open((eb_device_t*) &dev->priv_io, ip_addr) != EB_OK)
-		{
-		 	fprintf(stderr,"Can't connect to Etherbone device %s.\n", location);
-	 		return -1;
-		}
-
-		if(!ebs_sdb_find_device((eb_device_t ) dev->priv_io, VENDOR_CERN, DEVICE_FD_CORE, 0, &base_core))
-		{
-		 	fprintf(stderr,"Can't detect the FD core. Is the bitstream loaded?\n", location);
-	 		return -1;
-		}
-
-		dev->writel = fd_eb_writel;
-		dev->readl = fd_eb_readl;
-		dev->base_addr = base_core;
-
-		dbg("Found FD core @ 0x%x\n", base_core);
-
-	} else {
-		dbg("Sorry, SPEC temporarily unsupported\n.");
-		return -1;
-	}
-	
+    if(!probe_svec(dev, location))
+    	return 0;
+    if(!probe_spec(dev, location))
+    	return 0;
 }

 fdelay_device_t *fdelay_create()

--- a/software/lib/fdelay_lib.c
+++ b/software/lib/fdelay_lib.c
-/*                             \
+/*                             
 	FmcDelay1ns4Cha (a.k.a. The Fine Delay Card)
 	User-space driver/library

@@ -367,6 +367,7 @@ static void acam_write_reg(fdelay_device_t *dev, uint8_t reg, uint32_t data)
 	acam_set_address(dev, reg);
  fd_writel(data & 0xfffffff, FD_REG_TDR);
  fd_writel(FD_TDCSR_WRITE, FD_REG_TDCSR);
+//  printf("reg %d value 0x%x\n", reg, data);
 }

 /* Calculates the parameters of the ACAM PLL (hsdiv and refdiv)
@@ -483,7 +484,7 @@ static int acam_configure(fdelay_device_t *dev, int mode)
 	int64_t start_tics;
 	const int64_t lock_timeout = 2000000LL;

-	hw->acam_bin = acam_calc_pll(&hsdiv, &refdiv, 80.9553, 31.25e6) / 3.0;
+	hw->acam_bin = acam_calc_pll(&hsdiv, &refdiv, 80.9553, 31.25e6);// / 2.0;

 	/* Disable TDC inputs prior to configuring */
 	fd_writel(FD_TDCSR_STOP_DIS | FD_TDCSR_START_DIS, FD_REG_TDCSR);
@@ -498,9 +499,33 @@ static int acam_configure(fdelay_device_t *dev, int mode)
 	 					  AR1_Adj(4, 2) |
 	 					  AR1_Adj(5, 6) |
 	 					  AR1_Adj(6, 0));
-	   	acam_write_reg(dev, 2, AR2_RMode | AR2_Adj(7, 2) | AR2_Adj(8, 6));
-	   	acam_write_reg(dev, 3, 0);
-	   	acam_write_reg(dev, 4, AR4_EFlagHiZN);
+	   	acam_write_reg(dev, 2, AR2_RMode | AR2_Adj(7, 2) | AR2_Adj(8, 6)
+		    	   	    | AR2_DelRise1(0) 
+		    	   	    | AR2_DelFall1(0) 
+		    	   	    | AR2_DelRise2(0) 
+		    	   	    | AR2_DelFall2(0) 
+		    	   	);
+	   	acam_write_reg(dev, 3, AR3_DelTx(1,3) | 
+	   			       AR3_DelTx(2,3) |
+	   			       AR3_DelTx(3,3) |
+	   			       AR3_DelTx(4,3) |
+	   			       AR3_DelTx(5,3) |
+	   			       AR3_DelTx(6,3) |
+	   			       AR3_DelTx(7,3) |
+	   			       AR3_DelTx(8,3) | 
+	   			       AR3_RaSpeed(0,3) |
+	   			       AR3_RaSpeed(1,3) | 
+	   			       AR3_RaSpeed(2,3) 
+    	   			       );
+	   			       
+	   	acam_write_reg(dev, 4, AR4_EFlagHiZN
+	   			     | AR4_RaSpeed(3,3) 
+	   			     | AR4_RaSpeed(4,3)  
+	   			     | AR4_RaSpeed(5,3)  
+	   			     | AR4_RaSpeed(6,3)  
+	   			     | AR4_RaSpeed(7,3)  
+	   			     | AR4_RaSpeed(8,3)  
+	   			     );
 	   	acam_write_reg(dev, 5, AR5_StartRetrig |AR5_StartOff1(hw->calib.acam_start_offset) | AR5_MasterAluTrig);
 	   	acam_write_reg(dev, 6, AR6_Fill(200) | AR6_PowerOnECL);
 	   	acam_write_reg(dev, 7, AR7_HSDiv(hsdiv) | AR7_RefClkDiv(refdiv) | AR7_ResAdj | AR7_NegPhase);
@@ -508,11 +533,69 @@ static int acam_configure(fdelay_device_t *dev, int mode)
 	   	acam_write_reg(dev, 12, 0x0000000);
 	   	acam_write_reg(dev, 14, 0);

+		/* Reset the ACAM after the configuration */
+	   	acam_write_reg(dev, 4, AR4_EFlagHiZN | AR4_MasterReset | AR4_StartTimer(0));
+	}else if(mode == ACAM_GMODE)
+	{
+		dbg("ACAM: working in G-Mode\n");
+
+	 	acam_write_reg(dev, 0, 0);
+	 	acam_write_reg(dev, 7, 0);
+	   	
+	 	sleep(1);
+
+	 	acam_write_reg(dev, 0, AR0_ROsc | AR0_RiseEn0 | AR0_RiseEn1 | AR0_HQSel );
+	 	acam_write_reg(dev, 1, AR1_Adj(0, 0) |
+	 					  AR1_Adj(1, 0) |
+	 					  AR1_Adj(2, 5) |
+	 					  AR1_Adj(3, 0) |
+	 					  AR1_Adj(4, 5) |
+	 					  AR1_Adj(5, 0) |
+	 					  AR1_Adj(6, 5));
+	   	acam_write_reg(dev, 2, AR2_GMode | AR2_Adj(7, 0) | AR2_Adj(8, 5)
+		    	   	    | AR2_DelRise1(0) 
+		    	   	    | AR2_DelFall1(0) 
+		    	   	    | AR2_DelRise2(0) 
+		    	   	    | AR2_DelFall2(0) 
+		    	   	);
+	   	acam_write_reg(dev, 3, AR3_DelTx(1,3) | 
+	   			       AR3_DelTx(2,3) |
+	   			       AR3_DelTx(3,3) |
+	   			       AR3_DelTx(4,3) |
+	   			       AR3_DelTx(5,3) |
+	   			       AR3_DelTx(6,3) |
+	   			       AR3_DelTx(7,3) |
+	   			       AR3_DelTx(8,3) | 
+	   			       AR3_RaSpeed(0,3) |
+	   			       AR3_RaSpeed(1,3) | 
+	   			       AR3_RaSpeed(2,3) 
+    	   			       );
+	   			       
+	   	acam_write_reg(dev, 4, AR4_EFlagHiZN
+	   			     | AR4_RaSpeed(3,3) 
+	   			     | AR4_RaSpeed(4,3)  
+	   			     | AR4_RaSpeed(5,3)  
+	   			     | AR4_RaSpeed(6,3)  
+	   			     | AR4_RaSpeed(7,3)  
+	   			     | AR4_RaSpeed(8,3)  
+	   			     );
+	   	acam_write_reg(dev, 5, AR5_StartRetrig |AR5_StartOff1(hw->calib.acam_start_offset) | AR5_MasterAluTrig);
+	   	acam_write_reg(dev, 6, AR6_Fill(200) | AR6_PowerOnECL | AR6_StartOff2(hw->calib.acam_start_offset));
+	   	acam_write_reg(dev, 7, AR7_HSDiv(hsdiv) | AR7_RefClkDiv(refdiv) | AR7_ResAdj | AR7_NegPhase);
+	   	acam_write_reg(dev, 11, 0x7ff0000);
+	   	acam_write_reg(dev, 12, 0x0000000);
+	   	acam_write_reg(dev, 14, 0);
+
 		/* Reset the ACAM after the configuration */
 	   	acam_write_reg(dev, 4, AR4_EFlagHiZN | AR4_MasterReset | AR4_StartTimer(0));

 	} else if (mode == ACAM_IMODE)
 	{
+	 	acam_write_reg(dev, 0, 0);
+	 	acam_write_reg(dev, 7, 0);
+	   	
+	 	sleep(1);
+
 		acam_write_reg(dev, 0, AR0_TRiseEn(0) | AR0_HQSel | AR0_ROsc);
 	   	acam_write_reg(dev, 2, AR2_IMode);
 	   	acam_write_reg(dev, 5, AR5_StartOff1(3000) | AR5_MasterAluTrig);
@@ -546,8 +629,9 @@ static int acam_configure(fdelay_device_t *dev, int mode)
 		usleep(10000);
    }

+    dbg("%s: Locking took %lld millieconds\n", __FUNCTION__, (get_tics() - start_tics) / 1000LL);

-	acam_set_address(dev, 8); /* Permamently select FIFO1 register for readout */
+    acam_set_address(dev, 8); /* Permamently select FIFO1 register for readout */

    return 0;
 }
@@ -612,7 +696,7 @@ static double measure_output_delay(fdelay_device_t *dev, int channel, int fine,
      	udelay(1);
 		/* read the tag, convert to picoseconds and average */
 		fr = acam_read_reg(dev, chan_to_fifo[channel]);
-	 	double tag = (double)((fr >> 0) & 0x1ffff) * hw->acam_bin * 3.0;
+	 	double tag = (double)((fr >> 0) & 0x1ffff) * hw->acam_bin;

 //	 	dbg("Tag %.1f\n", tag);

@@ -794,7 +878,8 @@ void fdelay_update_calibration(fdelay_device_t *dev)
 	fd_decl_private(dev);
 	int channel, temp;

-    ds18x_read_temp(dev, &temp);
+        ds18x_read_temp(dev, &temp);
+    	hw->board_temp = temp;

 	for(channel = 1; channel <= 4; channel++)
 	{   
@@ -807,6 +892,12 @@ void fdelay_update_calibration(fdelay_device_t *dev)
 	}
 }

+float fdelay_get_board_temperature(fdelay_device_t *dev)
+{
+    fd_decl_private(dev);
+    return (float)hw->board_temp / 16.0;
+}		
+
 #if 0
 void poll_stats()
 {
@@ -911,9 +1002,9 @@ int fdelay_init(fdelay_device_t *dev, int init_flags)
    hw->calib.frr_poly[1] = -29825595LL;
    hw->calib.frr_poly[2] = 3801939743082LL;
    hw->calib.tdc_zero_offset = 35600;
-//    hw->calib.atmcr_val =  4 | (1500 << 4);
-    hw->calib.atmcr_val =  2 | (1000 << 4);
-    hw->calib.adsfr_val = 56648;
+    hw->calib.atmcr_val =  26 | (1500 << 8);
+//    hw->calib.atmcr_val =  2 | (1000 << 4);
+    hw->calib.adsfr_val =  84977;   //;;56648;
    hw->calib.acam_start_offset = 10000;
    for(i=0;i<4;i++)
      hw->calib.zero_offset[i] = 50000;
@@ -933,9 +1024,9 @@ int fdelay_init(fdelay_device_t *dev, int init_flags)

 	if(ds18x_init(dev) < 0)
 	{
-   fail(TEST_SPI, "DS18x sensor not detected.");
-		dbg("DS18x sensor not detected. Bah!\n");
-    	return -1;
+	    fail(TEST_SPI, "DS18x sensor not detected.");
+    	    dbg("DS18x sensor not detected. Bah!\n");
+    	    return -1;
 	}

 	int temp;
@@ -981,7 +1072,7 @@ int fdelay_init(fdelay_device_t *dev, int init_flags)
    return -1;

  /* Switch to the R-MODE (more precise) */
-  acam_configure(dev, ACAM_RMODE);
+  acam_configure(dev, ACAM_GMODE);

  /* Switch the ACAM to be driven by the delay core instead of the host */
  fd_writel( 0, FD_REG_GCR);
@@ -996,9 +1087,9 @@ int fdelay_init(fdelay_device_t *dev, int init_flags)
     - bin -> internal timebase scalefactor (ADSFR),
     - Start offset (must be consistent with the value written to the ACAM reg 4)
     - timestamp merging control register (ATMCR) */
-  fd_writel( hw->calib.adsfr_val, FD_REG_ADSFR);
-  fd_writel( 3 * hw->calib.acam_start_offset, FD_REG_ASOR);
-  fd_writel( hw->calib.atmcr_val, FD_REG_ATMCR);
+  fd_writel( hw->calib.adsfr_val, FD_REG_ADSFR );
+  fd_writel( 17000, FD_REG_ASOR );
+  fd_writel( hw->calib.atmcr_val, FD_REG_ATMCR );

  t_zero.utc = 0;
  t_zero.coarse = 0;
@@ -1178,23 +1269,23 @@ static int sign_extend(int n, int nbits)
 void ts_postprocess(fdelay_device_t *dev, fdelay_time_t *t)
 {
 	fd_decl_private(dev)
-	int32_t post_frac_start_adj = t->raw.frac - 3*hw->calib.acam_start_offset;
+	int32_t post_frac_start_adj = t->raw.frac - 17000; //2*hw->calib.acam_start_offset;

 	t->utc = t->raw.utc;

-	int c_thr = FD_ATMCR_C_THR_R(hw->calib.atmcr_val);
-	int f_thr = FD_ATMCR_F_THR_R(hw->calib.atmcr_val);
+	int c_thr = 26;//FD_ATMCR_C_THR_R(hw->calib.atmcr_val);
+	int f_thr = 1500;//FD_ATMCR_F_THR_R(hw->calib.atmcr_val);
 //	printf("CThr: %d FThr: %d\n", c_thr, f_thr);

    if (t->raw.start_offset <= c_thr
    && (post_frac_start_adj > f_thr))
-    	t->coarse = (t->raw.coarse-1) * 16;
+    	t->coarse = (t->raw.coarse-1) * 32;
 	else
-    	t->coarse = (t->raw.coarse) * 16;
+    	t->coarse = (t->raw.coarse) * 32;

   int64_t post_frac_multiplied = post_frac_start_adj * (int64_t)hw->calib.adsfr_val;

-	t->coarse += sign_extend(t->raw.subcycle_offset, 5) 
+	t->coarse += sign_extend(t->raw.subcycle_offset, 6) 
 	+ (post_frac_multiplied >> 24);
 	
 	t->frac = (post_frac_multiplied >> 12) & 0xfff;
@@ -1223,8 +1314,8 @@ int fdelay_read(fdelay_device_t *dev, fdelay_time_t *timestamps, int how_many)
 			uint32_t cyc, dbg;
 			ts.raw.utc = ((int64_t) (fd_readl(FD_REG_TSBR_SECH) & 0xff) << 32) | fd_readl(FD_REG_TSBR_SECL);
 			cyc =  fd_readl(FD_REG_TSBR_CYCLES) & 0xfffffff;
-			ts.raw.coarse = cyc >> 4;
-			ts.raw.start_offset = cyc & 0xf;
+			ts.raw.coarse = cyc >> 5;
+			ts.raw.start_offset = cyc & 0x1f;


 			dbg = fd_readl(FD_REG_TSBR_DEBUG);
@@ -1233,8 +1324,12 @@ int fdelay_read(fdelay_device_t *dev, fdelay_time_t *timestamps, int how_many)
 			
 			ts.raw.frac = FD_TSBR_FID_FINE_R(seq_frac);
 			ts.raw.frac |= (dbg & 0x7ff) << 12;
-			ts.raw.subcycle_offset = (dbg >> 11) & 0x1f;
+			ts.raw.frac &= 0x1ffff;
 		
+			ts.raw.subcycle_offset = (dbg >> 11) & 0x1f;
+			if(dbg & (1<<31))
+			    ts.raw.subcycle_offset |= 0x20;
+			
 			
 //            tag_dbg_raw_o(23 downto 16) <= raw_coarse_shifted_i(7 downto 0);
 //            tag_dbg_raw_o(31 downto 24) <= raw_utc_shifted_i(7 downto 0);
@@ -1278,13 +1373,15 @@ int fdelay_configure_output(fdelay_device_t *dev, int channel, int enable, int64
 	if(channel < 1 || channel > 4)
 		return -1;

- 	delay_ps -= hw->calib.zero_offset[channel-1];
+ 	delay_ps -= 0; // hw->calib.zero_offset[channel-1];
 	start = fdelay_from_picos(delay_ps);
 	end = fdelay_from_picos(delay_ps + width_ps - 4000);
    delta = fdelay_from_picos(delta_ps);
 

-// 	printf("Start: %lld: %d:%d rep %d\n", start.utc, start.coarse, start.frac, rep_count);
+
+ 	printf("Start: %lld: %d:%d rep %d\n", start.utc, start.coarse, start.frac, rep_count);
+ 	printf("DelayPs: %lld\n", delay_ps);


 	chan_writel(hw->frr_cur[channel-1],  FD_REG_FRR);

--- a/software/lib/onewire.c
+++ b/software/lib/onewire.c
@@ -172,6 +172,7 @@ int ds18x_init(fdelay_device_t *dev)
 {

 	ow_init(dev);
+
 	if(ds18x_read_serial(dev, ds18x_id) < 0)
 		return -1;

@@ -179,5 +180,7 @@ int ds18x_init(fdelay_device_t *dev)
 		ds18x_id[0], ds18x_id[1], ds18x_id[2], ds18x_id[3],
 		ds18x_id[4], ds18x_id[5], ds18x_id[6], ds18x_id[7]);

-	return ds18x_read_temp(dev, NULL);
+	ds18x_read_temp(dev, NULL);
+	sleep(1);
+	return 0;
 }
--- a/software/tests/Makefile
+++ b/software/tests/Makefile
-TESTS = gs_logger # dmtd_calibration gs_logger random_pulse_test sweep_test temperature_calibration
+TESTS = gs_logger simple_delay random_pulse_gen

 CFLAGS = -I../include
-LDFLAGS = -L../lib ../lib/libfinedelay.a -lm -letherbone
+LDFLAGS = -L../lib ../lib/libfinedelay.a -lm 
 CC=gcc

 .PHONY: all

--- a/software/tests/random_pulse_gen.c
+++ b/software/tests/random_pulse_gen.c
+#define _GNU_SOURCE
+
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+#include <errno.h>
+#include <fcntl.h>
+#include <stdint.h>
+#include <unistd.h>
+#include <signal.h>
+#include <sys/select.h>
+
+#define FDELAY_INTERNAL // for sysfs_get/set
+#include "fdelay_lib.h"
+
+/* Add two timestamps */
+static fdelay_time_t ts_add(fdelay_time_t a, fdelay_time_t b)
+{
+    a.frac += b.frac;
+    if(a.frac >= 4096)
+    {
+        a.frac -= 4096;
+		a.coarse++;
+    }
+    a.coarse += b.coarse;
+    if(a.coarse >= 125000000)
+    {
+        a.coarse -= 125000000;
+	a.utc ++;
+    }
+    a.utc += b.utc;
+    return a;
+}
+
+fdelay_time_t ts_sub(fdelay_time_t a, fdelay_time_t b)
+{
+	a.frac -= b.frac;
+  	if(a.frac < 0)
+   	{
+  		a.frac += 4096;
+     	a.coarse--;
+    }
+    a.coarse -= b.coarse;
+    if(a.coarse < 0)
+    {
+    	a.coarse += 125000000;
+        a.utc --;
+    }
+    a.utc-=b.utc;
+    return a;
+}
+             
+int64_t rrand64(int64_t min, int64_t max)
+{
+	int i;
+	uint64_t tmp = 0;
+	for(i=0;i<32;i++) 
+		tmp ^= ((uint64_t)random()) << i;
+	
+	tmp %= (max-min+1);
+	return min+tmp;
+}
+
+int armed = 0;
+
+static int64_t min_gap, max_gap;
+static fdelay_time_t t;
+
+void produce_pulses(fdelay_device_t *b)
+{
+	int64_t delta;
+	fdelay_time_t  td;
+
+	if(armed && !fdelay_channel_triggered(b, 1))
+		return ;
+
+	delta = rrand64(min_gap, max_gap);
+	fdelay_get_time(b, &t);
+
+	td = fdelay_from_picos(delta);
+	
+	t = ts_add(t, td);
+	
+
+	fdelay_configure_pulse_gen(b, 1, 1, t, min_gap/3, 0, 1);
+	
+	armed = 1;
+}
+
+
+int main(int argc, char *argv[])
+{
+	if(argc < 4)
+	{
+	    fprintf(stderr, "usage: %s card_location min_period[us] max_period[us] count\n", argv[0]);
+	    return 0;
+	}
+	
+	fdelay_device_t *b = fdelay_create();
+	
+	if(fdelay_probe(b, argv[1]) < 0)
+	{
+	    fprintf(stderr, "Probing failed\n");
+	    return 0;
+	}
+
+	
+	fdelay_init(b, 0);
+	fdelay_configure_trigger(b, 0, 0);	
+	
+	int count = atoi(argv[4]);
+
+	min_gap =(int64_t) (atof(argv[2]) * 1000000.0);
+	max_gap =(int64_t) (atof(argv[3]) * 1000000.0);
+	
+	int i = 0;
+
+
+	while(count < 0 || (i < count))
+	{
+    	    produce_pulses(b);
+	    i++;
+	}
+
+	printf("generated %d pulses\n", i);
+
+	return 0;
+}