Commit 90db6efe authored by Tomasz Wlostowski's avatar Tomasz Wlostowski

Merge branch 'gmode'

Conflicts:
	hdl/rtl/fd_acam_timestamp_postprocessor.vhd
	hdl/rtl/fd_acam_timestamper.vhd
	hdl/testbench/svec_wr_top/main.sv
	hdl/top/spec/wr/spec_top.vhd
	hdl/top/svec/wr/svec_top.ucf
	hdl/top/svec/wr/svec_top.vhd
parents a7736c9b a989eb86
......@@ -119,11 +119,15 @@ module acam_model
//
time t_prev;
always@(posedge DStart)
if(PuResN && !StartDis && !start_disabled_int) begin
// if(g_verbose)$display("acam::start %d", t);
q_start.put(t);
// $display("StartEvt %d [delta %d]\n", t, t-t_prev);
// t_prev = t;
start_disabled_int <= r_StartDisStart;
end
......@@ -185,8 +189,8 @@ module acam_model
else
break;
end
if(t_stop1 - t_start > 3780)
hit = (t_stop1 - t_start) - (128ns/g_rmode_resolution) + rmode_start_offset * 3;
if(t_stop1 - t_start > 8520)
hit = (t_stop1 - t_start) - (256ns/g_rmode_resolution) + rmode_start_offset * 3;
else
hit = t_stop1 - t_start + rmode_start_offset * 3;
......
......@@ -67,6 +67,17 @@ module svec_vme_buffers (
pullup(slave.write_n);
pulldown(slave.bbsy_n);
pullup(slave.iackin_n);
pullup(slave.iackout_n);
genvar i;
generate
for(i=0;i<6;i++)
assign slave.irq_n[i] = (VME_IRQ_n_i[i] ? 1'b0 : 1'bz);
endgenerate
assign VME_RST_n_o = slave.rst_n;
......@@ -93,6 +104,8 @@ module svec_vme_buffers (
assign slave.dtack_n = VME_DTACK_n_i;
assign slave.berr_n = ~VME_BERR_i;
assign slave.retry_n = VME_RETRY_n_i;
assign slave.iackout_n = VME_IACKOUT_n_i;
endmodule
......
......@@ -187,7 +187,7 @@ typedef enum { DONT_CARE = 'h100,
} vme_addr_size_t;
typedef enum {
SINGLE = 'h10, CR_CSR='h20, MBLT='h30, BLT='h40, LCK='h50, TwoeVME='h60, TwoeSST='h70 } vme_xfer_type_t;
SINGLE = 'h10, CR_CSR='h20, MBLT='h30, BLT='h40, LCK='h50, TwoeVME='h60, TwoeSST='h70, IACK = 'h80 } vme_xfer_type_t;
typedef enum { D08Byte0='h1, D08Byte1='h2, D08Byte2='h3, D08Byte3='h4, D16Byte01='h5, D16Byte23='h6, D32='h7 } vme_data_type_t ;
......@@ -207,17 +207,48 @@ class CBusAccessor_VME64x extends CBusAccessor;
protected bit [4:0] m_ga;
virtual IVME64X.tb vme;
function new(virtual IVME64X.tb _vme);
vme = _vme;
m_ga = 6'b010111;
vme.q_ga = m_ga;
m_ba = 8'b10000000;
endfunction // new
protected task acknowledge_irq(int level, ref int vector);
`assert_wait(tmo_rws_bus_free, vme.dtack_n && vme.berr_n, 10us)
release_bus();
#40ns;
vme.q_addr[3:1] = level;
vme.q_iackin_n = 1'b0;
vme.q_iack_n = 1'b0;
vme.q_am = 'h29;
#100ns;
vme.q_as_n = 1'b0;
#100ns;
vme.q_ds_n[0] = 1'b0;
`assert_wait(tmo_rws_bus_idle, !vme.dtack_n || !vme.berr_n, 4us)
if(!vme.berr_n)
$error("[rw_simple_generic]: VME bus error.");
vector = vme.data;
vme.q_iackin_n = 1'b1;
vme.q_iack_n = 1'b1;
#100ns;
release_bus();
endtask
protected task set_address(uint64_t addr_in, vme_addr_size_t asize, vme_xfer_type_t xtype);
bit[63:0] a = addr_in;
bit [31:0] a_out;
const bit [5:0] am_map [int] =
'{
A32 | CR_CSR : 6'b101111,
......@@ -248,11 +279,11 @@ class CBusAccessor_VME64x extends CBusAccessor;
a_out = {8'h0, ~m_ga[4:0], a[18:0]};
else case(asize)
A16:
a_out = {16'h0, m_ba[7:3], a[10:2], 2'b00};
a_out = {16'h0, a[15:2], 2'b00};
A24:
a_out = {8'h0, m_ba[7:3], a[18:2], 2'b00};
a_out = {8'h0, a[23:2], 2'b00};
A32:
a_out = {m_ba[7:3], a[26:2], 2'b00};
a_out = { a[31:2], 2'b00};
endcase // case (xtype)
vme.q_addr[31:2] = a_out[31:2];
......@@ -399,7 +430,30 @@ class CBusAccessor_VME64x extends CBusAccessor;
writem(aa, da, size, result);
endtask
task handle_irqs(ref int done);
done = 0;
if(vme.irq_n != 7'h7f)
begin
int i,level, vector;
for(i=6;i>=0;i--)
if(!vme.irq_n[i])
begin
level = i+1;
break;
end
$display("vme64x_bfm: got irq level %d", level);
acknowledge_irq(level, vector);
$display("vme64x_bfm: vector %x", vector);
done = 1;
end
endtask // handle_irqs
endclass // CBusAccessor_VME64x
......
......@@ -6,7 +6,7 @@
-- Author : Tomasz Wlostowski
-- Company : CERN
-- Created : 2011-08-29
-- Last update: 2013-02-21
-- Last update: 2013-02-06
-- Platform : FPGA-generic
-- Standard : VHDL'93
-------------------------------------------------------------------------------
......@@ -62,20 +62,20 @@ entity fd_acam_timestamp_postprocessor is
raw_utc_i : in std_logic_vector(c_TIMESTAMP_UTC_BITS-1 downto 0);
-- "start number" (value of coarse counter, counting at every start pulse of the
-- TDC, i.e. 125 MHz / 16 = 7.8215 MHz)
raw_coarse_i : in std_logic_vector(c_TIMESTAMP_COARSE_BITS-4-1 downto 0);
-- TDC, i.e. 125 MHz / 32 = 3.90625 MHz)
raw_coarse_i : in std_logic_vector(c_TIMESTAMP_COARSE_BITS-5-1 downto 0);
-- raw fractional timestamp generated by ACAM
raw_frac_i : in std_logic_vector(22 downto 0);
-- coarse offset (in 125 MHz clock cycles) from the last ACAM's start pulse to the
-- input pulse (0..15)
raw_start_offset_i : in std_logic_vector(3 downto 0);
raw_start_offset_i : in std_logic_vector(4 downto 0);
-- Offset between the actual timescale and the ACAM fixed start signal generated
-- by the AD9516 PLL. Used to align the timestamps to the externally
-- provided time base (e.g. by White Rabbit).
acam_subcycle_offset_i : in std_logic_vector(4 downto 0);
acam_subcycle_offset_i : in std_logic_vector(5 downto 0);
---------------------------------------------------------------------------
-- Post-processed timestamp. WARNING! DE-NORMALIZED!
......@@ -148,7 +148,7 @@ begin -- behavioral
pp_pipe(0) <= raw_valid_i;
post_frac_start_adj <= signed(raw_frac_i) - signed(regs_i.asor_offset_o);
post_tag_coarse(3 downto 0) <= (others => '0');
post_tag_coarse(4 downto 0) <= (others => '0');
post_tag_utc <= unsigned(raw_utc_i);
-- pipeline stage 2:
......@@ -162,9 +162,9 @@ begin -- behavioral
pp_pipe(1) <= pp_pipe(0);
if (unsigned(raw_start_offset_i) <= unsigned(regs_i.atmcr_c_thr_o)) and (post_frac_start_adj > signed(regs_i.atmcr_f_thr_o)) then
post_tag_coarse(post_tag_coarse'left downto 4) <= unsigned(raw_coarse_i) - 1;
post_tag_coarse(post_tag_coarse'left downto 5) <= unsigned(raw_coarse_i) - 1;
else
post_tag_coarse(post_tag_coarse'left downto 4) <= unsigned(raw_coarse_i);
post_tag_coarse(post_tag_coarse'left downto 5) <= unsigned(raw_coarse_i);
end if;
-- Pipeline stage 3:
......@@ -212,18 +212,19 @@ begin -- behavioral
-- extra coarse counts from ACAM's frac part after rescaling
tag_frac_o <= std_logic_vector(post_frac_multiplied_d0(c_SCALER_SHIFT + g_frac_bits-1 downto c_SCALER_SHIFT));
tag_frac_o <= std_logic_vector(post_frac_multiplied_d0(c_SCALER_SHIFT + g_frac_bits-1 downto c_SCALER_SHIFT));
tag_valid_o <= pp_pipe(4);
elsif(raw_valid_i = '1') then
tag_utc_o <= raw_utc_i;
tag_coarse_o <= raw_coarse_i & raw_start_offset_i;
tag_frac_o <= raw_frac_i(11 downto 0);
tag_dbg_raw_o(10 downto 0) <= raw_frac_i(22 downto 12);
tag_dbg_raw_o(15 downto 11) <= acam_subcycle_offset_i;
tag_utc_o <= raw_utc_i;
tag_coarse_o <= raw_coarse_i & raw_start_offset_i;
tag_frac_o <= raw_frac_i(11 downto 0);
tag_dbg_raw_o(10 downto 0) <= raw_frac_i(22 downto 12);
tag_dbg_raw_o(15 downto 11) <= acam_subcycle_offset_i(4 downto 0);
tag_dbg_raw_o(23 downto 16) <= raw_coarse_i(7 downto 0);
tag_dbg_raw_o(31 downto 24) <= raw_utc_i(7 downto 0);
tag_dbg_raw_o(30 downto 24) <= raw_utc_i(6 downto 0);
tag_dbg_raw_o(31) <= acam_subcycle_offset_i(5);
tag_valid_o <= '1';
else
......
......@@ -6,7 +6,7 @@
-- Author : Tomasz Wlostowski
-- Company : CERN
-- Created : 2011-08-24
-- Last update: 2013-02-21
-- Last update: 2013-02-12
-- Platform : FPGA-generic
-- Standard : VHDL'93
-------------------------------------------------------------------------------
......@@ -165,10 +165,10 @@ architecture behavioral of fd_acam_timestamper is
rst_n_i : in std_logic;
raw_valid_i : in std_logic;
raw_utc_i : in std_logic_vector(c_TIMESTAMP_UTC_BITS-1 downto 0);
raw_coarse_i : in std_logic_vector(c_TIMESTAMP_COARSE_BITS-4-1 downto 0);
raw_coarse_i : in std_logic_vector(c_TIMESTAMP_COARSE_BITS-5-1 downto 0);
raw_frac_i : in std_logic_vector(22 downto 0);
raw_start_offset_i : in std_logic_vector(3 downto 0);
acam_subcycle_offset_i : in std_logic_vector(4 downto 0);
raw_start_offset_i : in std_logic_vector(4 downto 0);
acam_subcycle_offset_i : in std_logic_vector(5 downto 0);
tag_valid_o : out std_logic;
tag_utc_o : out std_logic_vector(c_TIMESTAMP_UTC_BITS-1 downto 0);
tag_coarse_o : out std_logic_vector(c_TIMESTAMP_COARSE_BITS-1 downto 0);
......@@ -222,18 +222,18 @@ architecture behavioral of fd_acam_timestamper is
signal trig_pulse : std_logic;
-- counters (internal time base)
signal start_count : unsigned(3 downto 0);
signal coarse_count : unsigned(c_TIMESTAMP_COARSE_BITS-4-1 downto 0);
signal start_count : unsigned(4 downto 0);
signal coarse_count : unsigned(c_TIMESTAMP_COARSE_BITS-5-1 downto 0);
signal utc_count : unsigned(c_TIMESTAMP_UTC_BITS-1 downto 0);
signal subcycle_offset : signed(4 downto 0);
signal subcycle_offset : signed(5 downto 0);
signal gcr_input_en_d0 : std_logic;
-- raw (unprocessed) time tag
signal raw_tag_valid : std_logic;
signal raw_tag_coarse : unsigned(c_TIMESTAMP_COARSE_BITS-4-1 downto 0);
signal raw_tag_coarse : unsigned(c_TIMESTAMP_COARSE_BITS-5-1 downto 0);
signal raw_tag_frac : signed(22 downto 0);
signal raw_tag_start_offset : unsigned(3 downto 0);
signal raw_tag_start_offset : unsigned(4 downto 0);
signal raw_tag_utc : unsigned(c_TIMESTAMP_UTC_BITS-1 downto 0);
signal width_check_sreg : std_logic_vector(g_min_pulse_width-2 downto 0);
......@@ -401,11 +401,14 @@ begin -- behave
else
-- Enable the start input at proper moment to ensure that the 7.125 MHz
-- "start clock" cycle is not cut.
if(start_count = x"e") then
if(start_count = x"8") then
-- advance the start OK shift register with another one.
start_ok_sreg <= start_ok_sreg(start_ok_sreg'left-1 downto 0) & '1';
acam_start_dis_o <= '1';
elsif (start_count = x"18") then
acam_start_dis_o <= '0';
end if;
end if;
end if;
end if;
......@@ -440,6 +443,8 @@ begin -- behave
end if;
end process;
-- Process: p_sync_acam_ef
-- Input: acam_ef_i
-- Output: acam_ef_d1
......@@ -457,6 +462,17 @@ begin -- behave
-- Time Base Counters
-------------------------------------------------------------------------------
p_gen_start_mask : process(clk_ref_i)
begin
if rising_edge(clk_ref_i) then
if rst_n_i = '0' then
start_mask <= '0';
elsif(tdc_start_d(1) = '1' and tdc_start_d(2) = '0') then
start_mask <= not start_mask;
end if;
end if;
end process;
-- Start counter: counts the number of clk_ref_i cycles from the last TDC start
-- event.
......@@ -476,18 +492,18 @@ begin -- behave
-- between the current start count and the LSBs of the new time value
-- and correct the timestamps later on.
if(csync_p1_i = '1') then
subcycle_offset <= signed('0' & csync_coarse_i(3 downto 0)) - signed('0' & start_count) - 1;
subcycle_offset <= signed('0' & csync_coarse_i(4 downto 0)) - signed('0' & start_count) - 1;
end if;
-- Rising edge on TDC_START? Resynchronize the counter, to go to zero
-- right after the edge.
if(tdc_start_d(1) = '1' and tdc_start_d(2) = '0') then
start_count <= x"2";
if(tdc_start_d(1) = '1' and tdc_start_d(2) = '0' and start_mask = '0') then
start_count <= to_unsigned(2, 5);
advance_coarse <= '0';
else
-- Start cycle expired - advance the 128 ns x counter. We do that one
-- cycle in advance using a register to relax the P&R timing.
if(start_count = x"e") then
if(start_count = x"1e") then
advance_coarse <= '1';
else
advance_coarse <= '0';
......@@ -511,13 +527,13 @@ begin -- behave
-- overflow of start_count.
if(csync_p1_i = '1') then
if(advance_coarse = '1') then
coarse_count <= unsigned(csync_coarse_i(27 downto 4)) + 1;
coarse_count <= unsigned(csync_coarse_i(27 downto 5)) + 1;
else
coarse_count <= unsigned(csync_coarse_i(27 downto 4));
coarse_count <= unsigned(csync_coarse_i(27 downto 5));
end if;
elsif(advance_coarse = '1') then
-- well, just boringly count up
if(coarse_count = (g_clk_ref_freq / 16) - 1) then
if(coarse_count = (g_clk_ref_freq / 32) - 1) then
coarse_count <= (others => '0');
else
coarse_count <= coarse_count + 1;
......@@ -537,14 +553,14 @@ begin -- behave
utc_count <= (others => '0');
else
if(csync_p1_i = '1') then
if(advance_coarse = '1' and coarse_count = (g_clk_ref_freq / 16) -1) then
if(advance_coarse = '1' and coarse_count = (g_clk_ref_freq / 32) -1) then
-- I hate special cases!
utc_count <= unsigned(csync_utc_i) + 1;
else
utc_count <= unsigned(csync_utc_i);
end if;
elsif(advance_coarse = '1' and coarse_count = (g_clk_ref_freq / 16) - 1) then
elsif(advance_coarse = '1' and coarse_count = (g_clk_ref_freq / 32) - 1) then
utc_count <= utc_count + 1;
end if;
......@@ -721,7 +737,8 @@ begin -- behave
when RMODE_READ =>
-- store the fine tag
raw_tag_frac <= signed(acam_d_i(raw_tag_frac'left downto 0));
raw_tag_frac(21 downto 0) <= signed(acam_d_i(21 downto 0));
raw_tag_frac(22) <= '0';
-- check if the FIFO has become empty after the readout. If it didn't, the TDC
......
......@@ -3,7 +3,7 @@
---------------------------------------------------------------------------------------
-- File : fd_channel_wbgen2_pkg.vhd
-- Author : auto-generated by wbgen2 from fd_channel_wishbone_slave.wb
-- Created : Mon Jun 4 13:42:20 2012
-- Created : Fri Feb 15 12:07:17 2013
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE fd_channel_wishbone_slave.wb
......
......@@ -3,7 +3,7 @@
---------------------------------------------------------------------------------------
-- File : fd_channel_wishbone_slave.vhd
-- Author : auto-generated by wbgen2 from fd_channel_wishbone_slave.wb
-- Created : Mon Jun 4 13:42:20 2012
-- Created : Fri Feb 15 12:07:17 2013
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE fd_channel_wishbone_slave.wb
......@@ -161,11 +161,11 @@ begin
end if;
rddata_reg(0) <= fd_channel_dcr_enable_int;
rddata_reg(1) <= fd_channel_dcr_mode_int;
rddata_reg(2) <= 'X';
rddata_reg(2) <= '0';
rddata_reg(3) <= fd_channel_dcr_pg_trig_sync1;
rddata_reg(4) <= 'X';
rddata_reg(4) <= '0';
rddata_reg(5) <= fd_channel_dcr_upd_done_sync1;
rddata_reg(6) <= 'X';
rddata_reg(6) <= '0';
rddata_reg(7) <= fd_channel_dcr_no_fine_int;
rddata_reg(8) <= fd_channel_dcr_force_hi_int;
rddata_reg(9) <= 'X';
......
......@@ -3,7 +3,7 @@
---------------------------------------------------------------------------------------
-- File : fd_main_wbgen2_pkg.vhd
-- Author : auto-generated by wbgen2 from fd_main_wishbone_slave.wb
-- Created : Fri Dec 14 11:28:02 2012
-- Created : Fri Feb 15 12:07:16 2013
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE fd_main_wishbone_slave.wb
......@@ -130,7 +130,7 @@ package fd_main_wbgen2_pkg is
calr_cal_dmtd_o : std_logic;
calr_psel_o : std_logic_vector(3 downto 0);
adsfr_o : std_logic_vector(17 downto 0);
atmcr_c_thr_o : std_logic_vector(3 downto 0);
atmcr_c_thr_o : std_logic_vector(7 downto 0);
atmcr_f_thr_o : std_logic_vector(22 downto 0);
asor_offset_o : std_logic_vector(22 downto 0);
iepd_rst_stat_o : std_logic;
......
......@@ -3,7 +3,7 @@
---------------------------------------------------------------------------------------
-- File : fd_main_wishbone_slave.vhd
-- Author : auto-generated by wbgen2 from fd_main_wishbone_slave.wb
-- Created : Fri Dec 14 11:28:02 2012
-- Created : Fri Feb 15 12:07:16 2013
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE fd_main_wishbone_slave.wb
......@@ -159,7 +159,7 @@ signal fd_main_adsfr_swb_delay : std_logic ;
signal fd_main_adsfr_swb_s0 : std_logic ;
signal fd_main_adsfr_swb_s1 : std_logic ;
signal fd_main_adsfr_swb_s2 : std_logic ;
signal fd_main_atmcr_c_thr_int : std_logic_vector(3 downto 0);
signal fd_main_atmcr_c_thr_int : std_logic_vector(7 downto 0);
signal fd_main_atmcr_c_thr_swb : std_logic ;
signal fd_main_atmcr_c_thr_swb_delay : std_logic ;
signal fd_main_atmcr_c_thr_swb_s0 : std_logic ;
......@@ -332,7 +332,7 @@ begin
fd_main_adsfr_int <= "000000000000000000";
fd_main_adsfr_swb <= '0';
fd_main_adsfr_swb_delay <= '0';
fd_main_atmcr_c_thr_int <= "0000";
fd_main_atmcr_c_thr_int <= "00000000";
fd_main_atmcr_c_thr_swb <= '0';
fd_main_atmcr_c_thr_swb_delay <= '0';
fd_main_atmcr_f_thr_int <= "00000000000000000000000";
......@@ -373,8 +373,8 @@ begin
fd_main_tsbir_timeout_int <= "0000000000";
fd_main_tsbir_threshold_int <= "000000000000";
fid_read_ack_o <= '0';
fd_main_i2cr_scl_out_int <= '0';
fd_main_i2cr_sda_out_int <= '0';
fd_main_i2cr_scl_out_int <= '1';
fd_main_i2cr_sda_out_int <= '1';
fd_main_tder2_pelt_drive_int <= "00000000000000000000000000000000";
fd_main_tsbr_advance_adv_int <= '0';
eic_idr_write_int <= '0';
......@@ -595,8 +595,8 @@ begin
rddata_reg(3) <= regs_i.tcr_wr_present_i;
rddata_reg(4) <= regs_i.tcr_wr_ready_i;
rddata_reg(5) <= regs_i.tcr_wr_link_i;
rddata_reg(6) <= 'X';
rddata_reg(7) <= 'X';
rddata_reg(6) <= '0';
rddata_reg(7) <= '0';
rddata_reg(8) <= 'X';
rddata_reg(9) <= 'X';
rddata_reg(10) <= 'X';
......@@ -736,14 +736,14 @@ begin
fd_main_tdcsr_alutrig_int <= wrdata_reg(7);
fd_main_tdcsr_alutrig_int_delay <= wrdata_reg(7);
end if;
rddata_reg(0) <= 'X';
rddata_reg(1) <= 'X';
rddata_reg(0) <= '0';
rddata_reg(1) <= '0';
rddata_reg(2) <= fd_main_tdcsr_empty_sync1;
rddata_reg(3) <= 'X';
rddata_reg(4) <= 'X';
rddata_reg(5) <= 'X';
rddata_reg(6) <= 'X';
rddata_reg(7) <= 'X';
rddata_reg(3) <= '0';
rddata_reg(4) <= '0';
rddata_reg(5) <= '0';
rddata_reg(6) <= '0';
rddata_reg(7) <= '0';
rddata_reg(8) <= 'X';
rddata_reg(9) <= 'X';
rddata_reg(10) <= 'X';
......@@ -780,7 +780,7 @@ begin
fd_main_calr_psel_swb <= '1';
fd_main_calr_psel_swb_delay <= '1';
end if;
rddata_reg(0) <= 'X';
rddata_reg(0) <= '0';
rddata_reg(1) <= fd_main_calr_cal_pps_int;
rddata_reg(2) <= fd_main_calr_cal_dmtd_int;
rddata_reg(6 downto 3) <= fd_main_calr_psel_int;
......@@ -852,19 +852,15 @@ begin
ack_in_progress <= '1';
when "001101" =>
if (wb_we_i = '1') then
fd_main_atmcr_c_thr_int <= wrdata_reg(3 downto 0);
fd_main_atmcr_c_thr_int <= wrdata_reg(7 downto 0);
fd_main_atmcr_c_thr_swb <= '1';
fd_main_atmcr_c_thr_swb_delay <= '1';
fd_main_atmcr_f_thr_int <= wrdata_reg(26 downto 4);
fd_main_atmcr_f_thr_int <= wrdata_reg(30 downto 8);
fd_main_atmcr_f_thr_swb <= '1';
fd_main_atmcr_f_thr_swb_delay <= '1';
end if;
rddata_reg(3 downto 0) <= fd_main_atmcr_c_thr_int;
rddata_reg(26 downto 4) <= fd_main_atmcr_f_thr_int;
rddata_reg(27) <= 'X';
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(7 downto 0) <= fd_main_atmcr_c_thr_int;
rddata_reg(30 downto 8) <= fd_main_atmcr_f_thr_int;
rddata_reg(31) <= 'X';
ack_sreg(3) <= '1';
ack_in_progress <= '1';
......@@ -911,7 +907,7 @@ begin
fd_main_iepd_rst_stat_int <= wrdata_reg(0);
fd_main_iepd_rst_stat_int_delay <= wrdata_reg(0);
end if;
rddata_reg(0) <= 'X';
rddata_reg(0) <= '0';
if (wb_we_i = '0') then
fd_main_iepd_pdelay_lwb <= '1';
fd_main_iepd_pdelay_lwb_delay <= '1';
......@@ -957,7 +953,7 @@ begin
rddata_reg(26) <= fd_main_scr_sel_gpio_int;
rddata_reg(27) <= regs_i.scr_ready_i;
rddata_reg(28) <= fd_main_scr_cpol_int;
rddata_reg(29) <= 'X';
rddata_reg(29) <= '0';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
ack_sreg(2) <= '1';
......@@ -985,8 +981,8 @@ begin
end if;
rddata_reg(4 downto 0) <= fd_main_tsbcr_chan_mask_int;
rddata_reg(5) <= fd_main_tsbcr_enable_int;
rddata_reg(6) <= 'X';
rddata_reg(7) <= 'X';
rddata_reg(6) <= '0';
rddata_reg(7) <= '0';
rddata_reg(8) <= regs_i.tsbcr_full_i;
rddata_reg(9) <= regs_i.tsbcr_empty_i;
tsbcr_read_ack_o <= '1';
......@@ -1139,7 +1135,7 @@ begin
if (wb_we_i = '1') then
fd_main_tsbr_advance_adv_int <= wrdata_reg(0);
end if;
rddata_reg(0) <= 'X';
rddata_reg(0) <= '0';
rddata_reg(0) <= 'X';
rddata_reg(1) <= 'X';
rddata_reg(2) <= 'X';
......@@ -1376,7 +1372,7 @@ begin
-- PLL Locked
-- Mezzanice Present
-- Mezzanine Present
-- DMTD Clock Status
-- WR Timing Enable
regs_o.tcr_wr_enable_o <= fd_main_tcr_wr_enable_int;
......@@ -1478,8 +1474,8 @@ begin
end process;
-- Reference clock cycles
-- asynchronous std_logic_vector register : Reference clock cycles (type RW/WO, clk_ref_i <-> clk_sys_i)
-- Reference clock cycles (0...124999999)
-- asynchronous std_logic_vector register : Reference clock cycles (0...124999999) (type RW/WO, clk_ref_i <-> clk_sys_i)
process (clk_ref_i, rst_n_i)
begin
if (rst_n_i = '0') then
......@@ -1538,7 +1534,7 @@ begin
end process;
-- Start TDC write
-- Write to TDC
process (clk_ref_i, rst_n_i)
begin
if (rst_n_i = '0') then
......@@ -1555,7 +1551,7 @@ begin
end process;
-- Start TDC read
-- Read from TDC
process (clk_ref_i, rst_n_i)
begin
if (rst_n_i = '0') then
......@@ -1586,7 +1582,7 @@ begin
end process;
-- Start enable
-- Stop enable
process (clk_ref_i, rst_n_i)
begin
if (rst_n_i = '0') then
......@@ -1620,7 +1616,7 @@ begin
end process;
-- Stop enable
-- Start enable
process (clk_ref_i, rst_n_i)
begin
if (rst_n_i = '0') then
......@@ -1654,7 +1650,7 @@ begin
end process;
-- write 1: Pulse the Alutrigger line
-- Pulse <code>Alutrigger</code> line
process (clk_ref_i, rst_n_i)
begin
if (rst_n_i = '0') then
......@@ -1671,7 +1667,7 @@ begin
end process;
-- Triggers calibration pulses
-- Generate calibration pulses (type 1 calibration)
process (clk_ref_i, rst_n_i)
begin
if (rst_n_i = '0') then
......@@ -1704,10 +1700,10 @@ begin
end process;
-- Produce DDMTD calibration pattern
-- Produce DDMTD calibration pattern (type 2 calibration)
regs_o.calr_cal_dmtd_o <= fd_main_calr_cal_dmtd_int;
-- Enable pulse generation
-- asynchronous std_logic_vector register : Enable pulse generation (type RW/RO, clk_ref_i <-> clk_sys_i)
-- Calibration pulse output select/mask
-- asynchronous std_logic_vector register : Calibration pulse output select/mask (type RW/RO, clk_ref_i <-> clk_sys_i)
process (clk_ref_i, rst_n_i)
begin
if (rst_n_i = '0') then
......@@ -1758,7 +1754,7 @@ begin
fd_main_atmcr_c_thr_swb_s0 <= '0';
fd_main_atmcr_c_thr_swb_s1 <= '0';
fd_main_atmcr_c_thr_swb_s2 <= '0';
regs_o.atmcr_c_thr_o <= "0000";
regs_o.atmcr_c_thr_o <= "00000000";
elsif rising_edge(clk_ref_i) then
fd_main_atmcr_c_thr_swb_s0 <= fd_main_atmcr_c_thr_swb;
fd_main_atmcr_c_thr_swb_s1 <= fd_main_atmcr_c_thr_swb_s0;
......
......@@ -515,7 +515,7 @@ peripheral {
field {
name = "Wraparound Coarse Threshold";
prefix = "C_THR";
size = 4;
size = 8;
type = SLV;
clock = "clk_ref_i";
access_bus = READ_WRITE;
......
......@@ -6,7 +6,7 @@
-- Author : Tomasz Wlostowski
-- Company : CERN
-- Created : 2011-08-24
-- Last update: 2012-11-22
-- Last update: 2013-04-30
-- Platform : FPGA-generic
-- Standard : VHDL'93
-------------------------------------------------------------------------------
......@@ -76,7 +76,7 @@ package fine_delay_pkg is
constant c_FD_DMTD_CALIBRATION_PERIOD : integer := 144;