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FMC DEL 1ns 4cha
Commits
8f25c0df
Commit
8f25c0df
authored
Feb 21, 2013
by
Tomasz Wlostowski
Browse files
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hdl: use the TDC in G-mode (testing only)
parent
f5497277
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8 changed files
with
235 additions
and
217 deletions
+235
-217
fd_acam_timestamp_postprocessor.vhd
hdl/rtl/fd_acam_timestamp_postprocessor.vhd
+17
-18
fd_acam_timestamper.vhd
hdl/rtl/fd_acam_timestamper.vhd
+88
-93
fd_channel_wbgen2_pkg.vhd
hdl/rtl/fd_channel_wbgen2_pkg.vhd
+1
-1
fd_channel_wishbone_slave.vhd
hdl/rtl/fd_channel_wishbone_slave.vhd
+4
-4
fd_delay_line_arbiter.vhd
hdl/rtl/fd_delay_line_arbiter.vhd
+19
-16
fd_main_wbgen2_pkg.vhd
hdl/rtl/fd_main_wbgen2_pkg.vhd
+2
-2
fd_main_wishbone_slave.vhd
hdl/rtl/fd_main_wishbone_slave.vhd
+37
-41
fd_main_wishbone_slave.wb
hdl/rtl/fd_main_wishbone_slave.wb
+67
-42
No files found.
hdl/rtl/fd_acam_timestamp_postprocessor.vhd
View file @
8f25c0df
...
@@ -6,7 +6,7 @@
...
@@ -6,7 +6,7 @@
-- Author : Tomasz Wlostowski
-- Author : Tomasz Wlostowski
-- Company : CERN
-- Company : CERN
-- Created : 2011-08-29
-- Created : 2011-08-29
-- Last update: 201
2-05-18
-- Last update: 201
3-02-06
-- Platform : FPGA-generic
-- Platform : FPGA-generic
-- Standard : VHDL'93
-- Standard : VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
...
@@ -60,24 +60,22 @@ entity fd_acam_timestamp_postprocessor is
...
@@ -60,24 +60,22 @@ entity fd_acam_timestamp_postprocessor is
raw_valid_i
:
in
std_logic
;
raw_valid_i
:
in
std_logic
;
raw_utc_i
:
in
std_logic_vector
(
c_TIMESTAMP_UTC_BITS
-1
downto
0
);
raw_utc_i
:
in
std_logic_vector
(
c_TIMESTAMP_UTC_BITS
-1
downto
0
);
raw_utc_shifted_i
:
in
std_logic_vector
(
c_TIMESTAMP_UTC_BITS
-1
downto
0
);
-- "start number" (value of coarse counter, counting at every start pulse of the
-- "start number" (value of coarse counter, counting at every start pulse of the
-- TDC, i.e. 125 MHz / 16 = 7.8215 MHz)
-- TDC, i.e. 125 MHz / 32 = 3.90625 MHz)
raw_coarse_i
:
in
std_logic_vector
(
c_TIMESTAMP_COARSE_BITS
-4-1
downto
0
);
raw_coarse_i
:
in
std_logic_vector
(
c_TIMESTAMP_COARSE_BITS
-5-1
downto
0
);
raw_coarse_shifted_i
:
in
std_logic_vector
(
c_TIMESTAMP_COARSE_BITS
-4-1
downto
0
);
-- raw fractional timestamp generated by ACAM
-- raw fractional timestamp generated by ACAM
raw_frac_i
:
in
std_logic_vector
(
22
downto
0
);
raw_frac_i
:
in
std_logic_vector
(
22
downto
0
);
-- coarse offset (in 125 MHz clock cycles) from the last ACAM's start pulse to the
-- coarse offset (in 125 MHz clock cycles) from the last ACAM's start pulse to the
-- input pulse (0..15)
-- input pulse (0..15)
raw_start_offset_i
:
in
std_logic_vector
(
3
downto
0
);
raw_start_offset_i
:
in
std_logic_vector
(
4
downto
0
);
-- Offset between the actual timescale and the ACAM fixed start signal generated
-- Offset between the actual timescale and the ACAM fixed start signal generated
-- by the AD9516 PLL. Used to align the timestamps to the externally
-- by the AD9516 PLL. Used to align the timestamps to the externally
-- provided time base (e.g. by White Rabbit).
-- provided time base (e.g. by White Rabbit).
acam_subcycle_offset_i
:
in
std_logic_vector
(
4
downto
0
);
acam_subcycle_offset_i
:
in
std_logic_vector
(
5
downto
0
);
---------------------------------------------------------------------------
---------------------------------------------------------------------------
-- Post-processed timestamp. WARNING! DE-NORMALIZED!
-- Post-processed timestamp. WARNING! DE-NORMALIZED!
...
@@ -150,7 +148,7 @@ begin -- behavioral
...
@@ -150,7 +148,7 @@ begin -- behavioral
pp_pipe
(
0
)
<=
raw_valid_i
;
pp_pipe
(
0
)
<=
raw_valid_i
;
post_frac_start_adj
<=
signed
(
raw_frac_i
)
-
signed
(
regs_i
.
asor_offset_o
);
post_frac_start_adj
<=
signed
(
raw_frac_i
)
-
signed
(
regs_i
.
asor_offset_o
);
post_tag_coarse
(
3
downto
0
)
<=
(
others
=>
'0'
);
post_tag_coarse
(
4
downto
0
)
<=
(
others
=>
'0'
);
post_tag_utc
<=
unsigned
(
raw_utc_i
);
post_tag_utc
<=
unsigned
(
raw_utc_i
);
-- pipeline stage 2:
-- pipeline stage 2:
...
@@ -164,9 +162,9 @@ begin -- behavioral
...
@@ -164,9 +162,9 @@ begin -- behavioral
pp_pipe
(
1
)
<=
pp_pipe
(
0
);
pp_pipe
(
1
)
<=
pp_pipe
(
0
);
if
(
unsigned
(
raw_start_offset_i
)
<=
unsigned
(
regs_i
.
atmcr_c_thr_o
))
and
(
post_frac_start_adj
>
signed
(
regs_i
.
atmcr_f_thr_o
))
then
if
(
unsigned
(
raw_start_offset_i
)
<=
unsigned
(
regs_i
.
atmcr_c_thr_o
))
and
(
post_frac_start_adj
>
signed
(
regs_i
.
atmcr_f_thr_o
))
then
post_tag_coarse
(
post_tag_coarse
'left
downto
4
)
<=
unsigned
(
raw_coarse_i
)
-
1
;
post_tag_coarse
(
post_tag_coarse
'left
downto
5
)
<=
unsigned
(
raw_coarse_i
)
-
1
;
else
else
post_tag_coarse
(
post_tag_coarse
'left
downto
4
)
<=
unsigned
(
raw_coarse_i
);
post_tag_coarse
(
post_tag_coarse
'left
downto
5
)
<=
unsigned
(
raw_coarse_i
);
end
if
;
end
if
;
-- Pipeline stage 3:
-- Pipeline stage 3:
...
@@ -214,18 +212,19 @@ begin -- behavioral
...
@@ -214,18 +212,19 @@ begin -- behavioral
-- extra coarse counts from ACAM's frac part after rescaling
-- extra coarse counts from ACAM's frac part after rescaling
tag_frac_o
<=
std_logic_vector
(
post_frac_multiplied_d0
(
c_SCALER_SHIFT
+
g_frac_bits
-1
downto
c_SCALER_SHIFT
));
tag_frac_o
<=
std_logic_vector
(
post_frac_multiplied_d0
(
c_SCALER_SHIFT
+
g_frac_bits
-1
downto
c_SCALER_SHIFT
));
tag_valid_o
<=
pp_pipe
(
4
);
tag_valid_o
<=
pp_pipe
(
4
);
elsif
(
raw_valid_i
=
'1'
)
then
elsif
(
raw_valid_i
=
'1'
)
then
tag_utc_o
<=
raw_utc_i
;
tag_utc_o
<=
raw_utc_i
;
tag_coarse_o
<=
raw_coarse_i
&
raw_start_offset_i
;
tag_coarse_o
<=
raw_coarse_i
&
raw_start_offset_i
;
tag_frac_o
<=
raw_frac_i
(
11
downto
0
);
tag_frac_o
<=
raw_frac_i
(
11
downto
0
);
tag_dbg_raw_o
(
10
downto
0
)
<=
raw_frac_i
(
22
downto
12
);
tag_dbg_raw_o
(
10
downto
0
)
<=
raw_frac_i
(
22
downto
12
);
tag_dbg_raw_o
(
15
downto
11
)
<=
acam_subcycle_offset_i
;
tag_dbg_raw_o
(
15
downto
11
)
<=
acam_subcycle_offset_i
(
4
downto
0
);
tag_dbg_raw_o
(
23
downto
16
)
<=
raw_coarse_shifted_i
(
7
downto
0
);
tag_dbg_raw_o
(
23
downto
16
)
<=
raw_coarse_i
(
7
downto
0
);
tag_dbg_raw_o
(
31
downto
24
)
<=
raw_utc_shifted_i
(
7
downto
0
);
tag_dbg_raw_o
(
30
downto
24
)
<=
raw_utc_i
(
6
downto
0
);
tag_dbg_raw_o
(
31
)
<=
acam_subcycle_offset_i
(
5
);
tag_valid_o
<=
'1'
;
tag_valid_o
<=
'1'
;
else
else
...
...
hdl/rtl/fd_acam_timestamper.vhd
View file @
8f25c0df
This diff is collapsed.
Click to expand it.
hdl/rtl/fd_channel_wbgen2_pkg.vhd
View file @
8f25c0df
...
@@ -3,7 +3,7 @@
...
@@ -3,7 +3,7 @@
---------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------
-- File : fd_channel_wbgen2_pkg.vhd
-- File : fd_channel_wbgen2_pkg.vhd
-- Author : auto-generated by wbgen2 from fd_channel_wishbone_slave.wb
-- Author : auto-generated by wbgen2 from fd_channel_wishbone_slave.wb
-- Created :
Mon Jun 4 13:42:20 2012
-- Created :
Fri Feb 15 12:07:17 2013
-- Standard : VHDL'87
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE fd_channel_wishbone_slave.wb
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE fd_channel_wishbone_slave.wb
...
...
hdl/rtl/fd_channel_wishbone_slave.vhd
View file @
8f25c0df
...
@@ -3,7 +3,7 @@
...
@@ -3,7 +3,7 @@
---------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------
-- File : fd_channel_wishbone_slave.vhd
-- File : fd_channel_wishbone_slave.vhd
-- Author : auto-generated by wbgen2 from fd_channel_wishbone_slave.wb
-- Author : auto-generated by wbgen2 from fd_channel_wishbone_slave.wb
-- Created :
Mon Jun 4 13:42:20 2012
-- Created :
Fri Feb 15 12:07:17 2013
-- Standard : VHDL'87
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE fd_channel_wishbone_slave.wb
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE fd_channel_wishbone_slave.wb
...
@@ -161,11 +161,11 @@ begin
...
@@ -161,11 +161,11 @@ begin
end
if
;
end
if
;
rddata_reg
(
0
)
<=
fd_channel_dcr_enable_int
;
rddata_reg
(
0
)
<=
fd_channel_dcr_enable_int
;
rddata_reg
(
1
)
<=
fd_channel_dcr_mode_int
;
rddata_reg
(
1
)
<=
fd_channel_dcr_mode_int
;
rddata_reg
(
2
)
<=
'
X
'
;
rddata_reg
(
2
)
<=
'
0
'
;
rddata_reg
(
3
)
<=
fd_channel_dcr_pg_trig_sync1
;
rddata_reg
(
3
)
<=
fd_channel_dcr_pg_trig_sync1
;
rddata_reg
(
4
)
<=
'
X
'
;
rddata_reg
(
4
)
<=
'
0
'
;
rddata_reg
(
5
)
<=
fd_channel_dcr_upd_done_sync1
;
rddata_reg
(
5
)
<=
fd_channel_dcr_upd_done_sync1
;
rddata_reg
(
6
)
<=
'
X
'
;
rddata_reg
(
6
)
<=
'
0
'
;
rddata_reg
(
7
)
<=
fd_channel_dcr_no_fine_int
;
rddata_reg
(
7
)
<=
fd_channel_dcr_no_fine_int
;
rddata_reg
(
8
)
<=
fd_channel_dcr_force_hi_int
;
rddata_reg
(
8
)
<=
fd_channel_dcr_force_hi_int
;
rddata_reg
(
9
)
<=
'X'
;
rddata_reg
(
9
)
<=
'X'
;
...
...
hdl/rtl/fd_delay_line_arbiter.vhd
View file @
8f25c0df
...
@@ -6,7 +6,7 @@
...
@@ -6,7 +6,7 @@
-- Author : Tomasz Wlostowski
-- Author : Tomasz Wlostowski
-- Company : CERN
-- Company : CERN
-- Created : 2011-08-24
-- Created : 2011-08-24
-- Last update: 201
2-04-25
-- Last update: 201
3-02-21
-- Platform : FPGA-generic
-- Platform : FPGA-generic
-- Standard : VHDL'93
-- Standard : VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
...
@@ -70,7 +70,7 @@ entity fd_delay_line_arbiter is
...
@@ -70,7 +70,7 @@ entity fd_delay_line_arbiter is
end
fd_delay_line_arbiter
;
end
fd_delay_line_arbiter
;
architecture
behavioral
of
fd_delay_line_arbiter
is
architecture
behavioral
of
fd_delay_line_arbiter
is
signal
arb_sreg
:
std_logic_vector
(
4
*
3
-
1
downto
0
);
signal
arb_sreg
:
std_logic_vector
(
4
*
4
-
1
downto
0
);
type
t_dly_array
is
array
(
integer
range
<>
)
of
std_logic_vector
(
9
downto
0
);
type
t_dly_array
is
array
(
integer
range
<>
)
of
std_logic_vector
(
9
downto
0
);
...
@@ -78,6 +78,7 @@ architecture behavioral of fd_delay_line_arbiter is
...
@@ -78,6 +78,7 @@ architecture behavioral of fd_delay_line_arbiter is
signal
delay_vec
:
t_dly_array
(
0
to
3
);
signal
delay_vec
:
t_dly_array
(
0
to
3
);
signal
delay_len_reg
:
std_logic_vector
(
3
downto
0
);
signal
delay_len_reg
:
std_logic_vector
(
3
downto
0
);
signal
delay_val_reg
:
std_logic_vector
(
9
downto
0
);
signal
delay_val_reg
:
std_logic_vector
(
9
downto
0
);
signal
pending_reg
:
std_logic_vector
(
3
downto
0
);
begin
-- behavioral
begin
-- behavioral
...
@@ -93,31 +94,33 @@ begin -- behavioral
...
@@ -93,31 +94,33 @@ begin -- behavioral
if
rst_n_i
=
'0'
then
if
rst_n_i
=
'0'
then
delay_len_reg
<=
(
others
=>
'1'
);
delay_len_reg
<=
(
others
=>
'1'
);
delay_val_reg
<=
(
others
=>
'0'
);
delay_val_reg
<=
(
others
=>
'0'
);
delay_len_o
<=
(
others
=>
'1'
);
delay_len_o
<=
(
others
=>
'1'
);
-- done_reg <= (others => '0');
-- done_reg <= (others => '0');
done_o
<=
(
others
=>
'0'
);
done_o
<=
(
others
=>
'0'
);
arb_sreg
<=
std_logic_vector
(
to_unsigned
(
1
,
arb_sreg
'length
));
arb_sreg
<=
std_logic_vector
(
to_unsigned
(
1
,
arb_sreg
'length
));
pending_reg
<=
(
others
=>
'0'
);
else
else
arb_sreg
<=
arb_sreg
(
arb_sreg
'left
-1
downto
0
)
&
arb_sreg
(
arb_sreg
'left
);
arb_sreg
<=
arb_sreg
(
arb_sreg
'left
-1
downto
0
)
&
arb_sreg
(
arb_sreg
'left
);
for
i
in
0
to
3
loop
for
i
in
0
to
3
loop
if
(
arb_sreg
(
3
*
i
)
=
'1'
and
load_i
(
i
)
=
'1'
)
then
delay_val_reg
<=
delay_vec
(
i
);
delay_len_reg
(
i
)
<=
'0'
;
done_o
(
i
)
<=
'1'
;
end
if
;
if
(
arb_sreg
(
3
*
i
+
1
)
=
'1'
)
then
delay_val_reg
<=
delay_vec
(
i
);
done_o
(
i
)
<=
'0'
;
end
if
;
if
(
arb_sreg
(
4
*
i
)
=
'1'
and
load_i
(
i
)
=
'1'
)
then
if
(
arb_sreg
(
3
*
i
+
2
)
=
'1'
)
then
delay_val_reg
<=
delay_vec
(
i
);
delay_val_reg
<=
delay_vec
(
i
);
pending_reg
(
i
)
<=
'1'
;
delay_len_reg
(
i
)
<=
'1'
;
delay_len_reg
(
i
)
<=
'1'
;
done_o
(
i
)
<=
'0'
;
done_o
(
i
)
<=
'0'
;
elsif
(
arb_sreg
(
4
*
i
+
1
)
=
'1'
)
then
delay_len_reg
(
i
)
<=
not
pending_reg
(
i
);
done_o
(
i
)
<=
'0'
;
elsif
(
arb_sreg
(
4
*
i
+
2
)
=
'1'
)
then
delay_len_reg
(
i
)
<=
not
pending_reg
(
i
);
done_o
(
i
)
<=
'0'
;
elsif
(
arb_sreg
(
4
*
i
+
3
)
=
'1'
)
then
delay_len_reg
(
i
)
<=
'1'
;
done_o
(
i
)
<=
pending_reg
(
i
);
pending_reg
(
i
)
<=
'0'
;
else
done_o
(
i
)
<=
'0'
;
end
if
;
end
if
;
end
loop
;
-- i in 0 to 3
end
loop
;
-- i in 0 to 3
...
...
hdl/rtl/fd_main_wbgen2_pkg.vhd
View file @
8f25c0df
...
@@ -3,7 +3,7 @@
...
@@ -3,7 +3,7 @@
---------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------
-- File : fd_main_wbgen2_pkg.vhd
-- File : fd_main_wbgen2_pkg.vhd
-- Author : auto-generated by wbgen2 from fd_main_wishbone_slave.wb
-- Author : auto-generated by wbgen2 from fd_main_wishbone_slave.wb
-- Created : Fri
Dec 14 11:28:02 2012
-- Created : Fri
Feb 15 12:07:16 2013
-- Standard : VHDL'87
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE fd_main_wishbone_slave.wb
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE fd_main_wishbone_slave.wb
...
@@ -130,7 +130,7 @@ package fd_main_wbgen2_pkg is
...
@@ -130,7 +130,7 @@ package fd_main_wbgen2_pkg is
calr_cal_dmtd_o
:
std_logic
;
calr_cal_dmtd_o
:
std_logic
;
calr_psel_o
:
std_logic_vector
(
3
downto
0
);
calr_psel_o
:
std_logic_vector
(
3
downto
0
);
adsfr_o
:
std_logic_vector
(
17
downto
0
);
adsfr_o
:
std_logic_vector
(
17
downto
0
);
atmcr_c_thr_o
:
std_logic_vector
(
3
downto
0
);
atmcr_c_thr_o
:
std_logic_vector
(
7
downto
0
);
atmcr_f_thr_o
:
std_logic_vector
(
22
downto
0
);
atmcr_f_thr_o
:
std_logic_vector
(
22
downto
0
);
asor_offset_o
:
std_logic_vector
(
22
downto
0
);
asor_offset_o
:
std_logic_vector
(
22
downto
0
);
iepd_rst_stat_o
:
std_logic
;
iepd_rst_stat_o
:
std_logic
;
...
...
hdl/rtl/fd_main_wishbone_slave.vhd
View file @
8f25c0df
...
@@ -3,7 +3,7 @@
...
@@ -3,7 +3,7 @@
---------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------
-- File : fd_main_wishbone_slave.vhd
-- File : fd_main_wishbone_slave.vhd
-- Author : auto-generated by wbgen2 from fd_main_wishbone_slave.wb
-- Author : auto-generated by wbgen2 from fd_main_wishbone_slave.wb
-- Created : Fri
Dec 14 11:28:02 2012
-- Created : Fri
Feb 15 12:07:16 2013
-- Standard : VHDL'87
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE fd_main_wishbone_slave.wb
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE fd_main_wishbone_slave.wb
...
@@ -159,7 +159,7 @@ signal fd_main_adsfr_swb_delay : std_logic ;
...
@@ -159,7 +159,7 @@ signal fd_main_adsfr_swb_delay : std_logic ;
signal
fd_main_adsfr_swb_s0
:
std_logic
;
signal
fd_main_adsfr_swb_s0
:
std_logic
;
signal
fd_main_adsfr_swb_s1
:
std_logic
;
signal
fd_main_adsfr_swb_s1
:
std_logic
;
signal
fd_main_adsfr_swb_s2
:
std_logic
;
signal
fd_main_adsfr_swb_s2
:
std_logic
;
signal
fd_main_atmcr_c_thr_int
:
std_logic_vector
(
3
downto
0
);
signal
fd_main_atmcr_c_thr_int
:
std_logic_vector
(
7
downto
0
);
signal
fd_main_atmcr_c_thr_swb
:
std_logic
;
signal
fd_main_atmcr_c_thr_swb
:
std_logic
;
signal
fd_main_atmcr_c_thr_swb_delay
:
std_logic
;
signal
fd_main_atmcr_c_thr_swb_delay
:
std_logic
;
signal
fd_main_atmcr_c_thr_swb_s0
:
std_logic
;
signal
fd_main_atmcr_c_thr_swb_s0
:
std_logic
;
...
@@ -332,7 +332,7 @@ begin
...
@@ -332,7 +332,7 @@ begin
fd_main_adsfr_int
<=
"000000000000000000"
;
fd_main_adsfr_int
<=
"000000000000000000"
;
fd_main_adsfr_swb
<=
'0'
;
fd_main_adsfr_swb
<=
'0'
;
fd_main_adsfr_swb_delay
<=
'0'
;
fd_main_adsfr_swb_delay
<=
'0'
;
fd_main_atmcr_c_thr_int
<=
"0000"
;
fd_main_atmcr_c_thr_int
<=
"0000
0000
"
;
fd_main_atmcr_c_thr_swb
<=
'0'
;
fd_main_atmcr_c_thr_swb
<=
'0'
;
fd_main_atmcr_c_thr_swb_delay
<=
'0'
;
fd_main_atmcr_c_thr_swb_delay
<=
'0'
;
fd_main_atmcr_f_thr_int
<=
"00000000000000000000000"
;
fd_main_atmcr_f_thr_int
<=
"00000000000000000000000"
;
...
@@ -373,8 +373,8 @@ begin
...
@@ -373,8 +373,8 @@ begin
fd_main_tsbir_timeout_int
<=
"0000000000"
;
fd_main_tsbir_timeout_int
<=
"0000000000"
;
fd_main_tsbir_threshold_int
<=
"000000000000"
;
fd_main_tsbir_threshold_int
<=
"000000000000"
;
fid_read_ack_o
<=
'0'
;
fid_read_ack_o
<=
'0'
;
fd_main_i2cr_scl_out_int
<=
'
0
'
;
fd_main_i2cr_scl_out_int
<=
'
1
'
;
fd_main_i2cr_sda_out_int
<=
'
0
'
;
fd_main_i2cr_sda_out_int
<=
'
1
'
;
fd_main_tder2_pelt_drive_int
<=
"00000000000000000000000000000000"
;
fd_main_tder2_pelt_drive_int
<=
"00000000000000000000000000000000"
;
fd_main_tsbr_advance_adv_int
<=
'0'
;
fd_main_tsbr_advance_adv_int
<=
'0'
;
eic_idr_write_int
<=
'0'
;
eic_idr_write_int
<=
'0'
;
...
@@ -595,8 +595,8 @@ begin
...
@@ -595,8 +595,8 @@ begin
rddata_reg
(
3
)
<=
regs_i
.
tcr_wr_present_i
;
rddata_reg
(
3
)
<=
regs_i
.
tcr_wr_present_i
;
rddata_reg
(
4
)
<=
regs_i
.
tcr_wr_ready_i
;
rddata_reg
(
4
)
<=
regs_i
.
tcr_wr_ready_i
;
rddata_reg
(
5
)
<=
regs_i
.
tcr_wr_link_i
;
rddata_reg
(
5
)
<=
regs_i
.
tcr_wr_link_i
;
rddata_reg
(
6
)
<=
'
X
'
;
rddata_reg
(
6
)
<=
'
0
'
;
rddata_reg
(
7
)
<=
'
X
'
;
rddata_reg
(
7
)
<=
'
0
'
;
rddata_reg
(
8
)
<=
'X'
;
rddata_reg
(
8
)
<=
'X'
;
rddata_reg
(
9
)
<=
'X'
;
rddata_reg
(
9
)
<=
'X'
;
rddata_reg
(
10
)
<=
'X'
;
rddata_reg
(
10
)
<=
'X'
;
...
@@ -736,14 +736,14 @@ begin
...
@@ -736,14 +736,14 @@ begin
fd_main_tdcsr_alutrig_int
<=
wrdata_reg
(
7
);
fd_main_tdcsr_alutrig_int
<=
wrdata_reg
(
7
);
fd_main_tdcsr_alutrig_int_delay
<=
wrdata_reg
(
7
);
fd_main_tdcsr_alutrig_int_delay
<=
wrdata_reg
(
7
);
end
if
;
end
if
;
rddata_reg
(
0
)
<=
'
X
'
;
rddata_reg
(
0
)
<=
'
0
'
;
rddata_reg
(
1
)
<=
'
X
'
;
rddata_reg
(
1
)
<=
'
0
'
;
rddata_reg
(
2
)
<=
fd_main_tdcsr_empty_sync1
;
rddata_reg
(
2
)
<=
fd_main_tdcsr_empty_sync1
;
rddata_reg
(
3
)
<=
'
X
'
;
rddata_reg
(
3
)
<=
'
0
'
;
rddata_reg
(
4
)
<=
'
X
'
;
rddata_reg
(
4
)
<=
'
0
'
;
rddata_reg
(
5
)
<=
'
X
'
;
rddata_reg
(
5
)
<=
'
0
'
;
rddata_reg
(
6
)
<=
'
X
'
;
rddata_reg
(
6
)
<=
'
0
'
;
rddata_reg
(
7
)
<=
'
X
'
;
rddata_reg
(
7
)
<=
'
0
'
;
rddata_reg
(
8
)
<=
'X'
;
rddata_reg
(
8
)
<=
'X'
;
rddata_reg
(
9
)
<=
'X'
;
rddata_reg
(
9
)
<=
'X'
;
rddata_reg
(
10
)
<=
'X'
;
rddata_reg
(
10
)
<=
'X'
;
...
@@ -780,7 +780,7 @@ begin
...
@@ -780,7 +780,7 @@ begin
fd_main_calr_psel_swb
<=
'1'
;
fd_main_calr_psel_swb
<=
'1'
;
fd_main_calr_psel_swb_delay
<=
'1'
;
fd_main_calr_psel_swb_delay
<=
'1'
;
end
if
;
end
if
;
rddata_reg
(
0
)
<=
'
X
'
;
rddata_reg
(
0
)
<=
'
0
'
;
rddata_reg
(
1
)
<=
fd_main_calr_cal_pps_int
;
rddata_reg
(
1
)
<=
fd_main_calr_cal_pps_int
;
rddata_reg
(
2
)
<=
fd_main_calr_cal_dmtd_int
;
rddata_reg
(
2
)
<=
fd_main_calr_cal_dmtd_int
;
rddata_reg
(
6
downto
3
)
<=
fd_main_calr_psel_int
;
rddata_reg
(
6
downto
3
)
<=
fd_main_calr_psel_int
;
...
@@ -852,19 +852,15 @@ begin
...
@@ -852,19 +852,15 @@ begin
ack_in_progress
<=
'1'
;
ack_in_progress
<=
'1'
;
when
"001101"
=>
when
"001101"
=>
if
(
wb_we_i
=
'1'
)
then
if
(
wb_we_i
=
'1'
)
then
fd_main_atmcr_c_thr_int
<=
wrdata_reg
(
3
downto
0
);
fd_main_atmcr_c_thr_int
<=
wrdata_reg
(
7
downto
0
);
fd_main_atmcr_c_thr_swb
<=
'1'
;
fd_main_atmcr_c_thr_swb
<=
'1'
;
fd_main_atmcr_c_thr_swb_delay
<=
'1'
;
fd_main_atmcr_c_thr_swb_delay
<=
'1'
;
fd_main_atmcr_f_thr_int
<=
wrdata_reg
(
26
downto
4
);
fd_main_atmcr_f_thr_int
<=
wrdata_reg
(
30
downto
8
);
fd_main_atmcr_f_thr_swb
<=
'1'
;
fd_main_atmcr_f_thr_swb
<=
'1'
;
fd_main_atmcr_f_thr_swb_delay
<=
'1'
;
fd_main_atmcr_f_thr_swb_delay
<=
'1'
;
end
if
;
end
if
;
rddata_reg
(
3
downto
0
)
<=
fd_main_atmcr_c_thr_int
;
rddata_reg
(
7
downto
0
)
<=
fd_main_atmcr_c_thr_int
;
rddata_reg
(
26
downto
4
)
<=
fd_main_atmcr_f_thr_int
;
rddata_reg
(
30
downto
8
)
<=
fd_main_atmcr_f_thr_int
;
rddata_reg
(
27
)
<=
'X'
;
rddata_reg
(
28
)
<=
'X'
;
rddata_reg
(
29
)
<=
'X'
;
rddata_reg
(
30
)
<=
'X'
;
rddata_reg
(
31
)
<=
'X'
;
rddata_reg
(
31
)
<=
'X'
;
ack_sreg
(
3
)
<=
'1'
;
ack_sreg
(
3
)
<=
'1'
;
ack_in_progress
<=
'1'
;
ack_in_progress
<=
'1'
;
...
@@ -911,7 +907,7 @@ begin
...
@@ -911,7 +907,7 @@ begin
fd_main_iepd_rst_stat_int
<=
wrdata_reg
(
0
);
fd_main_iepd_rst_stat_int
<=
wrdata_reg
(
0
);
fd_main_iepd_rst_stat_int_delay
<=
wrdata_reg
(
0
);
fd_main_iepd_rst_stat_int_delay
<=
wrdata_reg
(
0
);
end
if
;
end
if
;
rddata_reg
(
0
)
<=
'
X
'
;
rddata_reg
(
0
)
<=
'
0
'
;
if
(
wb_we_i
=
'0'
)
then
if
(
wb_we_i
=
'0'
)
then
fd_main_iepd_pdelay_lwb
<=
'1'
;
fd_main_iepd_pdelay_lwb
<=
'1'
;
fd_main_iepd_pdelay_lwb_delay
<=
'1'
;
fd_main_iepd_pdelay_lwb_delay
<=
'1'
;
...
@@ -957,7 +953,7 @@ begin
...
@@ -957,7 +953,7 @@ begin
rddata_reg
(
26
)
<=
fd_main_scr_sel_gpio_int
;
rddata_reg
(
26
)
<=
fd_main_scr_sel_gpio_int
;
rddata_reg
(
27
)
<=
regs_i
.
scr_ready_i
;
rddata_reg
(
27
)
<=
regs_i
.
scr_ready_i
;
rddata_reg
(
28
)
<=
fd_main_scr_cpol_int
;
rddata_reg
(
28
)
<=
fd_main_scr_cpol_int
;
rddata_reg
(
29
)
<=
'
X
'
;
rddata_reg
(
29
)
<=
'
0
'
;
rddata_reg
(
30
)
<=
'X'
;
rddata_reg
(
30
)
<=
'X'
;
rddata_reg
(
31
)
<=
'X'
;
rddata_reg
(
31
)
<=
'X'
;
ack_sreg
(
2
)
<=
'1'
;
ack_sreg
(
2
)
<=
'1'
;
...
@@ -985,8 +981,8 @@ begin
...
@@ -985,8 +981,8 @@ begin
end
if
;
end
if
;
rddata_reg
(
4
downto
0
)
<=
fd_main_tsbcr_chan_mask_int
;
rddata_reg
(
4
downto
0
)
<=
fd_main_tsbcr_chan_mask_int
;
rddata_reg
(
5
)
<=
fd_main_tsbcr_enable_int
;
rddata_reg
(
5
)
<=
fd_main_tsbcr_enable_int
;
rddata_reg
(
6
)
<=
'
X
'
;
rddata_reg
(
6
)
<=
'
0
'
;
rddata_reg
(
7
)
<=
'
X
'
;
rddata_reg
(
7
)
<=
'
0
'
;
rddata_reg
(
8
)
<=
regs_i
.
tsbcr_full_i
;
rddata_reg
(
8
)
<=
regs_i
.
tsbcr_full_i
;
rddata_reg
(
9
)
<=
regs_i
.
tsbcr_empty_i
;
rddata_reg
(
9
)
<=
regs_i
.
tsbcr_empty_i
;
tsbcr_read_ack_o
<=
'1'
;
tsbcr_read_ack_o
<=
'1'
;
...
@@ -1139,7 +1135,7 @@ begin
...
@@ -1139,7 +1135,7 @@ begin
if
(
wb_we_i
=
'1'
)
then
if
(
wb_we_i
=
'1'
)
then
fd_main_tsbr_advance_adv_int
<=
wrdata_reg
(
0
);
fd_main_tsbr_advance_adv_int
<=
wrdata_reg
(
0
);
end
if
;
end
if
;
rddata_reg
(
0
)
<=
'
X
'
;
rddata_reg
(
0
)
<=
'
0
'
;
rddata_reg
(
0
)
<=
'X'
;
rddata_reg
(
0
)
<=
'X'
;
rddata_reg
(
1
)
<=
'X'
;
rddata_reg
(
1
)
<=
'X'
;
rddata_reg
(
2
)
<=
'X'
;
rddata_reg
(
2
)
<=
'X'
;
...
@@ -1376,7 +1372,7 @@ begin
...
@@ -1376,7 +1372,7 @@ begin
-- PLL Locked
-- PLL Locked
-- Mezzani
c
e Present
-- Mezzani
n
e Present
-- DMTD Clock Status
-- DMTD Clock Status
-- WR Timing Enable
-- WR Timing Enable
regs_o
.
tcr_wr_enable_o
<=
fd_main_tcr_wr_enable_int
;
regs_o
.
tcr_wr_enable_o
<=
fd_main_tcr_wr_enable_int
;
...
@@ -1478,8 +1474,8 @@ begin
...
@@ -1478,8 +1474,8 @@ begin
end
process
;
end
process
;
-- Reference clock cycles
-- Reference clock cycles
(0...124999999)
-- asynchronous std_logic_vector register : Reference clock cycles (type RW/WO, clk_ref_i <-> clk_sys_i)
-- asynchronous std_logic_vector register : Reference clock cycles (
0...124999999) (
type RW/WO, clk_ref_i <-> clk_sys_i)
process
(
clk_ref_i
,
rst_n_i
)
process
(
clk_ref_i
,
rst_n_i
)
begin
begin
if
(
rst_n_i
=
'0'
)
then
if
(
rst_n_i
=
'0'
)
then
...
@@ -1538,7 +1534,7 @@ begin
...
@@ -1538,7 +1534,7 @@ begin
end
process
;
end
process
;
--
Start TDC write
--
Write to TDC
process
(
clk_ref_i
,
rst_n_i
)
process
(
clk_ref_i
,
rst_n_i
)
begin
begin
if
(
rst_n_i
=
'0'
)
then
if
(
rst_n_i
=
'0'
)
then
...
@@ -1555,7 +1551,7 @@ begin
...
@@ -1555,7 +1551,7 @@ begin
end
process
;
end
process
;
--
Start TDC read
--
Read from TDC
process
(
clk_ref_i
,
rst_n_i
)
process
(
clk_ref_i
,
rst_n_i
)
begin
begin
if
(
rst_n_i
=
'0'
)
then
if
(
rst_n_i
=
'0'
)
then
...
@@ -1586,7 +1582,7 @@ begin
...
@@ -1586,7 +1582,7 @@ begin
end
process
;
end
process
;
-- St
art
enable
-- St
op
enable
process
(
clk_ref_i
,
rst_n_i
)
process
(
clk_ref_i
,
rst_n_i
)
begin
begin
if
(
rst_n_i
=
'0'
)
then
if
(
rst_n_i
=
'0'
)
then
...
@@ -1620,7 +1616,7 @@ begin
...
@@ -1620,7 +1616,7 @@ begin
end
process
;
end
process
;
-- St
op
enable
-- St
art
enable
process
(
clk_ref_i
,
rst_n_i
)
process
(
clk_ref_i
,
rst_n_i
)
begin
begin
if
(
rst_n_i
=
'0'
)
then
if
(
rst_n_i
=
'0'
)
then
...
@@ -1654,7 +1650,7 @@ begin
...
@@ -1654,7 +1650,7 @@ begin
end
process
;
end
process
;
--
write 1: Pulse the Alutrigger
line
--
Pulse <code>Alutrigger</code>
line
process
(
clk_ref_i
,
rst_n_i
)
process
(
clk_ref_i
,
rst_n_i
)
begin
begin
if
(
rst_n_i
=
'0'
)
then
if
(
rst_n_i
=
'0'
)
then
...
@@ -1671,7 +1667,7 @@ begin
...
@@ -1671,7 +1667,7 @@ begin
end
process
;
end
process
;
--
Triggers calibration pulses
--
Generate calibration pulses (type 1 calibration)
process
(
clk_ref_i
,
rst_n_i
)
process
(
clk_ref_i
,
rst_n_i
)
begin
begin
if
(
rst_n_i
=
'0'
)
then
if
(
rst_n_i
=
'0'
)
then
...
@@ -1704,10 +1700,10 @@ begin
...
@@ -1704,10 +1700,10 @@ begin
end
process
;
end
process
;
-- Produce DDMTD calibration pattern
-- Produce DDMTD calibration pattern
(type 2 calibration)
regs_o
.
calr_cal_dmtd_o
<=
fd_main_calr_cal_dmtd_int
;
regs_o
.
calr_cal_dmtd_o
<=
fd_main_calr_cal_dmtd_int
;
--
Enable pulse generation
--
Calibration pulse output select/mask
-- asynchronous std_logic_vector register :
Enable pulse generation
(type RW/RO, clk_ref_i <-> clk_sys_i)
-- asynchronous std_logic_vector register :
Calibration pulse output select/mask
(type RW/RO, clk_ref_i <-> clk_sys_i)
process
(
clk_ref_i
,
rst_n_i
)
process
(
clk_ref_i
,
rst_n_i
)
begin
begin
if
(
rst_n_i
=
'0'
)
then
if
(
rst_n_i
=
'0'
)
then
...
@@ -1758,7 +1754,7 @@ begin
...
@@ -1758,7 +1754,7 @@ begin
fd_main_atmcr_c_thr_swb_s0
<=
'0'
;
fd_main_atmcr_c_thr_swb_s0
<=
'0'
;
fd_main_atmcr_c_thr_swb_s1
<=
'0'
;
fd_main_atmcr_c_thr_swb_s1
<=
'0'
;
fd_main_atmcr_c_thr_swb_s2
<=
'0'
;
fd_main_atmcr_c_thr_swb_s2
<=
'0'
;
regs_o
.
atmcr_c_thr_o
<=
"0000"
;
regs_o
.
atmcr_c_thr_o
<=
"0000
0000
"
;
elsif
rising_edge
(
clk_ref_i
)
then
elsif
rising_edge
(
clk_ref_i
)
then
fd_main_atmcr_c_thr_swb_s0
<=
fd_main_atmcr_c_thr_swb
;
fd_main_atmcr_c_thr_swb_s0
<=
fd_main_atmcr_c_thr_swb
;
fd_main_atmcr_c_thr_swb_s1
<=
fd_main_atmcr_c_thr_swb_s0
;
fd_main_atmcr_c_thr_swb_s1
<=
fd_main_atmcr_c_thr_swb_s0
;
...
...
hdl/rtl/fd_main_wishbone_slave.wb
View file @
8f25c0df
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