Skip to content

F
FMC DEL 1ns 4cha
Commit 8f25c0df authored by Tomasz Wlostowski's avatar Tomasz Wlostowski
Browse files
Options

hdl: use the TDC in G-mode (testing only)

parent f5497277
Hide whitespace changes
Inline Side-by-side
Showing with 235 additions and 217 deletions
hdl/rtl/fd_acam_timestamp_postprocessor.vhd
View file @ 8f25c0df
......@@ -6,7 +6,7 @@
-- Author : Tomasz Wlostowski
-- Company : CERN
-- Created : 2011-08-29
-- Last update: 2012-05-18
-- Last update: 2013-02-06
-- Platform : FPGA-generic
-- Standard : VHDL'93
-------------------------------------------------------------------------------
......@@ -60,24 +60,22 @@ entity fd_acam_timestamp_postprocessor is
raw_valid_i : in std_logic;
raw_utc_i : in std_logic_vector(c_TIMESTAMP_UTC_BITS-1 downto 0);
raw_utc_shifted_i : in std_logic_vector(c_TIMESTAMP_UTC_BITS-1 downto 0);
-- "start number" (value of coarse counter, counting at every start pulse of the
-- TDC, i.e. 125 MHz / 16 = 7.8215 MHz)
raw_coarse_i : in std_logic_vector(c_TIMESTAMP_COARSE_BITS-4-1 downto 0);
raw_coarse_shifted_i : in std_logic_vector(c_TIMESTAMP_COARSE_BITS-4-1 downto 0);
-- TDC, i.e. 125 MHz / 32 = 3.90625 MHz)
raw_coarse_i : in std_logic_vector(c_TIMESTAMP_COARSE_BITS-5-1 downto 0);
-- raw fractional timestamp generated by ACAM
raw_frac_i : in std_logic_vector(22 downto 0);
-- coarse offset (in 125 MHz clock cycles) from the last ACAM's start pulse to the
-- input pulse (0..15)
raw_start_offset_i : in std_logic_vector(3 downto 0);
raw_start_offset_i : in std_logic_vector(4 downto 0);
-- Offset between the actual timescale and the ACAM fixed start signal generated
-- by the AD9516 PLL. Used to align the timestamps to the externally
-- provided time base (e.g. by White Rabbit).
acam_subcycle_offset_i : in std_logic_vector(4 downto 0);
acam_subcycle_offset_i : in std_logic_vector(5 downto 0);
---------------------------------------------------------------------------
-- Post-processed timestamp. WARNING! DE-NORMALIZED!
......@@ -150,7 +148,7 @@ begin -- behavioral
pp_pipe(0) <= raw_valid_i;
post_frac_start_adj <= signed(raw_frac_i) - signed(regs_i.asor_offset_o);
post_tag_coarse(3 downto 0) <= (others => '0');
post_tag_coarse(4 downto 0) <= (others => '0');
post_tag_utc <= unsigned(raw_utc_i);
-- pipeline stage 2:
......@@ -164,9 +162,9 @@ begin -- behavioral
pp_pipe(1) <= pp_pipe(0);
if (unsigned(raw_start_offset_i) <= unsigned(regs_i.atmcr_c_thr_o)) and (post_frac_start_adj > signed(regs_i.atmcr_f_thr_o)) then
post_tag_coarse(post_tag_coarse'left downto 4) <= unsigned(raw_coarse_i) - 1;
post_tag_coarse(post_tag_coarse'left downto 5) <= unsigned(raw_coarse_i) - 1;
else
post_tag_coarse(post_tag_coarse'left downto 4) <= unsigned(raw_coarse_i);
post_tag_coarse(post_tag_coarse'left downto 5) <= unsigned(raw_coarse_i);
end if;
-- Pipeline stage 3:
......@@ -214,18 +212,19 @@ begin -- behavioral
-- extra coarse counts from ACAM's frac part after rescaling
tag_frac_o <= std_logic_vector(post_frac_multiplied_d0(c_SCALER_SHIFT + g_frac_bits-1 downto c_SCALER_SHIFT));
tag_frac_o <= std_logic_vector(post_frac_multiplied_d0(c_SCALER_SHIFT + g_frac_bits-1 downto c_SCALER_SHIFT));
tag_valid_o <= pp_pipe(4);
elsif(raw_valid_i = '1') then
tag_utc_o <= raw_utc_i;
tag_coarse_o <= raw_coarse_i & raw_start_offset_i;
tag_frac_o <= raw_frac_i(11 downto 0);
tag_dbg_raw_o(10 downto 0) <= raw_frac_i(22 downto 12);
tag_dbg_raw_o(15 downto 11) <= acam_subcycle_offset_i;
tag_dbg_raw_o(23 downto 16) <= raw_coarse_shifted_i(7 downto 0);
tag_dbg_raw_o(31 downto 24) <= raw_utc_shifted_i(7 downto 0);
tag_utc_o <= raw_utc_i;
tag_coarse_o <= raw_coarse_i & raw_start_offset_i;
tag_frac_o <= raw_frac_i(11 downto 0);
tag_dbg_raw_o(10 downto 0) <= raw_frac_i(22 downto 12);
tag_dbg_raw_o(15 downto 11) <= acam_subcycle_offset_i(4 downto 0);
tag_dbg_raw_o(23 downto 16) <= raw_coarse_i(7 downto 0);
tag_dbg_raw_o(30 downto 24) <= raw_utc_i(6 downto 0);
tag_dbg_raw_o(31) <= acam_subcycle_offset_i(5);
tag_valid_o <= '1';
else
......
hdl/rtl/fd_acam_timestamper.vhd
View file @ 8f25c0df
......@@ -6,7 +6,7 @@
-- Author : Tomasz Wlostowski
-- Company : CERN
-- Created : 2011-08-24
-- Last update: 2012-05-18
-- Last update: 2013-02-12
-- Platform : FPGA-generic
-- Standard : VHDL'93
-------------------------------------------------------------------------------
......@@ -165,12 +165,10 @@ architecture behavioral of fd_acam_timestamper is
rst_n_i : in std_logic;
raw_valid_i : in std_logic;
raw_utc_i : in std_logic_vector(c_TIMESTAMP_UTC_BITS-1 downto 0);
raw_utc_shifted_i : in std_logic_vector(c_TIMESTAMP_UTC_BITS-1 downto 0);
raw_coarse_i : in std_logic_vector(c_TIMESTAMP_COARSE_BITS-4-1 downto 0);
raw_coarse_shifted_i : in std_logic_vector(c_TIMESTAMP_COARSE_BITS-4-1 downto 0);
raw_coarse_i : in std_logic_vector(c_TIMESTAMP_COARSE_BITS-5-1 downto 0);
raw_frac_i : in std_logic_vector(22 downto 0);
raw_start_offset_i : in std_logic_vector(3 downto 0);
acam_subcycle_offset_i : in std_logic_vector(4 downto 0);
raw_start_offset_i : in std_logic_vector(4 downto 0);
acam_subcycle_offset_i : in std_logic_vector(5 downto 0);
tag_valid_o : out std_logic;
tag_utc_o : out std_logic_vector(c_TIMESTAMP_UTC_BITS-1 downto 0);
tag_coarse_o : out std_logic_vector(c_TIMESTAMP_COARSE_BITS-1 downto 0);
......@@ -192,18 +190,18 @@ architecture behavioral of fd_acam_timestamper is
-- maximum time (in clk_ref_i cycles) between the input pulse and the presence
-- of its timestamp in ACAM's output FIFO.
constant c_ACAM_TIMEOUT : integer := 60;
constant c_FALLING_REENABLE_TIMEOUT : integer := 62; -- 500 ns safety delay
constant c_ACAM_PURGE_TIMEOUT : unsigned(3 downto 0) := to_unsigned(15, 4);
constant c_FALLING_REENABLE_TIMEOUT : integer := 32; -- 500 ns safety delay
constant c_ones : std_logic_vector(31 downto 0) := x"ffffffff";
-- states of the main ACAM FSM reading/writing data from/to the TDC
type t_acam_fsm_state is (IDLE, R_ADDR, R_PULSE, R_READ, R_EXTEND_R_PULSE1, R_END_CYCLE, R_ADDR2, W_DATA_ADDR, W_PULSE, W_WAIT,
RMODE_PURGE_FIFO,
RMODE_PURGE_WAIT,
RMODE_PURGE_WAIT2,
RMODE_PURGE_CHECK_EMPTY,
RMODE_READ,
RMODE_READ_PULSE,
RMODE_READ_PULSE2,
RMODE_READ_PULSE3,
R_EXTEND_R_PULSE2,
RMODE_CHECK_WIDTH,
RMODE_MEASURE_WIDTH);
......@@ -224,21 +222,19 @@ architecture behavioral of fd_acam_timestamper is
signal trig_pulse : std_logic;
-- counters (internal time base)
signal start_count : unsigned(3 downto 0);
signal coarse_count : unsigned(c_TIMESTAMP_COARSE_BITS-4-1 downto 0);
signal coarse_count_shifted : unsigned(c_TIMESTAMP_COARSE_BITS-4-1 downto 0);
signal utc_count : unsigned(c_TIMESTAMP_UTC_BITS-1 downto 0);
signal utc_count_shifted : unsigned(c_TIMESTAMP_UTC_BITS-1 downto 0);
signal subcycle_offset : signed(4 downto 0);
signal start_count : unsigned(4 downto 0);
signal coarse_count : unsigned(c_TIMESTAMP_COARSE_BITS-5-1 downto 0);
signal utc_count : unsigned(c_TIMESTAMP_UTC_BITS-1 downto 0);
signal subcycle_offset : signed(5 downto 0);
signal gcr_input_en_d0 : std_logic;
-- raw (unprocessed) time tag
signal raw_tag_valid : std_logic;
signal raw_tag_coarse, raw_tag_coarse_sh : unsigned(c_TIMESTAMP_COARSE_BITS-4-1 downto 0);
signal raw_tag_frac : signed(22 downto 0);
signal raw_tag_start_offset : unsigned(3 downto 0);
signal raw_tag_utc, raw_tag_utc_sh : unsigned(c_TIMESTAMP_UTC_BITS-1 downto 0);
signal raw_tag_valid : std_logic;
signal raw_tag_coarse : unsigned(c_TIMESTAMP_COARSE_BITS-5-1 downto 0);
signal raw_tag_frac : signed(22 downto 0);
signal raw_tag_start_offset : unsigned(4 downto 0);
signal raw_tag_utc : unsigned(c_TIMESTAMP_UTC_BITS-1 downto 0);
signal width_check_sreg : std_logic_vector(g_min_pulse_width-2 downto 0);
signal width_check_mask : std_logic_vector(g_min_pulse_width-2 downto 0);
......@@ -259,10 +255,13 @@ architecture behavioral of fd_acam_timestamper is
signal tag_valid_int : std_logic;
signal tag_coarse : std_logic_vector(27 downto 0);
signal mask_stop : std_logic;
signal safety_counter : unsigned(7 downto 0);
signal safety_counter_mask : std_logic;
signal mask_stop_clamp : std_logic;
signal safety_counter : unsigned(7 downto 0);
signal purge_count : unsigned(3 downto 0);
signal acam_restart : std_logic;
signal start_mask : std_logic;
begin -- behave
......@@ -278,18 +277,13 @@ begin -- behave
begin
if rising_edge(clk_ref_i) then
if(rst_n_i = '0') then
trig_d <= (others => '0');
trig_pulse <= '0';
tag_enable_d <= (others => '0');
trig_d <= (others => '0');
trig_pulse <= '0';
else
trig_d(0) <= trig_a_i and tag_enable;
trig_d(1) <= trig_d(0) and tag_enable_d(0);
trig_d(2) <= trig_d(1) and tag_enable_d(1);
trig_pulse <= (trig_d(1) and not trig_d(2)) and tag_enable_d(2) and not mask_stop_clamp;
tag_enable_d(0) <= tag_enable;
tag_enable_d(1) <= tag_enable_d(0);
tag_enable_d(2) <= tag_enable_d(1);
trig_d(0) <= trig_a_i;
trig_d(1) <= trig_d(0);
trig_d(2) <= trig_d(1);
trig_pulse <= (trig_d(1) and not trig_d(2)) and tag_enable and (not safety_counter_mask);
end if;
end if;
end process;
......@@ -298,17 +292,16 @@ begin -- behave
begin
if rising_edge(clk_ref_i) then
if rst_n_i = '0' then
safety_counter <= (others => '0');
mask_stop_clamp <= '0';
safety_counter <= to_unsigned(c_FALLING_REENABLE_TIMEOUT, safety_counter'length);
safety_counter_mask <= '1';
else
if(trig_d(2) = '1' and tag_enable = '1')then
mask_stop_clamp <= '1';
safety_counter <= to_unsigned(c_FALLING_REENABLE_TIMEOUT, safety_counter'length);
elsif(trig_d(2) = '0' and tag_enable = '1') then
if(trig_d(2) = '1') then
safety_counter <= to_unsigned(c_FALLING_REENABLE_TIMEOUT, safety_counter'length);
safety_counter_mask <= '1';
else
safety_counter <= safety_counter-1;
if(safety_counter = 0) then
mask_stop_clamp <= '0';
safety_counter_mask <= '0';
end if;
end if;
end if;
......@@ -377,7 +370,7 @@ begin -- behave
-- - we are not waiting for REARM command
-- - we have generated at least one valid TDC start pulse (so the TDC has some
-- meaningful reference
if(regs_i.gcr_input_en_o = '0' or tag_enable = '0' or start_ok = '0' or mask_stop = '1' or mask_stop_clamp = '1') then
if (regs_i.gcr_input_en_o = '0' or tag_enable = '0' or start_ok = '0' or safety_counter_mask = '1') then
acam_stop_dis_o <= '1';
else
acam_stop_dis_o <= '0';
......@@ -400,7 +393,7 @@ begin -- behave
start_ok_sreg <= (others => '0');
acam_start_dis_o <= '1';
else
-- Host control? just pass the whatever the host decides to the start
-- Host control? just pass whatever the host decides to the start
-- disable pin
if(regs_i.gcr_bypass_o = '1') then
acam_start_dis_o <= host_start_dis;
......@@ -408,11 +401,14 @@ begin -- behave
else
-- Enable the start input at proper moment to ensure that the 7.125 MHz
-- "start clock" cycle is not cut.
if(start_count = x"e") then
if(start_count = x"8") then
-- advance the start OK shift register with another one.
start_ok_sreg <= start_ok_sreg(start_ok_sreg'left-1 downto 0) & '1';
acam_start_dis_o <= '1';
elsif (start_count = x"18") then
acam_start_dis_o <= '0';
end if;
end if;
end if;
end if;
......@@ -447,6 +443,8 @@ begin -- behave
end if;
end process;
-- Process: p_sync_acam_ef
-- Input: acam_ef_i
-- Output: acam_ef_d1
......@@ -464,6 +462,17 @@ begin -- behave
-- Time Base Counters
-------------------------------------------------------------------------------
p_gen_start_mask : process(clk_ref_i)
begin
if rising_edge(clk_ref_i) then
if rst_n_i = '0' then
start_mask <= '0';
elsif(tdc_start_d(1) = '1' and tdc_start_d(2) = '0') then
start_mask <= not start_mask;
end if;
end if;
end process;
-- Start counter: counts the number of clk_ref_i cycles from the last TDC start
-- event.
......@@ -483,18 +492,18 @@ begin -- behave
-- between the current start count and the LSBs of the new time value
-- and correct the timestamps later on.
if(csync_p1_i = '1') then
subcycle_offset <= signed('0' & csync_coarse_i(3 downto 0)) - signed('0' & start_count) - 1;
subcycle_offset <= signed('0' & csync_coarse_i(4 downto 0)) - signed('0' & start_count) - 1;
end if;
-- Rising edge on TDC_START? Resynchronize the counter, to go to zero
-- right after the edge.
if(tdc_start_d(1) = '1' and tdc_start_d(2) = '0') then
start_count <= x"2";
if(tdc_start_d(1) = '1' and tdc_start_d(2) = '0' and start_mask = '0') then
start_count <= to_unsigned(2, 5);
advance_coarse <= '0';
else
-- Start cycle expired - advance the 128 ns x counter. We do that one
-- cycle in advance using a register to relax the P&R timing.
if(start_count = x"e") then
if(start_count = x"1e") then
advance_coarse <= '1';
else
advance_coarse <= '0';
......@@ -511,30 +520,25 @@ begin -- behave
begin
if rising_edge(clk_ref_i) then
if rst_n_i = '0' or regs_i.gcr_bypass_o = '1' then
coarse_count <= (others => '0');
coarse_count_shifted <= (others => '0');
coarse_count <= (others => '0');
else
-- External resync event: reload the counter with new time value. A
-- special case is executed when the resync event came at the same moment as the
-- overflow of start_count.
if(csync_p1_i = '1') then
if(advance_coarse = '1') then
coarse_count <= unsigned(csync_coarse_i(27 downto 4)) + 1;
coarse_count <= unsigned(csync_coarse_i(27 downto 5)) + 1;
else
coarse_count <= unsigned(csync_coarse_i(27 downto 4));
coarse_count <= unsigned(csync_coarse_i(27 downto 5));
end if;
elsif(advance_coarse = '1') then
-- well, just boringly count up
if(coarse_count = (g_clk_ref_freq / 16) - 1) then
if(coarse_count = (g_clk_ref_freq / 32) - 1) then
coarse_count <= (others => '0');
else
coarse_count <= coarse_count + 1;
end if;
-- keep a "shifted" copy updated in the middle of TDC start cycle
if(start_count = x"8") then
coarse_count_shifted <= coarse_count;
end if;
end if;
end if;
......@@ -546,24 +550,20 @@ begin -- behave
begin
if rising_edge(clk_ref_i) then
if(rst_n_i = '0') then
utc_count <= (others => '0');
utc_count_shifted <= (others => '0');
utc_count <= (others => '0');
else
if(csync_p1_i = '1') then
if(advance_coarse = '1' and coarse_count = (g_clk_ref_freq / 16) -1) then
if(advance_coarse = '1' and coarse_count = (g_clk_ref_freq / 32) -1) then
-- I hate special cases!
utc_count <= unsigned(csync_utc_i) + 1;
else
utc_count <= unsigned(csync_utc_i);
end if;
elsif(advance_coarse = '1' and coarse_count = (g_clk_ref_freq / 16) - 1) then
elsif(advance_coarse = '1' and coarse_count = (g_clk_ref_freq / 32) - 1) then
utc_count <= utc_count + 1;
end if;
if(start_count = x"8") then
utc_count_shifted <= utc_count;
end if;
end if;
end if;
end process;
......@@ -611,9 +611,11 @@ begin -- behave
gcr_input_en_d0 <= '0';
mask_stop <= '0';
acam_restart <= '0';
else
if (safety_counter_mask = '0') then
acam_restart <= '0';
end if;
gcr_input_en_d0 <= regs_i.gcr_input_en_o;
......@@ -646,22 +648,18 @@ begin -- behave
if(start_ok = '1' and trig_pulse = '0' and tag_rearm_p1_i = '1' and gcr_input_en_d0 = '1') then
tag_enable <= '1';
mask_stop <= '0';
end if;
-- Got a trigger pulse?
if(trig_pulse = '1' and tag_enable = '1' and start_ok = '1') then
mask_stop <= '1';
-- start checking its width
afsm_state <= RMODE_MEASURE_WIDTH;
-- store the coarse timestamp
raw_tag_coarse <= coarse_count;
raw_tag_coarse_sh <= coarse_count_shifted;
raw_tag_start_offset <= start_count;
raw_tag_utc <= utc_count;
raw_tag_utc_sh <= utc_count_shifted;
timeout_counter <= (others => '0');
......@@ -731,14 +729,17 @@ begin -- behave
afsm_state <= RMODE_READ_PULSE2;
when RMODE_READ_PULSE2 =>
afsm_state <= RMODE_READ_PULSE3;
when RMODE_READ_PULSE3 =>
afsm_state <= RMODE_READ;
when RMODE_READ =>
-- store the fine tag
raw_tag_frac <= signed(acam_d_i(raw_tag_frac'left downto 0));
raw_tag_frac(21 downto 0) <= signed(acam_d_i(21 downto 0));
raw_tag_frac(22) <= '0';
acam_rd_n_o <= '1';
-- check if the FIFO has become empty after the readout. If it didn't, the TDC
-- must have tagged another rising edge on the trigger input, which
......@@ -750,38 +751,34 @@ begin -- behave
-- for 24 ns, there should be no risk of metastability.
if(acam_ef_i = '1') then
afsm_state <= IDLE;
raw_tag_valid <= '1';
tag_enable <= '0';
else
afsm_state <= RMODE_PURGE_FIFO;
tag_enable <= '0';
end if;
tag_enable <= '0';
afsm_state <= RMODE_PURGE_FIFO;
-- Purge FIFO state: read out all data remaining in the ACAM fifo after when a
-- glitchy pulse occured.
when RMODE_PURGE_FIFO =>
acam_rd_n_o <= '0';
raw_tag_valid <= '0';
acam_rd_n_o <= '1';
acam_reset_int <= '1';
afsm_state <= RMODE_PURGE_WAIT;
purge_count <= to_unsigned(0, purge_count'length);
-- RD_n width extension (SI)
when RMODE_PURGE_WAIT =>
afsm_state <= RMODE_PURGE_WAIT2;
acam_reset_int <= '0';
when RMODE_PURGE_WAIT2 =>
afsm_state <= RMODE_PURGE_CHECK_EMPTY;
purge_count <= purge_count + 1;
-- Check if the FIFO is empty, if not - remove the next word
when RMODE_PURGE_CHECK_EMPTY =>
acam_rd_n_o <= '1';
if(acam_ef_i = '0') then
afsm_state <= RMODE_PURGE_FIFO;
else
tag_enable <= '1';
afsm_state <= IDLE;
if(purge_count = c_ACAM_PURGE_TIMEOUT) then
afsm_state <= IDLE;
acam_restart <= '1';
end if;
-- Host ACAM access: W_states: writes, R_states: reads.
when W_DATA_ADDR =>
acam_d_o <= acam_wdata;
......@@ -856,9 +853,7 @@ begin -- behave
rst_n_i => rst_n_i,
raw_valid_i => raw_tag_valid,
raw_utc_i => std_logic_vector(raw_tag_utc),
raw_utc_shifted_i => std_logic_vector(raw_tag_utc_sh),
raw_coarse_i => std_logic_vector(raw_tag_coarse),
raw_coarse_shifted_i => std_logic_vector(raw_tag_coarse_sh),
raw_frac_i => std_logic_vector(raw_tag_frac),
raw_start_offset_i => std_logic_vector(raw_tag_start_offset),
acam_subcycle_offset_i => std_logic_vector(subcycle_offset),
......
hdl/rtl/fd_channel_wbgen2_pkg.vhd
View file @ 8f25c0df
......@@ -3,7 +3,7 @@
---------------------------------------------------------------------------------------
-- File : fd_channel_wbgen2_pkg.vhd
-- Author : auto-generated by wbgen2 from fd_channel_wishbone_slave.wb
-- Created : Mon Jun 4 13:42:20 2012
-- Created : Fri Feb 15 12:07:17 2013
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE fd_channel_wishbone_slave.wb
......
hdl/rtl/fd_channel_wishbone_slave.vhd
View file @ 8f25c0df
......@@ -3,7 +3,7 @@
---------------------------------------------------------------------------------------
-- File : fd_channel_wishbone_slave.vhd
-- Author : auto-generated by wbgen2 from fd_channel_wishbone_slave.wb
-- Created : Mon Jun 4 13:42:20 2012
-- Created : Fri Feb 15 12:07:17 2013
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE fd_channel_wishbone_slave.wb
......@@ -161,11 +161,11 @@ begin
end if;
rddata_reg(0) <= fd_channel_dcr_enable_int;
rddata_reg(1) <= fd_channel_dcr_mode_int;
rddata_reg(2) <= 'X';
rddata_reg(2) <= '0';
rddata_reg(3) <= fd_channel_dcr_pg_trig_sync1;
rddata_reg(4) <= 'X';
rddata_reg(4) <= '0';
rddata_reg(5) <= fd_channel_dcr_upd_done_sync1;
rddata_reg(6) <= 'X';
rddata_reg(6) <= '0';
rddata_reg(7) <= fd_channel_dcr_no_fine_int;
rddata_reg(8) <= fd_channel_dcr_force_hi_int;
rddata_reg(9) <= 'X';
......
hdl/rtl/fd_delay_line_arbiter.vhd
View file @ 8f25c0df
......@@ -6,7 +6,7 @@
-- Author : Tomasz Wlostowski
-- Company : CERN
-- Created : 2011-08-24
-- Last update: 2012-04-25
-- Last update: 2013-02-21
-- Platform : FPGA-generic
-- Standard : VHDL'93
-------------------------------------------------------------------------------
......@@ -70,7 +70,7 @@ entity fd_delay_line_arbiter is
end fd_delay_line_arbiter;
architecture behavioral of fd_delay_line_arbiter is
signal arb_sreg : std_logic_vector(4*3 - 1 downto 0);
signal arb_sreg : std_logic_vector(4*4 - 1 downto 0);
type t_dly_array is array (integer range <>) of std_logic_vector(9 downto 0);
......@@ -78,6 +78,7 @@ architecture behavioral of fd_delay_line_arbiter is
signal delay_vec : t_dly_array(0 to 3);
signal delay_len_reg : std_logic_vector(3 downto 0);
signal delay_val_reg : std_logic_vector(9 downto 0);
signal pending_reg : std_logic_vector(3 downto 0);
begin -- behavioral
......@@ -93,31 +94,33 @@ begin -- behavioral
if rst_n_i = '0' then
delay_len_reg <= (others => '1');
delay_val_reg <= (others => '0');
delay_len_o <= (others => '1');
delay_len_o <= (others => '1');
-- done_reg <= (others => '0');
done_o <= (others => '0');
arb_sreg <= std_logic_vector(to_unsigned(1, arb_sreg'length));
pending_reg <= (others => '0');
else
arb_sreg <= arb_sreg(arb_sreg'left-1 downto 0) & arb_sreg(arb_sreg'left);
for i in 0 to 3 loop
if(arb_sreg(3*i) = '1' and load_i(i) = '1') then
delay_val_reg <= delay_vec(i);
delay_len_reg(i) <= '0';
done_o(i) <= '1';
end if;
if(arb_sreg(3*i+1) = '1') then
delay_val_reg <= delay_vec(i);
done_o(i) <= '0';
end if;
if(arb_sreg(3*i+2) = '1') then
if(arb_sreg(4*i) = '1' and load_i(i) = '1') then
delay_val_reg <= delay_vec(i);
pending_reg(i) <= '1';
delay_len_reg(i) <= '1';
done_o(i) <= '0';
elsif(arb_sreg(4*i+1) = '1') then
delay_len_reg(i) <= not pending_reg(i);
done_o(i) <= '0';
elsif(arb_sreg(4*i+2) = '1') then
delay_len_reg(i) <= not pending_reg(i);
done_o(i) <= '0';
elsif(arb_sreg(4*i+3) = '1') then
delay_len_reg(i) <= '1';
done_o(i) <= pending_reg(i);
pending_reg(i) <= '0';
else
done_o(i) <= '0';
end if;
end loop; -- i in 0 to 3
......
hdl/rtl/fd_main_wbgen2_pkg.vhd
View file @ 8f25c0df
......@@ -3,7 +3,7 @@
---------------------------------------------------------------------------------------
-- File : fd_main_wbgen2_pkg.vhd
-- Author : auto-generated by wbgen2 from fd_main_wishbone_slave.wb
-- Created : Fri Dec 14 11:28:02 2012
-- Created : Fri Feb 15 12:07:16 2013
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE fd_main_wishbone_slave.wb
......@@ -130,7 +130,7 @@ package fd_main_wbgen2_pkg is
calr_cal_dmtd_o : std_logic;
calr_psel_o : std_logic_vector(3 downto 0);
adsfr_o : std_logic_vector(17 downto 0);
atmcr_c_thr_o : std_logic_vector(3 downto 0);
atmcr_c_thr_o : std_logic_vector(7 downto 0);
atmcr_f_thr_o : std_logic_vector(22 downto 0);
asor_offset_o : std_logic_vector(22 downto 0);
iepd_rst_stat_o : std_logic;
......
hdl/rtl/fd_main_wishbone_slave.vhd
View file @ 8f25c0df
......@@ -3,7 +3,7 @@
---------------------------------------------------------------------------------------
-- File : fd_main_wishbone_slave.vhd
-- Author : auto-generated by wbgen2 from fd_main_wishbone_slave.wb
-- Created : Fri Dec 14 11:28:02 2012
-- Created : Fri Feb 15 12:07:16 2013
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE fd_main_wishbone_slave.wb
......@@ -159,7 +159,7 @@ signal fd_main_adsfr_swb_delay : std_logic ;
signal fd_main_adsfr_swb_s0 : std_logic ;
signal fd_main_adsfr_swb_s1 : std_logic ;
signal fd_main_adsfr_swb_s2 : std_logic ;
signal fd_main_atmcr_c_thr_int : std_logic_vector(3 downto 0);
signal fd_main_atmcr_c_thr_int : std_logic_vector(7 downto 0);
signal fd_main_atmcr_c_thr_swb : std_logic ;
signal fd_main_atmcr_c_thr_swb_delay : std_logic ;
signal fd_main_atmcr_c_thr_swb_s0 : std_logic ;
......@@ -332,7 +332,7 @@ begin
fd_main_adsfr_int <= "000000000000000000";
fd_main_adsfr_swb <= '0';
fd_main_adsfr_swb_delay <= '0';
fd_main_atmcr_c_thr_int <= "0000";
fd_main_atmcr_c_thr_int <= "00000000";
fd_main_atmcr_c_thr_swb <= '0';
fd_main_atmcr_c_thr_swb_delay <= '0';
fd_main_atmcr_f_thr_int <= "00000000000000000000000";
......@@ -373,8 +373,8 @@ begin
fd_main_tsbir_timeout_int <= "0000000000";
fd_main_tsbir_threshold_int <= "000000000000";
fid_read_ack_o <= '0';
fd_main_i2cr_scl_out_int <= '0';
fd_main_i2cr_sda_out_int <= '0';
fd_main_i2cr_scl_out_int <= '1';
fd_main_i2cr_sda_out_int <= '1';
fd_main_tder2_pelt_drive_int <= "00000000000000000000000000000000";
fd_main_tsbr_advance_adv_int <= '0';
eic_idr_write_int <= '0';
......@@ -595,8 +595,8 @@ begin
rddata_reg(3) <= regs_i.tcr_wr_present_i;
rddata_reg(4) <= regs_i.tcr_wr_ready_i;
rddata_reg(5) <= regs_i.tcr_wr_link_i;
rddata_reg(6) <= 'X';
rddata_reg(7) <= 'X';
rddata_reg(6) <= '0';
rddata_reg(7) <= '0';
rddata_reg(8) <= 'X';
rddata_reg(9) <= 'X';
rddata_reg(10) <= 'X';
......@@ -736,14 +736,14 @@ begin
fd_main_tdcsr_alutrig_int <= wrdata_reg(7);
fd_main_tdcsr_alutrig_int_delay <= wrdata_reg(7);
end if;
rddata_reg(0) <= 'X';
rddata_reg(1) <= 'X';
rddata_reg(0) <= '0';
rddata_reg(1) <= '0';
rddata_reg(2) <= fd_main_tdcsr_empty_sync1;
rddata_reg(3) <= 'X';
rddata_reg(4) <= 'X';
rddata_reg(5) <= 'X';
rddata_reg(6) <= 'X';
rddata_reg(7) <= 'X';
rddata_reg(3) <= '0';
rddata_reg(4) <= '0';
rddata_reg(5) <= '0';
rddata_reg(6) <= '0';
rddata_reg(7) <= '0';
rddata_reg(8) <= 'X';
rddata_reg(9) <= 'X';
rddata_reg(10) <= 'X';
......@@ -780,7 +780,7 @@ begin
fd_main_calr_psel_swb <= '1';
fd_main_calr_psel_swb_delay <= '1';
end if;
rddata_reg(0) <= 'X';
rddata_reg(0) <= '0';
rddata_reg(1) <= fd_main_calr_cal_pps_int;
rddata_reg(2) <= fd_main_calr_cal_dmtd_int;
rddata_reg(6 downto 3) <= fd_main_calr_psel_int;
......@@ -852,19 +852,15 @@ begin
ack_in_progress <= '1';
when "001101" =>
if (wb_we_i = '1') then
fd_main_atmcr_c_thr_int <= wrdata_reg(3 downto 0);
fd_main_atmcr_c_thr_int <= wrdata_reg(7 downto 0);
fd_main_atmcr_c_thr_swb <= '1';
fd_main_atmcr_c_thr_swb_delay <= '1';
fd_main_atmcr_f_thr_int <= wrdata_reg(26 downto 4);
fd_main_atmcr_f_thr_int <= wrdata_reg(30 downto 8);
fd_main_atmcr_f_thr_swb <= '1';
fd_main_atmcr_f_thr_swb_delay <= '1';
end if;
rddata_reg(3 downto 0) <= fd_main_atmcr_c_thr_int;
rddata_reg(26 downto 4) <= fd_main_atmcr_f_thr_int;
rddata_reg(27) <= 'X';
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(7 downto 0) <= fd_main_atmcr_c_thr_int;
rddata_reg(30 downto 8) <= fd_main_atmcr_f_thr_int;
rddata_reg(31) <= 'X';
ack_sreg(3) <= '1';
ack_in_progress <= '1';
......@@ -911,7 +907,7 @@ begin
fd_main_iepd_rst_stat_int <= wrdata_reg(0);
fd_main_iepd_rst_stat_int_delay <= wrdata_reg(0);
end if;
rddata_reg(0) <= 'X';
rddata_reg(0) <= '0';
if (wb_we_i = '0') then
fd_main_iepd_pdelay_lwb <= '1';
fd_main_iepd_pdelay_lwb_delay <= '1';
......@@ -957,7 +953,7 @@ begin
rddata_reg(26) <= fd_main_scr_sel_gpio_int;
rddata_reg(27) <= regs_i.scr_ready_i;
rddata_reg(28) <= fd_main_scr_cpol_int;
rddata_reg(29) <= 'X';
rddata_reg(29) <= '0';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
ack_sreg(2) <= '1';
......@@ -985,8 +981,8 @@ begin
end if;
rddata_reg(4 downto 0) <= fd_main_tsbcr_chan_mask_int;
rddata_reg(5) <= fd_main_tsbcr_enable_int;
rddata_reg(6) <= 'X';
rddata_reg(7) <= 'X';
rddata_reg(6) <= '0';
rddata_reg(7) <= '0';
rddata_reg(8) <= regs_i.tsbcr_full_i;
rddata_reg(9) <= regs_i.tsbcr_empty_i;
tsbcr_read_ack_o <= '1';
......@@ -1139,7 +1135,7 @@ begin
if (wb_we_i = '1') then
fd_main_tsbr_advance_adv_int <= wrdata_reg(0);
end if;
rddata_reg(0) <= 'X';
rddata_reg(0) <= '0';
rddata_reg(0) <= 'X';
rddata_reg(1) <= 'X';
rddata_reg(2) <= 'X';
......@@ -1376,7 +1372,7 @@ begin
-- PLL Locked
-- Mezzanice Present
-- Mezzanine Present
-- DMTD Clock Status
-- WR Timing Enable
regs_o.tcr_wr_enable_o <= fd_main_tcr_wr_enable_int;
......@@ -1478,8 +1474,8 @@ begin
end process;
-- Reference clock cycles
-- asynchronous std_logic_vector register : Reference clock cycles (type RW/WO, clk_ref_i <-> clk_sys_i)
-- Reference clock cycles (0...124999999)
-- asynchronous std_logic_vector register : Reference clock cycles (0...124999999) (type RW/WO, clk_ref_i <-> clk_sys_i)
process (clk_ref_i, rst_n_i)
begin
if (rst_n_i = '0') then
......@@ -1538,7 +1534,7 @@ begin
end process;
-- Start TDC write
-- Write to TDC
process (clk_ref_i, rst_n_i)
begin
if (rst_n_i = '0') then
......@@ -1555,7 +1551,7 @@ begin
end process;
-- Start TDC read
-- Read from TDC
process (clk_ref_i, rst_n_i)
begin
if (rst_n_i = '0') then
......@@ -1586,7 +1582,7 @@ begin
end process;
-- Start enable
-- Stop enable
process (clk_ref_i, rst_n_i)
begin
if (rst_n_i = '0') then
......@@ -1620,7 +1616,7 @@ begin
end process;
-- Stop enable
-- Start enable
process (clk_ref_i, rst_n_i)
begin
if (rst_n_i = '0') then
......@@ -1654,7 +1650,7 @@ begin
end process;
-- write 1: Pulse the Alutrigger line
-- Pulse <code>Alutrigger</code> line
process (clk_ref_i, rst_n_i)
begin
if (rst_n_i = '0') then
......@@ -1671,7 +1667,7 @@ begin
end process;
-- Triggers calibration pulses
-- Generate calibration pulses (type 1 calibration)
process (clk_ref_i, rst_n_i)
begin
if (rst_n_i = '0') then
......@@ -1704,10 +1700,10 @@ begin
end process;
-- Produce DDMTD calibration pattern
-- Produce DDMTD calibration pattern (type 2 calibration)
regs_o.calr_cal_dmtd_o <= fd_main_calr_cal_dmtd_int;
-- Enable pulse generation
-- asynchronous std_logic_vector register : Enable pulse generation (type RW/RO, clk_ref_i <-> clk_sys_i)
-- Calibration pulse output select/mask
-- asynchronous std_logic_vector register : Calibration pulse output select/mask (type RW/RO, clk_ref_i <-> clk_sys_i)
process (clk_ref_i, rst_n_i)
begin
if (rst_n_i = '0') then
......@@ -1758,7 +1754,7 @@ begin
fd_main_atmcr_c_thr_swb_s0 <= '0';
fd_main_atmcr_c_thr_swb_s1 <= '0';
fd_main_atmcr_c_thr_swb_s2 <= '0';
regs_o.atmcr_c_thr_o <= "0000";
regs_o.atmcr_c_thr_o <= "00000000";
elsif rising_edge(clk_ref_i) then
fd_main_atmcr_c_thr_swb_s0 <= fd_main_atmcr_c_thr_swb;
fd_main_atmcr_c_thr_swb_s1 <= fd_main_atmcr_c_thr_swb_s0;
......
hdl/rtl/fd_main_wishbone_slave.wb
View file @ 8f25c0df
......@@ -70,7 +70,7 @@ peripheral {
field {
name = "Reset magic value";
description = "Protection field - the state of RST_FMC/RST_CORE lines will\
only be updated if LOCK is written with 0xdead";
only be updated if LOCK is written with 0xdead together with the new state of the reset lines.";
type = PASS_THROUGH;
prefix = "LOCK";
align = 16;
......@@ -80,7 +80,7 @@ peripheral {
reg {
name = "ID Register";
description = "Magic identification value (for detecting FD cores by the driver)";
description = "Magic identification value (for detecting FD cores by the driver). Now the enumeration is handled through SDB, but the register is kept for compatibility with older software.";
prefix = "IDR";
field {
......@@ -104,7 +104,7 @@ peripheral {
prefix = "BYPASS";
description = "Descides who is in charge of the TDC and delay lines:\
write 0: TDC and delay lines are controlled by the HDL core (normal operation)\
write 1: TDC and delay lines controlled from the host (calibration)";
write 1: TDC and delay lines controlled from the host (calibration and testing)";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
......@@ -115,7 +115,8 @@ peripheral {
name = "Enable trigger input";
description = "write 1: trigger input is enabled\
write 0: trigger input is disabled";
write 0: trigger input is disabled.\
Note: state of INPUT_EN is relevant only in normal operation mode (i.e. when GCR.BYPASS == 0).";
prefix = "INPUT_EN";
type = BIT;
access_bus = READ_WRITE;
......@@ -134,7 +135,7 @@ peripheral {
};
field {
name = "Mezzanice Present";
name = "Mezzanine Present";
description = "read 1: FMC card is present (PRSNT_L == 0)\
read 0: no FMC card in the slot (PRSNT_L == 1)";
prefix = "FMC_PRESENT";
......@@ -146,7 +147,7 @@ peripheral {
reg {
name = "Timing Control Register";
description = "Controls timing stuff (and White Rabbit referencing)";
description = "Controls time setting and White Rabbit/local time base selection.";
prefix = "TCR";
......@@ -159,7 +160,7 @@ peripheral {
prefix = "DMTD_STAT";
description = "Status of the DMTD (helper) clock, used for calibration purposes.\
read 0: DMTD clock is not available or has been lost since last read operation of WR_TCR register\
read 1: DMTD clock is OK and has been like this since the previous read of WR_TCR register";
read 1: DMTD clock is OK and has been like this since previous read of WR_TCR register";
type = BIT;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
......@@ -170,7 +171,9 @@ peripheral {
prefix = "WR_ENABLE";
description = "Enables/disables WR synchronization.\
write 1: WR synchronization is enabled. Poll the WR_LOCKED bit to check if the WR Core is still locked.\
write 0: WR synchronization is disabled, the card is in free running mode.";
write 0: WR synchronization is disabled, the card is in free running mode.\
Note: enabling WR synchronization will cause a jump in the time base counter of the core. This may lead to lost pulses, therefore it is strongly\
recommended do disable the trigger input before entering WR mode. When WR mode is disabled, the core will continue with the last known WR time, counted with the local oscillator (no jump).";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
......@@ -193,7 +196,7 @@ peripheral {
prefix = "WR_PRESENT";
description = "Indicates whether we have a WR Core associated with this Fine Delay Core. Reflects the state\
of 'g_with_wr_core' generic HDL parameter. \
read 0: No WR Core present.\
read 0: No WR Core present. Enabling WR will have no effect.\
read 1: WR Core available.";
type = BIT;
access_bus = READ_ONLY;
......@@ -203,8 +206,8 @@ peripheral {
field {
name = "WR Core Time Ready";
prefix = "WR_READY";
description = "read 0: WR Core time syncing in progress (or no link).\
read 1: WR Core time ready.";
description = "read 0: WR Core is not synchronied yet: there is no link, no PTP master in the network or synchronization is in progress.\
read 1: WR Core time is ready. User may enable WR reference by setting TCR.WR_ENABLE bit.";
type = BIT;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
......@@ -213,8 +216,8 @@ peripheral {
field {
name = "WR Core Link Up";
prefix = "WR_LINK";
description = "read 0: Link is down.\
read 1: Link is up.";
description = "read 0: Ethernet link is down.\
read 1: Ethernet link is up.";
type = BIT;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
......@@ -223,9 +226,9 @@ peripheral {
field {
name = "Capture Current Time";
prefix = "CAP_TIME";
description = "Controls the readout of TM_x registers.\
write 1: transfers the current value of UTC/Nsec counters to TM_x registers.\
write 0: no effect";
description = "Controls the readout of <code>TM_xxx</code> registers.\
write 1: transfers the current value of seconds/cycles counters to <code>TM_xxx</code> registers.\
write 0: no effect.";
type = MONOSTABLE;
clock = "clk_ref_i";
};
......@@ -233,10 +236,10 @@ peripheral {
field {
name = "Set Current Time";
prefix = "SET_TIME";
description = "Controls the write of TM_x registers to the internal time counter.\
write 1: transfers the current value of TM_x to the timebase counters.\
description = "Controls transfer of <code>TM_x</code> registers to the internal time counter.\
write 1: transfers the current value of <code>TM_x</code> to the timebase counters.\
write 0: no effect.\
<b>WARNING</b> Setting time also resynchronizes internal timebase counters, therefore \
<b>Note:</b> Setting time also resynchronizes internal timebase counters, therefore \
time registers must be set after every reset/power cycle. ";
type = MONOSTABLE;
clock = "clk_ref_i";
......@@ -247,8 +250,8 @@ peripheral {
reg {
name = "Time Register - TAI seconds (MSB)";
prefix = "TM_SECH";
description = "read: value of internal seconds counter taken during write to TCR.CAP_TIME bit.\
write: new value of time (acked by writing TCR.SET_TIME bit)";
description = "read: value of internal seconds counter taken during write to <code>TCR.CAP_TIME</code> bit.\
write: new value of time (acked by writing <code>TCR.SET_TIME</code> bit)";
field {
name = "TAI seconds (MSB)";
size = 8;
......@@ -263,8 +266,8 @@ peripheral {
reg {
name = "Time Register - TAI seconds (LSB)";
prefix = "TM_SECL";
description = "read: value of internal seconds counter taken during write to TCR.CAP_TIME bit.\
write: new value of time (acked by writing TCR.SET_TIME bit)";
description = "read: value of internal seconds counter taken during write to <code>TCR.CAP_TIME</code> bit.\
write: new value of time (acked by writing <code>TCR.SET_TIME</code> bit)";
field {
name = "TAI seconds (LSB)";
size = 32;
......@@ -279,10 +282,10 @@ peripheral {
reg {
name = "Time Register - sub-second 125 MHz clock cycles ";
prefix = "TM_CYCLES";
description = "read: value of internal 125 MHz cycles counter taken during write to TCR.CAP_TIME bit.\
write: new value of time (acked by writing TCR.SET_TIME bit)";
description = "read: value of internal 125 MHz cycles counter taken during write to <code>TCR.CAP_TIME</code> bit.\
write: new value of time (acked by writing <code>TCR.SET_TIME</code> bit)";
field {
name = "Reference clock cycles";
name = "Reference clock cycles (0...124999999)";
size = 28;
type = SLV;
access_bus = READ_WRITE;
......@@ -293,7 +296,8 @@ peripheral {
};
reg {
name = "TDC Data Register";
name = "Host-driven TDC Data Register";
description = "28-bit data value read from / to be written to the ACAM. Used when bypass (host-driven) mode is active.";
prefix = "TDR";
field {
......@@ -309,18 +313,23 @@ peripheral {
reg {
name = "TDC control/status reg";
name = "Host-driven TDC Control/Status";
description = "Allows controlling the TDC directly from the host (when <code>GCR.BYPASS == 1</code>).";
prefix = "TDCSR";
field {
name = "Start TDC write";
name = "Write to TDC";
description = "write 1: write the data word programmed in <code>TDR</code> TDR register to the TDC. The TDC address must be set via the SPI I/O expander.\
write 0: no effect.";
prefix = "WRITE";
clock = "clk_ref_i";
type = MONOSTABLE;
};
field {
name = "Start TDC read";
name = "Read from TDC";
description = "write 1: read a data word from the TDC. The read word will be put in the <code>TDR</code> register. The TDC address must be set via the SPI I/O expander.\
write 0: no effect.";
prefix = "READ";
clock = "clk_ref_i";
type = MONOSTABLE;
......@@ -329,6 +338,7 @@ peripheral {
field {
clock = "clk_ref_i";
name = "Empty flag";
description = "Raw status of the EMPTY pin of the TDC. When zero, the internal TDC FIFO is empty (no timestamps to read)";
prefix = "EMPTY";
type = BIT;
access_bus = READ_ONLY;
......@@ -337,13 +347,19 @@ peripheral {
field {
clock = "clk_ref_i";
name = "Start enable";
name = "Stop enable";
description = "Controls the <code>StopDis</code> input of the TDC.\
write 1: disables the TDC stop input.\
write 0: no effect.";
prefix = "STOP_EN";
type = MONOSTABLE;
};
field {
clock = "clk_ref_i";
description = "Controls the <code>StartDis</code> input of the TDC.\
write 1: disables the TDC start input.\
write 0: no effect.";
name = "Start disable";
prefix = "START_DIS";
type = MONOSTABLE;
......@@ -351,7 +367,10 @@ peripheral {
field {
clock = "clk_ref_i";
name = "Stop enable";
description = "Controls the <code>StartDis</code> input of the TDC.\
write 1: enables the TDC start input.\
write 0: no effect.";
name = "Start enable";
prefix = "START_EN";
type = MONOSTABLE;
};
......@@ -359,13 +378,19 @@ peripheral {
field {
clock = "clk_ref_i";
name = "Stop disable";
description = "Controls the <code>StopDis</code> input of the TDC.\
write 1: enables the TDC stop input.\
write 0: no effect.";
prefix = "STOP_DIS";
type = MONOSTABLE;
};
field {
clock = "clk_ref_i";
name = "write 1: Pulse the Alutrigger line";
name = "Pulse <code>Alutrigger</code> line";
description = "Controls the TDC's <code>Alutrigger</code> line.\ Depending on the TDC's configuration, it can be used as a reset/FIFO clear/trigger signal.\
write 1: generates a pulse the <code>Alutrigger</code> line\
write 0: no effect.";
prefix = "ALUTRIG";
type = MONOSTABLE;
};
......@@ -374,11 +399,12 @@ peripheral {
reg {
prefix = "CALR";
name = "Calibration register";
description = "Controls calibration-related activities";
field {
clock = "clk_ref_i";
name = "Triggers calibration pulses";
description = "write 1: Generates synchronous calibration pulse on the channels selected in the PSEL field.\
name = "Generate calibration pulses (type 1 calibration)";
description = "write 1: Generates a single calibration pulse on the TDC start input and the channels selected in the PSEL field.\
write 0: no effect.";
prefix = "CAL_PULSE";
type = MONOSTABLE;
......@@ -396,10 +422,9 @@ peripheral {
};
field {
-- clock = "clk_ref_i";
name = "Produce DDMTD calibration pattern";
name = "Produce DDMTD calibration pattern (type 2 calibration)";
description = "write 1: Enables DMTD test pattern generation on Delay chain input and output selected in PSEL.\
write 0: DMTD pattern generation disabled.";
write 0: DMTD pattern generation disabled.";
prefix = "CAL_DMTD";
type = BIT;
access_dev = READ_ONLY;
......@@ -408,7 +433,7 @@ write 0: DMTD pattern generation disabled.";
field {
clock = "clk_ref_i";
name = "Enable pulse generation";
name = "Calibration pulse output select/mask";
description = "1: enable generation of calibration pulses on the output corresponding to the written bit\
0: disable generation on the corresponding output";
prefix = "PSEL";
......@@ -470,7 +495,7 @@ write 0: DMTD pattern generation disabled.";
reg {
prefix = "ADSFR";
name = "Acam to Delay line fractional part Scale Factor Register";
description = "Coefficient used to re-scale the fine part of the timestamp produced by Acam. Contains the number of Delay line bins per one Acam bin. Can be used to compensate the INL error and jitter of the delay lines induced by temperature changes. It's value can be calculated with the following formula: <b>ADFSR = (2 ** 14) * Acam_bin [ps] / Delay_bin [ps]</b>";
description = "Coefficient used to re-scale the fine part of the timestamp produced by Acam. Contains the number of Delay line bins per one Acam bin. Its value can be calculated with the following formula: <code>ADFSR = 2097.2 * ACAM bin size [ps]</code>";
field {
name = "ADFSR Value";
......@@ -490,7 +515,7 @@ write 0: DMTD pattern generation disabled.";
field {
name = "Wraparound Coarse Threshold";
prefix = "C_THR";
size = 4;
size = 8;
type = SLV;
clock = "clk_ref_i";
access_bus = READ_WRITE;
......
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment