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FMC DEL 1ns 4cha
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FMC DEL 1ns 4cha
Commits
883c423a
Commit
883c423a
authored
Mar 24, 2014
by
Tomasz Wlostowski
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hdl/testbench/svec_wr_top: verify the new arbiter
parent
7dea47db
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3 changed files
with
29 additions
and
20 deletions
+29
-20
mc100ep195.vh
hdl/include/mc100ep195.vh
+14
-4
Manifest.py
hdl/testbench/svec_wr_top/Manifest.py
+1
-1
main.sv
hdl/testbench/svec_wr_top/main.sv
+14
-15
No files found.
hdl/include/mc100ep195.vh
View file @
883c423a
...
...
@@ -12,10 +12,22 @@ module mc100ep195
const int c_min_delay = 2ns;
const int c_time_per_tap = 10ps;
reg [9:0] cur_dly = 0;
int cur_dly;
reg o_reg = 0;
assign o = o_reg;
bit dly[0:2000];
int ptr = 0;
always #(c_time_per_tap)
begin
dly[ptr++] = i;
if(ptr == 1024)
ptr = 0;
end
assign o = dly[ptr - 1 - cur_dly < 0 ? ptr -1 -cur_dly + 1024: ptr-1-cur_dly];
always@(posedge len)
...
...
@@ -25,7 +37,5 @@ module mc100ep195
always@(i)
o_reg <= #(c_min_delay + cur_dly * c_time_per_tap) i;
endmodule // mc100ep195
hdl/testbench/svec_wr_top/Manifest.py
View file @
883c423a
...
...
@@ -5,5 +5,5 @@ vlog_opt="+incdir+../../include/wb +incdir+../../include/vme64x_bfm +incdir+../.
files
=
[
"main.sv"
]
modules
=
{
"local"
:
[
"../../top/svec
/wr
"
]
}
modules
=
{
"local"
:
[
"../../top/svec"
]
}
hdl/testbench/svec_wr_top/main.sv
View file @
883c423a
...
...
@@ -59,7 +59,10 @@ module period_meas(input enable, input a);
always
@
(
posedge
a
)
begin
if
(
prev_a
>
0
)
begin
if
(
enable
)
tag_a
.
put
($
time
-
prev_a
)
;
end
else
end
if
(
!
enable
)
prev_a
=
0
;
else
prev_a
=
$
time
;
end
...
...
@@ -75,7 +78,7 @@ module period_meas(input enable, input a);
tag_a
.
get
(
delta
)
;
$
display
(
"
Delay
: %.3f ns"
,
real
'
(
delta
)
/
real
'
(
1
ns
)
)
;
$
display
(
"
Period
: %.3f ns"
,
real
'
(
delta
)
/
real
'
(
1
ns
)
)
;
end
end
endmodule
// delay_meas
...
...
@@ -144,8 +147,10 @@ module main;
always
@
(
out0
[
0
])
out0_delayed
<=
#
10
ps
out0
[
0
]
;
period_meas
U_DMeas0
(
pulse_enable
,
out0
[
0
])
;
period_meas
U_DMeas1
(
pulse_enable
,
out0
[
1
])
;
period_meas
U_DMeas2
(
pulse_enable
,
out0
[
2
])
;
period_meas
U_DMeas3
(
pulse_enable
,
out0
[
3
])
;
task
automatic
init_vme64x_core
(
ref
CBusAccessor_VME64x
acc
)
;
/* map func0 to 0x80000000, A32 */
...
...
@@ -168,19 +173,10 @@ module main;
#
20u
s
;
init_vme64x_core
(
acc
)
;
acc_casted
.
set_default_xfer_size
(
A32
|
SINGLE
|
D32
)
;
// acc.read('h20000, d, D32|A32|SINGLE);
// $display("Vector 1 = %x", d);
acc
.
read
(
'h80030080
,
d
,
D32
|
A32
|
SINGLE
)
;
$
display
(
"Vector 0 = %x"
,
d
)
;
acc
.
read
(
'h80030084
,
d
,
D32
|
A32
|
SINGLE
)
;
$
display
(
"Vector 1 = %x"
,
d
)
;
acc
.
read
(
'h80030088
,
d
,
D32
|
A32
|
SINGLE
)
;
$
display
(
"Vector 2 = %x"
,
d
)
;
$
stop
;
drv0
=
new
(
acc
,
'h80010000
)
;
...
...
@@ -188,9 +184,12 @@ module main;
t_start
=
new
;
drv0
.
get_time
(
t_start
)
;
t_start
.
coarse
+=
2000
;
t_start
.
coarse
+=
2000
0
;
drv0
.
config_output
(
0
,
CSimDrv_FineDelay
::
PULSE_GEN
,
1
,
t_start
,
200000
,
1001000
,
-
1
)
;
drv0
.
config_output
(
1
,
CSimDrv_FineDelay
::
PULSE_GEN
,
1
,
t_start
,
200000
,
1001100
,
-
1
)
;
drv0
.
config_output
(
2
,
CSimDrv_FineDelay
::
PULSE_GEN
,
1
,
t_start
,
200000
,
1001200
,
-
1
)
;
drv0
.
config_output
(
3
,
CSimDrv_FineDelay
::
PULSE_GEN
,
1
,
t_start
,
200000
,
1001300
,
-
1
)
;
$
display
(
"Init done"
)
;
...
...
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