Commit 828b9fab authored by Tomasz Wlostowski's avatar Tomasz Wlostowski

V4 PCB design uploaded (minor fixes wrs the V3)

parent 8c745caf
[DesignatorManager]
LogicalDesignator0=FTG5
LogicalPartID0=1
DocumentName0=EDA-02267-V2-0_sch.SchDoc
ChannelName0=EDA-02267-V2-0_sch
UniqueID0=\CHQUXTEM
PhysicalDesignator0=FTG5
PhysicalDesignatorLocked0=0
LogicalDesignator1=FTG4
LogicalPartID1=1
DocumentName1=EDA-02267-V2-0_sch.SchDoc
ChannelName1=EDA-02267-V2-0_sch
UniqueID1=\CXGAQQLP
PhysicalDesignator1=FTG4
PhysicalDesignatorLocked1=0
LogicalDesignator2=FTG3
LogicalPartID2=1
DocumentName2=EDA-02267-V2-0_sch.SchDoc
ChannelName2=EDA-02267-V2-0_sch
UniqueID2=\DCGXKANM
PhysicalDesignator2=FTG3
PhysicalDesignatorLocked2=0
LogicalDesignator3=FTG1
LogicalPartID3=1
DocumentName3=EDA-02267-V2-0_sch.SchDoc
ChannelName3=EDA-02267-V2-0_sch
UniqueID3=\HBGRHMCN
PhysicalDesignator3=FTG1
PhysicalDesignatorLocked3=0
LogicalDesignator4=C2
LogicalPartID4=1
DocumentName4=EDA-02267-V2-0_sch.SchDoc
ChannelName4=EDA-02267-V2-0_sch
UniqueID4=\HNUAEDNO
PhysicalDesignator4=C2
PhysicalDesignatorLocked4=0
LogicalDesignator5=J1
LogicalPartID5=2
DocumentName5=EDA-02267-V2-0_sch.SchDoc
ChannelName5=EDA-02267-V2-0_sch
UniqueID5=\JXJNUPIT
PhysicalDesignator5=J1
PhysicalDesignatorLocked5=0
LogicalDesignator6=FTG2
LogicalPartID6=1
DocumentName6=EDA-02267-V2-0_sch.SchDoc
ChannelName6=EDA-02267-V2-0_sch
UniqueID6=\KTVISOBD
PhysicalDesignator6=FTG2
PhysicalDesignatorLocked6=0
LogicalDesignator7=R1
LogicalPartID7=1
DocumentName7=EDA-02267-V2-0_sch.SchDoc
ChannelName7=EDA-02267-V2-0_sch
UniqueID7=\LHHDYBYT
PhysicalDesignator7=R1
PhysicalDesignatorLocked7=0
LogicalDesignator8=R2
LogicalPartID8=1
DocumentName8=EDA-02267-V2-0_sch.SchDoc
ChannelName8=EDA-02267-V2-0_sch
UniqueID8=\MQEYJIRX
PhysicalDesignator8=R2
PhysicalDesignatorLocked8=0
LogicalDesignator9=IC1
LogicalPartID9=1
DocumentName9=EDA-02267-V2-0_sch.SchDoc
ChannelName9=EDA-02267-V2-0_sch
UniqueID9=\MSPBGNXQ
PhysicalDesignator9=IC1
PhysicalDesignatorLocked9=0
LogicalDesignator10=FTG6
LogicalPartID10=1
DocumentName10=EDA-02267-V2-0_sch.SchDoc
ChannelName10=EDA-02267-V2-0_sch
UniqueID10=\PMRLWWGI
PhysicalDesignator10=FTG6
PhysicalDesignatorLocked10=0
LogicalDesignator11=J1
LogicalPartID11=1
DocumentName11=EDA-02267-V2-0_sch.SchDoc
ChannelName11=EDA-02267-V2-0_sch
UniqueID11=\QUYUHKUL
PhysicalDesignator11=J1
PhysicalDesignatorLocked11=0
LogicalDesignator12=C1
LogicalPartID12=1
DocumentName12=EDA-02267-V2-0_sch.SchDoc
ChannelName12=EDA-02267-V2-0_sch
UniqueID12=\TITEXCPY
PhysicalDesignator12=C1
PhysicalDesignatorLocked12=0
LogicalDesignator13=C3
LogicalPartID13=1
DocumentName13=EDA-02267-V2-0_sch.SchDoc
ChannelName13=EDA-02267-V2-0_sch
UniqueID13=\VAMIHRDF
PhysicalDesignator13=C3
PhysicalDesignatorLocked13=0
LogicalDesignator14=B1
LogicalPartID14=1
DocumentName14=EDA-02267-V2-0_sch.SchDoc
ChannelName14=EDA-02267-V2-0_sch
UniqueID14=\VBAGOSTE
PhysicalDesignator14=B1
PhysicalDesignatorLocked14=0
LogicalDesignator15=B3
LogicalPartID15=1
DocumentName15=EDA-02267-V2-0_sch.SchDoc
ChannelName15=EDA-02267-V2-0_sch
UniqueID15=\VBFXUCBF
PhysicalDesignator15=B3
PhysicalDesignatorLocked15=0
LogicalDesignator16=J1
LogicalPartID16=3
DocumentName16=EDA-02267-V2-0_sch.SchDoc
ChannelName16=EDA-02267-V2-0_sch
UniqueID16=\WFGPEOJO
PhysicalDesignator16=J1
PhysicalDesignatorLocked16=0
LogicalDesignator17=B2
LogicalPartID17=1
DocumentName17=EDA-02267-V2-0_sch.SchDoc
ChannelName17=EDA-02267-V2-0_sch
UniqueID17=\WMGSPSSA
PhysicalDesignator17=B2
PhysicalDesignatorLocked17=0
[SheetNumberManager]
SheetNumberOrder=Display Order
SheetNumberMethod=Increasing
"Line","SPEC 1.1 FPGA","FMC Connector","Fine delay v2","I/O Standard"
"CLK1_M2C_N","L22","g3","fd_clk_ref_n_i","LVDS_25"
"CLK1_M2C_P","L20","g2","fd_clk_ref_p_i","LVDS_25"
"LA24_P","W14","h28","fd_delay_len_o[0]","LVCMOS25"
"LA24_N","Y14","h29","fd_delay_len_o[1]","LVCMOS25"
"LA29_N","Y18","g31","fd_delay_len_o[2]","LVCMOS25"
"LA29_P","W17","g30","fd_delay_len_o[3]","LVCMOS25"
"LA21_N","W13","h26","fd_delay_pulse_o[0]","LVCMOS25"
"LA21_P","V13","h25","fd_delay_pulse_o[1]","LVCMOS25"
"LA25_N","U15","g28","fd_delay_pulse_o[2]","LVCMOS25"
"LA25_P","T15","g27","fd_delay_pulse_o[3]","LVCMOS25"
"LA32_N","A20","h38","fd_delay_val_o[0]","LVCMOS25"
"LA32_P","B20","h37","fd_delay_val_o[1]","LVCMOS25"
"LA33_N","A19","g37","fd_delay_val_o[2]","LVCMOS25"
"LA33_P","C19","g36","fd_delay_val_o[3]","LVCMOS25"
"LA30_N","W18","h35","fd_delay_val_o[4]","LVCMOS25"
"LA30_P","V17","h34","fd_delay_val_o[5]","LVCMOS25"
"LA31_N","C18","g34","fd_delay_val_o[6]","LVCMOS25"
"LA31_P","D17","g33","fd_delay_val_o[7]","LVCMOS25"
"LA28_N","W15","h32","fd_delay_val_o[8]","LVCMOS25"
"LA28_P","Y16","h31","fd_delay_val_o[9]","LVCMOS25"
"LA15_P","V11","h19","fd_led_trig_o","LVCMOS25"
"LA23_N","AB16","d24","fd_spi_cs_dac_n_o","LVCMOS25"
"LA20_P","R11","g21","fd_spi_cs_gpio_n_o","LVCMOS25"
"LA26_N","AB17","d27","fd_spi_cs_pll_n_o","LVCMOS25"
"LA27_N","AB18","c27","fd_spi_miso_i","LVCMOS25"
"LA27_P","AA18","c26","fd_spi_mosi_o","LVCMOS25"
"LA26_P","Y17","d26","fd_spi_sclk_o","LVCMOS25"
"LA18_P","T12","c22","fd_tdc_a_o[0]","LVCMOS25"
"LA18_N","U12","c23","fd_tdc_a_o[1]","LVCMOS25"
"LA19_P","Y15","h22","fd_tdc_a_o[2]","LVCMOS25"
"LA19_N","AB15","h23","fd_tdc_a_o[3]","LVCMOS25"
"LA16_P","W12","g18","fd_tdc_alutrigger_o","LVCMOS25"
"LA20_N","T11","g22","fd_tdc_cs_n_o","LVCMOS25"
"LA01_N","AB12","d9","fd_tdc_d_b[0]","LVCMOS25"
"LA04_N","U8","h11","fd_tdc_d_b[1]","LVCMOS25"
"LA08_P","R9","g12","fd_tdc_d_b[10]","LVCMOS25"
"LA08_N","R8","g13","fd_tdc_d_b[11]","LVCMOS25"
"LA05_P","AA6","d11","fd_tdc_d_b[12]","LVCMOS25"
"LA05_N","AB6","d12","fd_tdc_d_b[13]","LVCMOS25"
"LA07_P","U9","h13","fd_tdc_d_b[14]","LVCMOS25"
"LA07_N","V9","h14","fd_tdc_d_b[15]","LVCMOS25"
"LA09_P","Y7","d14","fd_tdc_d_b[16]","LVCMOS25"
"LA09_N","AB7","d15","fd_tdc_d_b[17]","LVCMOS25"
"LA10_P","AA8","c14","fd_tdc_d_b[18]","LVCMOS25"
"LA10_N","AB8","c15","fd_tdc_d_b[19]","LVCMOS25"
"LA01_P","AA12","d8","fd_tdc_d_b[2]","LVCMOS25"
"LA12_P","T10","g15","fd_tdc_d_b[20]","LVCMOS25"
"LA12_N","U10","g16","fd_tdc_d_b[21]","LVCMOS25"
"LA11_P","W10","h16","fd_tdc_d_b[22]","LVCMOS25"
"LA11_N","Y10","h17","fd_tdc_d_b[23]","LVCMOS25"
"LA13_P","Y9","d17","fd_tdc_d_b[24]","LVCMOS25"
"LA13_N","AB9","d18","fd_tdc_d_b[25]","LVCMOS25"
"LA14_P","AA4","c18","fd_tdc_d_b[26]","LVCMOS25"
"LA14_N","AB4","c19","fd_tdc_d_b[27]","LVCMOS25"
"LA04_P","T8","h10","fd_tdc_d_b[3]","LVCMOS25"
"LA03_N","W8","g10","fd_tdc_d_b[4]","LVCMOS25"
"LA03_P","V7","g9","fd_tdc_d_b[5]","LVCMOS25"
"LA02_N","Y6","h8","fd_tdc_d_b[6]","LVCMOS25"
"LA02_P","W6","h7","fd_tdc_d_b[7]","LVCMOS25"
"LA06_P","Y5","c10","fd_tdc_d_b[8]","LVCMOS25"
"LA06_N","AB5","c11","fd_tdc_d_b[9]","LVCMOS25"
"LA16_N","Y12","g19","fd_tdc_emptyf_i","LVCMOS25"
"LA23_P","AA16","d23","fd_tdc_oe_n_o","LVCMOS25"
"LA17_N","AB13","d21","fd_tdc_rd_n_o","LVCMOS25"
"LA22_P","R13","g24","fd_tdc_start_dis_o","LVCMOS25"
"CLK0_M2C_N","F16","h5","fd_tdc_start_n_i","LVDS_25"
"CLK0_M2C_P","E16","h4","fd_tdc_start_p_i","LVDS_25"
"LA22_N","T14","g25","fd_tdc_stop_dis_o","LVCMOS25"
"LA17_P","Y13","d20","fd_tdc_wr_n_o","LVCMOS25"
"LA00_P","Y11","g6","fd_trig_a_i","LVCMOS25"
"LA00_N","AB11","g7","fd_trig_cal_o","LVCMOS25"
"FMC_SCL","F7","c30","fmc_scl_b","LVCMOS33"
"FMC_SDA","F8","c31","fmc_sda_b","LVCMOS33"
"LA15_N","W11","h20","onewire_b","LVCMOS25"
"DP0_C2M_N","A6","c3",,
"PRSNT_M2C_L","AB14","h2",,
"GBTCLK0_M2C_P","A10","d4",,
"GBTCLK0_M2C_N","B10","d5",,
"DP0_C2M_P","B6","c2",,
"DP0_M2C_P","D7","c6",,
"DP0_M2C_N","C7","c7",,
"PG_C2M ","AA14","d1",,
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